1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37IMAGE ?= temp 38CONFIG ?= DefaultConfig 39NUM_CORES ?= 1 40MFC ?= 1 41 42 43ifeq ($(MAKECMDGOALS),) 44GOALS = verilog 45else 46GOALS = $(MAKECMDGOALS) 47endif 48 49# common chisel args 50ifeq ($(MFC),1) 51CHISEL_VERSION = chisel 52FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 53SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 54MFC_ARGS = --dump-fir --target systemverilog --split-verilog \ 55 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 56RELEASE_ARGS += $(MFC_ARGS) 57DEBUG_ARGS += $(MFC_ARGS) 58PLDM_ARGS += $(MFC_ARGS) 59else 60CHISEL_VERSION = chisel3 61FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 62SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 63endif 64 65ifneq ($(XSTOP_PREFIX),) 66RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 67DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 68PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 69endif 70 71# co-simulation with DRAMsim3 72ifeq ($(WITH_DRAMSIM3),1) 73ifndef DRAMSIM3_HOME 74$(error DRAMSIM3_HOME is not set) 75endif 76override SIM_ARGS += --with-dramsim3 77endif 78 79# run emu with chisel-db 80ifeq ($(WITH_CHISELDB),1) 81override SIM_ARGS += --with-chiseldb 82endif 83 84# run emu with chisel-db 85ifeq ($(WITH_ROLLINGDB),1) 86override SIM_ARGS += --with-rollingdb 87endif 88 89# enable ResetGen 90ifeq ($(WITH_RESETGEN),1) 91override SIM_ARGS += --reset-gen 92endif 93 94# run with disable all perf 95ifeq ($(DISABLE_PERF),1) 96override SIM_ARGS += --disable-perf 97endif 98 99# run with disable all db 100ifeq ($(DISABLE_ALWAYSDB),1) 101override SIM_ARGS += --disable-alwaysdb 102endif 103 104# dynamic switch CONSTANTIN 105ifeq ($(WITH_CONSTANTIN),1) 106override SIM_ARGS += --with-constantin 107endif 108 109# emu for the release version 110RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen 111DEBUG_ARGS += --enable-difftest 112PLDM_ARGS += --fpga-platform --enable-difftest 113ifeq ($(GOALS),verilog) 114RELEASE_ARGS += --disable-always-basic-diff 115endif 116ifeq ($(RELEASE),1) 117override SIM_ARGS += $(RELEASE_ARGS) 118else ifeq ($(PLDM),1) 119override SIM_ARGS += $(PLDM_ARGS) 120else 121override SIM_ARGS += $(DEBUG_ARGS) 122endif 123 124TIMELOG = $(BUILD_DIR)/time.log 125TIME_CMD = time -avp -o $(TIMELOG) 126 127ifeq ($(PLDM),1) 128SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 129SED_ENDIF = `endif // not def SYNTHESIS 130endif 131 132.DEFAULT_GOAL = verilog 133 134help: 135 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help 136 137$(TOP_V): $(SCALA_FILE) 138 mkdir -p $(@D) 139 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \ 140 --target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 141 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 142ifeq ($(MFC),1) 143 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)" 144endif 145 @git log -n 1 >> .__head__ 146 @git diff >> .__diff__ 147 @sed -i 's/^/\/\// ' .__head__ 148 @sed -i 's/^/\/\//' .__diff__ 149 @cat .__head__ .__diff__ $@ > .__out__ 150 @mv .__out__ $@ 151 @rm .__head__ .__diff__ 152 153verilog: $(TOP_V) 154 155$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 156 mkdir -p $(@D) 157 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 158 @date -R | tee -a $(TIMELOG) 159 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 160 --target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 161 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 162ifeq ($(MFC),1) 163 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)" 164endif 165 @git log -n 1 >> .__head__ 166 @git diff >> .__diff__ 167 @sed -i 's/^/\/\// ' .__head__ 168 @sed -i 's/^/\/\//' .__diff__ 169 @cat .__head__ .__diff__ $@ > .__out__ 170 @mv .__out__ $@ 171 @rm .__head__ .__diff__ 172ifeq ($(PLDM),1) 173 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 174 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 175else 176ifeq ($(ENABLE_XPROP),1) 177 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 178else 179 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 180endif 181endif 182ifeq ($(MFC),1) 183 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 184endif 185 186sim-verilog: $(SIM_TOP_V) 187 188clean: 189 $(MAKE) -C ./difftest clean 190 rm -rf $(BUILD_DIR) 191 192init: 193 git submodule update --init 194 cd rocket-chip && git submodule update --init cde hardfloat 195 196bump: 197 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 198 199bsp: 200 mill -i mill.bsp.BSP/install 201 202idea: 203 mill -i mill.scalalib.GenIdea/idea 204 205# verilator simulation 206emu: sim-verilog 207 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 208 209emu-run: emu 210 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 211 212# vcs simulation 213simv: sim-verilog 214 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 215 216simv-run: 217 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 218 219# palladium simulation 220pldm-build: sim-verilog 221 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 222 223pldm-run: 224 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 225 226pldm-debug: 227 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 228 229include Makefile.test 230 231.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 232