1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 9# 10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13# 14# See the Mulan PSL v2 for more details. 15#*************************************************************************************** 16 17TOP = XSTop 18FPGATOP = top.TopMain 19BUILD_DIR = ./build 20TOP_V = $(BUILD_DIR)/$(TOP).v 21SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 22TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 23MEM_GEN = ./scripts/vlsi_mem_gen 24 25SIMTOP = top.SimTop 26IMAGE ?= temp 27CONFIG ?= DefaultConfig 28NUM_CORES ?= 1 29 30# co-simulation with DRAMsim3 31ifeq ($(WITH_DRAMSIM3),1) 32ifndef DRAMSIM3_HOME 33$(error DRAMSIM3_HOME is not set) 34endif 35override SIM_ARGS += --with-dramsim3 36endif 37 38TIMELOG = $(BUILD_DIR)/time.log 39TIME_CMD = time -a -o $(TIMELOG) 40 41.DEFAULT_GOAL = verilog 42 43help: 44 mill XiangShan.test.runMain $(SIMTOP) --help 45 46$(TOP_V): $(SCALA_FILE) 47 mkdir -p $(@D) 48 mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \ 49 --config $(CONFIG) --full-stacktrace --output-file $(@F) \ 50 --disable-all --remove-assert --infer-rw \ 51 --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf \ 52 --gen-mem-verilog full $(SIM_ARGS) \ 53 --num-cores $(NUM_CORES) 54 sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@ 55 @git log -n 1 >> .__head__ 56 @git diff >> .__diff__ 57 @sed -i 's/^/\/\// ' .__head__ 58 @sed -i 's/^/\/\//' .__diff__ 59 @cat .__head__ .__diff__ $@ > .__out__ 60 @mv .__out__ $@ 61 @rm .__head__ .__diff__ 62 63verilog: $(TOP_V) 64 65SIM_TOP = SimTop 66SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v 67$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 68 mkdir -p $(@D) 69 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) 70 @date -R | tee -a $(TIMELOG) 71 $(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D) \ 72 --config $(CONFIG) --full-stacktrace --output-file $(@F) \ 73 --num-cores $(NUM_CORES) $(SIM_ARGS) --infer-rw \ 74 --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf \ 75 --gen-mem-verilog full 76 @git log -n 1 >> .__head__ 77 @git diff >> .__diff__ 78 @sed -i 's/^/\/\// ' .__head__ 79 @sed -i 's/^/\/\//' .__diff__ 80 @cat .__head__ .__diff__ $@ > .__out__ 81 @mv .__out__ $@ 82 @rm .__head__ .__diff__ 83 sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V) 84 85sim-verilog: $(SIM_TOP_V) 86 87clean: 88 $(MAKE) -C ./difftest clean 89 rm -rf ./build 90 91init: 92 git submodule update --init 93 94bump: 95 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 96 97bsp: 98 mill -i mill.bsp.BSP/install 99 100# verilator simulation 101emu: 102 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 103 104emu-run: 105 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 106 107# vcs simulation 108simv: 109 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 110 111.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 112 113