1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40 41SUPPORT_CHI_ISSUE = B E.b 42ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 43$(error "Unsupported CHI issue: $(ISSUE)") 44endif 45 46ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 47$(error At most one target can be specified) 48endif 49 50ifeq ($(MAKECMDGOALS),) 51GOALS = verilog 52else 53GOALS = $(MAKECMDGOALS) 54endif 55 56# common chisel args 57FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 58SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 59MFC_ARGS = --dump-fir --target systemverilog --split-verilog \ 60 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 61RELEASE_ARGS += $(MFC_ARGS) 62DEBUG_ARGS += $(MFC_ARGS) 63PLDM_ARGS += $(MFC_ARGS) 64 65ifneq ($(XSTOP_PREFIX),) 66RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 67DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 68PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 69endif 70 71ifeq ($(IMSIC_USE_TL),1) 72RELEASE_ARGS += --imsic-use-tl 73DEBUG_ARGS += --imsic-use-tl 74PLDM_ARGS += --imsic-use-tl 75endif 76 77# co-simulation with DRAMsim3 78ifeq ($(WITH_DRAMSIM3),1) 79ifndef DRAMSIM3_HOME 80$(error DRAMSIM3_HOME is not set) 81endif 82override SIM_ARGS += --with-dramsim3 83endif 84 85# run emu with chisel-db 86ifeq ($(WITH_CHISELDB),1) 87override SIM_ARGS += --with-chiseldb 88endif 89 90# run emu with chisel-db 91ifeq ($(WITH_ROLLINGDB),1) 92override SIM_ARGS += --with-rollingdb 93endif 94 95# enable ResetGen 96ifeq ($(WITH_RESETGEN),1) 97override SIM_ARGS += --reset-gen 98endif 99 100# run with disable all perf 101ifeq ($(DISABLE_PERF),1) 102override SIM_ARGS += --disable-perf 103endif 104 105# run with disable all db 106ifeq ($(DISABLE_ALWAYSDB),1) 107override SIM_ARGS += --disable-alwaysdb 108endif 109 110# dynamic switch CONSTANTIN 111ifeq ($(WITH_CONSTANTIN),1) 112override SIM_ARGS += --with-constantin 113endif 114 115# emu for the release version 116RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 117DEBUG_ARGS += --enable-difftest 118PLDM_ARGS += --fpga-platform --enable-difftest 119ifeq ($(RELEASE),1) 120override SIM_ARGS += $(RELEASE_ARGS) 121else ifeq ($(PLDM),1) 122override SIM_ARGS += $(PLDM_ARGS) 123else 124override SIM_ARGS += $(DEBUG_ARGS) 125endif 126 127TIMELOG = $(BUILD_DIR)/time.log 128TIME_CMD = time -avp -o $(TIMELOG) 129 130ifeq ($(PLDM),1) 131SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 132SED_ENDIF = `endif // not def SYNTHESIS 133endif 134 135.DEFAULT_GOAL = verilog 136 137help: 138 mill -i xiangshan.runMain $(FPGATOP) --help 139 140version: 141 mill -i xiangshan.runMain $(FPGATOP) --version 142 143jar: 144 mill -i xiangshan.assembly 145 146test-jar: 147 mill -i xiangshan.test.assembly 148 149$(TOP_V): $(SCALA_FILE) 150 mkdir -p $(@D) 151 $(TIME_CMD) mill -i xiangshan.runMain $(FPGATOP) \ 152 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 153 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 154 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 155 @git log -n 1 >> .__head__ 156 @git diff >> .__diff__ 157 @sed -i 's/^/\/\// ' .__head__ 158 @sed -i 's/^/\/\//' .__diff__ 159 @cat .__head__ .__diff__ $@ > .__out__ 160 @mv .__out__ $@ 161 @rm .__head__ .__diff__ 162 163verilog: $(TOP_V) 164 165$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 166 mkdir -p $(@D) 167 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 168 @date -R | tee -a $(TIMELOG) 169 $(TIME_CMD) mill -i xiangshan.test.runMain $(SIMTOP) \ 170 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 171 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 172 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 173 @git log -n 1 >> .__head__ 174 @git diff >> .__diff__ 175 @sed -i 's/^/\/\// ' .__head__ 176 @sed -i 's/^/\/\//' .__diff__ 177 @cat .__head__ .__diff__ $@ > .__out__ 178 @mv .__out__ $@ 179 @rm .__head__ .__diff__ 180ifeq ($(PLDM),1) 181 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 182 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 183else 184ifeq ($(ENABLE_XPROP),1) 185 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 186else 187 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 188endif 189endif 190 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 191 192sim-verilog: $(SIM_TOP_V) 193 194clean: 195 $(MAKE) -C ./difftest clean 196 rm -rf $(BUILD_DIR) 197 198init: 199 git submodule update --init 200 cd rocket-chip && git submodule update --init cde hardfloat 201 cd openLLC && git submodule update --init openNCB 202 203bump: 204 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 205 206bsp: 207 mill -i mill.bsp.BSP/install 208 209idea: 210 mill -i mill.idea.GenIdea/idea 211 212# verilator simulation 213emu: sim-verilog 214 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 215 216emu-run: emu 217 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 218 219# vcs simulation 220simv: sim-verilog 221 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 222 223simv-run: 224 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 225 226# palladium simulation 227pldm-build: sim-verilog 228 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 229 230pldm-run: 231 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 232 233pldm-debug: 234 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 235 236include Makefile.test 237 238include src/main/scala/device/standalone/standalone_device.mk 239 240.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 241