1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 9# 10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13# 14# See the Mulan PSL v2 for more details. 15#*************************************************************************************** 16 17BUILD_DIR = ./build 18RTL_DIR = $(BUILD_DIR)/rtl 19 20TOP = XSTop 21SIM_TOP = SimTop 22 23FPGATOP = top.TopMain 24SIMTOP = top.SimTop 25 26TOP_V = $(RTL_DIR)/$(TOP).v 27SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).v 28 29SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 30TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 31 32MEM_GEN = ./scripts/vlsi_mem_gen 33MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 34SPLIT_VERILOG = ./scripts/split_verilog.sh 35 36IMAGE ?= temp 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39MFC ?= 1 40 41 42ifeq ($(MAKECMDGOALS),) 43GOALS = verilog 44else 45GOALS = $(MAKECMDGOALS) 46endif 47 48# common chisel args 49ifeq ($(MFC),1) 50CHISEL_VERSION = chisel 51FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf" 52SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf" 53MFC_ARGS = --dump-fir --target verilog \ 54 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 55RELEASE_ARGS += $(MFC_ARGS) 56DEBUG_ARGS += $(MFC_ARGS) 57PLDM_ARGS += $(MFC_ARGS) 58else 59CHISEL_VERSION = chisel3 60FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 61SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 62endif 63 64ifneq ($(XSTOP_PREFIX),) 65RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 66DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 67PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 68endif 69 70# co-simulation with DRAMsim3 71ifeq ($(WITH_DRAMSIM3),1) 72ifndef DRAMSIM3_HOME 73$(error DRAMSIM3_HOME is not set) 74endif 75override SIM_ARGS += --with-dramsim3 76endif 77 78# run emu with chisel-db 79ifeq ($(WITH_CHISELDB),1) 80override SIM_ARGS += --with-chiseldb 81endif 82 83# run emu with chisel-db 84ifeq ($(WITH_ROLLINGDB),1) 85override SIM_ARGS += --with-rollingdb 86endif 87 88# run with disable all db 89ifeq ($(DISABLE_ALWAYSDB),1) 90override SIM_ARGS += --disable-alwaysdb 91endif 92 93# dynamic switch CONSTANTIN 94ifeq ($(WITH_CONSTANTIN),1) 95override SIM_ARGS += --with-constantin 96endif 97 98# emu for the release version 99RELEASE_ARGS += --fpga-platform --disable-all --remove-assert 100DEBUG_ARGS += --enable-difftest 101PLDM_ARGS += --fpga-platform --enable-difftest 102ifeq ($(GOALS),verilog) 103RELEASE_ARGS += --disable-always-basic-diff 104endif 105ifeq ($(RELEASE),1) 106override SIM_ARGS += $(RELEASE_ARGS) 107else ifeq ($(PLDM),1) 108override SIM_ARGS += $(PLDM_ARGS) 109else 110override SIM_ARGS += $(DEBUG_ARGS) 111endif 112 113TIMELOG = $(BUILD_DIR)/time.log 114TIME_CMD = time -a -o $(TIMELOG) 115 116SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' 117 118ifeq ($(PLDM),1) 119SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 120SED_ENDIF = `endif // not def SYNTHESIS 121endif 122 123.DEFAULT_GOAL = verilog 124 125help: 126 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help 127 128$(TOP_V): $(SCALA_FILE) 129 mkdir -p $(@D) 130 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \ 131 -td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 132 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 133ifeq ($(MFC),1) 134 $(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v 135 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)" 136endif 137 $(SED_CMD) $@ 138 @git log -n 1 >> .__head__ 139 @git diff >> .__diff__ 140 @sed -i 's/^/\/\// ' .__head__ 141 @sed -i 's/^/\/\//' .__diff__ 142 @cat .__head__ .__diff__ $@ > .__out__ 143 @mv .__out__ $@ 144 @rm .__head__ .__diff__ 145 146verilog: $(TOP_V) 147 148$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 149 mkdir -p $(@D) 150 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) 151 @date -R | tee -a $(TIMELOG) 152 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 153 -td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 154 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 155ifeq ($(MFC),1) 156 $(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v 157 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)" 158endif 159 $(SED_CMD) $@ 160 @git log -n 1 >> .__head__ 161 @git diff >> .__diff__ 162 @sed -i 's/^/\/\// ' .__head__ 163 @sed -i 's/^/\/\//' .__diff__ 164 @cat .__head__ .__diff__ $@ > .__out__ 165 @mv .__out__ $@ 166 @rm .__head__ .__diff__ 167ifeq ($(PLDM),1) 168 sed -i -e 's/$$fatal/$$finish/g' $(SIM_TOP_V) 169 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(SIM_TOP_V) 170else 171 sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V) 172endif 173ifeq ($(MFC),1) 174 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V) 175endif 176 177sim-verilog: $(SIM_TOP_V) 178 179clean: 180 $(MAKE) -C ./difftest clean 181 rm -rf $(BUILD_DIR) 182 183init: 184 git submodule update --init 185 cd rocket-chip && git submodule update --init cde hardfloat 186 187bump: 188 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 189 190bsp: 191 mill -i mill.bsp.BSP/install 192 193idea: 194 mill -i mill.scalalib.GenIdea/idea 195 196# verilator simulation 197emu: sim-verilog 198 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 199 200emu-run: emu 201 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 202 203# vcs simulation 204simv: sim-verilog 205 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 206 207# palladium simulation 208pldm-build: sim-verilog 209 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 210 211pldm-run: 212 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 213 214pldm-debug: 215 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 216 217include Makefile.test 218 219.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 220