xref: /XiangShan/Makefile (revision 4176c33937a5547113be7a0c2411a74f09cc2dfd) 
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8#          http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13#
14# See the Mulan PSL v2 for more details.
15#***************************************************************************************
16
17BUILD_DIR = ./build
18RTL_DIR = $(BUILD_DIR)/rtl
19
20TOP = XSTop
21SIM_TOP = SimTop
22
23FPGATOP = top.TopMain
24SIMTOP  = top.SimTop
25
26TOP_V = $(RTL_DIR)/$(TOP).v
27SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).v
28
29SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
30TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
31
32MEM_GEN = ./scripts/vlsi_mem_gen
33MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
34SPLIT_VERILOG = ./scripts/split_verilog.sh
35
36IMAGE  ?= temp
37CONFIG ?= DefaultConfig
38NUM_CORES ?= 1
39MFC ?= 0
40
41# common chisel args
42ifeq ($(MFC),1)
43CHISEL_VERSION = chisel
44FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf"
45SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf"
46MFC_ARGS = --dump-fir \
47           --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing"
48RELEASE_ARGS += $(MFC_ARGS)
49DEBUG_ARGS += $(MFC_ARGS)
50PLDM_ARGS += $(MFC_ARGS)
51else
52CHISEL_VERSION = chisel3
53FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
54SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
55endif
56
57ifneq ($(XSTOP_PREFIX),)
58RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX)
59DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX)
60PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX)
61endif
62
63# co-simulation with DRAMsim3
64ifeq ($(WITH_DRAMSIM3),1)
65ifndef DRAMSIM3_HOME
66$(error DRAMSIM3_HOME is not set)
67endif
68override SIM_ARGS += --with-dramsim3
69endif
70
71# run emu with chisel-db
72ifeq ($(WITH_CHISELDB),1)
73override SIM_ARGS += --with-chiseldb
74endif
75
76# run emu with chisel-db
77ifeq ($(WITH_ROLLINGDB),1)
78override SIM_ARGS += --with-rollingdb
79endif
80
81# dynamic switch CONSTANTIN
82ifeq ($(WITH_CONSTANTIN),0)
83$(info disable WITH_CONSTANTIN)
84else
85override SIM_ARGS += --with-constantin
86endif
87
88# emu for the release version
89RELEASE_ARGS += --disable-all --remove-assert --fpga-platform
90DEBUG_ARGS   += --enable-difftest
91PLDM_ARGS += --disable-all --fpga-platform --enable-difftest
92ifeq ($(RELEASE),1)
93override SIM_ARGS += $(RELEASE_ARGS)
94else ifeq ($(PLDM),1)
95override SIM_ARGS += $(PLDM_ARGS)
96else
97override SIM_ARGS += $(DEBUG_ARGS)
98endif
99
100TIMELOG = $(BUILD_DIR)/time.log
101TIME_CMD = time -a -o $(TIMELOG)
102
103SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
104
105ifeq ($(PLDM),1)
106SED_IFNDEF = `ifndef SYNTHESIS	// src/main/scala/device/RocketDebugWrapper.scala
107SED_ENDIF  = `endif // not def SYNTHESIS
108endif
109
110.DEFAULT_GOAL = verilog
111
112help:
113	mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
114
115$(TOP_V): $(SCALA_FILE)
116	mkdir -p $(@D)
117	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP)   \
118		-td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS)                    \
119		--num-cores $(NUM_CORES) $(RELEASE_ARGS)
120ifeq ($(MFC),1)
121	$(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v
122	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)"
123endif
124	$(SED_CMD) $@
125	@git log -n 1 >> .__head__
126	@git diff >> .__diff__
127	@sed -i 's/^/\/\// ' .__head__
128	@sed -i 's/^/\/\//' .__diff__
129	@cat .__head__ .__diff__ $@ > .__out__
130	@mv .__out__ $@
131	@rm .__head__ .__diff__
132
133verilog: $(TOP_V)
134
135$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
136	mkdir -p $(@D)
137	@echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
138	@date -R | tee -a $(TIMELOG)
139	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP)    \
140		-td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS)                          \
141		--num-cores $(NUM_CORES) $(SIM_ARGS)
142ifeq ($(MFC),1)
143	$(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v
144	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)"
145endif
146	$(SED_CMD) $@
147	@git log -n 1 >> .__head__
148	@git diff >> .__diff__
149	@sed -i 's/^/\/\// ' .__head__
150	@sed -i 's/^/\/\//' .__diff__
151	@cat .__head__ .__diff__ $@ > .__out__
152	@mv .__out__ $@
153	@rm .__head__ .__diff__
154ifeq ($(PLDM),1)
155	sed -i -e 's/$$fatal/$$finish/g' $(SIM_TOP_V)
156	sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(SIM_TOP_V)
157else
158	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
159endif
160ifeq ($(MFC),1)
161	sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V)
162endif
163
164sim-verilog: $(SIM_TOP_V)
165
166clean:
167	$(MAKE) -C ./difftest clean
168	rm -rf $(BUILD_DIR)
169
170init:
171	git submodule update --init
172	cd rocket-chip && git submodule update --init cde hardfloat
173
174bump:
175	git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
176
177bsp:
178	mill -i mill.bsp.BSP/install
179
180idea:
181	mill -i mill.scalalib.GenIdea/idea
182
183# verilator simulation
184emu: sim-verilog
185	$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
186
187emu-run: emu
188	$(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
189
190# vcs simulation
191simv: sim-verilog
192	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
193
194# palladium simulation
195pldm-build: sim-verilog
196	$(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
197
198pldm-run:
199	$(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
200
201pldm-debug:
202	$(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
203
204include Makefile.test
205
206.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)
207