1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69 70# prefix of XSTop or XSNoCTop 71ifneq ($(XSTOP_PREFIX),) 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 80# L2 cache size in KB 81ifneq ($(L2_CACHE_SIZE),) 82COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 83endif 84 85# L3 cache size in KB 86ifneq ($(L3_CACHE_SIZE),) 87COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 88endif 89 90# configuration from yaml file 91ifneq ($(YAML_CONFIG),) 92COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 93endif 94 95# public args sumup 96RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 97DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 98override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 99 100# co-simulation with DRAMsim3 101ifeq ($(WITH_DRAMSIM3),1) 102ifndef DRAMSIM3_HOME 103$(error DRAMSIM3_HOME is not set) 104endif 105override SIM_ARGS += --with-dramsim3 106endif 107 108# run emu with chisel-db 109ifeq ($(WITH_CHISELDB),1) 110override SIM_ARGS += --with-chiseldb 111endif 112 113# run emu with chisel-db 114ifeq ($(WITH_ROLLINGDB),1) 115override SIM_ARGS += --with-rollingdb 116endif 117 118# enable ResetGen 119ifeq ($(WITH_RESETGEN),1) 120override SIM_ARGS += --reset-gen 121endif 122 123# run with disable all perf 124ifeq ($(DISABLE_PERF),1) 125override SIM_ARGS += --disable-perf 126endif 127 128# run with disable all db 129ifeq ($(DISABLE_ALWAYSDB),1) 130override SIM_ARGS += --disable-alwaysdb 131endif 132 133# dynamic switch CONSTANTIN 134ifeq ($(WITH_CONSTANTIN),1) 135override SIM_ARGS += --with-constantin 136endif 137 138# emu for the release version 139RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 140DEBUG_ARGS += --enable-difftest 141override PLDM_ARGS += --enable-difftest 142ifeq ($(RELEASE),1) 143override SIM_ARGS += $(RELEASE_ARGS) 144else ifeq ($(PLDM),1) 145override SIM_ARGS += $(PLDM_ARGS) 146else 147override SIM_ARGS += $(DEBUG_ARGS) 148endif 149 150# use RELEASE_ARGS for TopMain by default 151ifeq ($(PLDM), 1) 152TOPMAIN_ARGS += $(PLDM_ARGS) 153else 154TOPMAIN_ARGS += $(RELEASE_ARGS) 155endif 156 157TIMELOG = $(BUILD_DIR)/time.log 158TIME_CMD = time -avp -o $(TIMELOG) 159 160ifeq ($(PLDM),1) 161SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 162SED_ENDIF = `endif // not def SYNTHESIS 163endif 164 165.DEFAULT_GOAL = verilog 166 167help: 168 mill -i xiangshan.runMain $(FPGATOP) --help 169 170version: 171 mill -i xiangshan.runMain $(FPGATOP) --version 172 173jar: 174 mill -i xiangshan.assembly 175 176test-jar: 177 mill -i xiangshan.test.assembly 178 179$(TOP_V): $(SCALA_FILE) 180 mkdir -p $(@D) 181 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 182 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 183 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 184ifeq ($(CHISEL_TARGET),systemverilog) 185 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 186 @git log -n 1 >> .__head__ 187 @git diff >> .__diff__ 188 @sed -i 's/^/\/\// ' .__head__ 189 @sed -i 's/^/\/\//' .__diff__ 190 @cat .__head__ .__diff__ $@ > .__out__ 191 @mv .__out__ $@ 192 @rm .__head__ .__diff__ 193endif 194 195verilog: $(TOP_V) 196 197$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 198 mkdir -p $(@D) 199 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 200 @date -R | tee -a $(TIMELOG) 201 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 202 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 203 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 204ifeq ($(CHISEL_TARGET),systemverilog) 205 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 206 @git log -n 1 >> .__head__ 207 @git diff >> .__diff__ 208 @sed -i 's/^/\/\// ' .__head__ 209 @sed -i 's/^/\/\//' .__diff__ 210 @cat .__head__ .__diff__ $@ > .__out__ 211 @mv .__out__ $@ 212 @rm .__head__ .__diff__ 213ifeq ($(PLDM),1) 214 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 215 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 216else 217ifeq ($(ENABLE_XPROP),1) 218 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 219else 220 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 221endif 222endif 223 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 224endif 225 226sim-verilog: $(SIM_TOP_V) 227 228clean: 229 $(MAKE) -C ./difftest clean 230 rm -rf $(BUILD_DIR) 231 232init: 233 git submodule update --init 234 cd rocket-chip && git submodule update --init cde hardfloat 235 cd openLLC && git submodule update --init openNCB 236 237bump: 238 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 239 240bsp: 241 mill -i mill.bsp.BSP/install 242 243idea: 244 mill -i mill.idea.GenIdea/idea 245 246check-format: 247 mill xiangshan.checkFormat 248 249reformat: 250 mill xiangshan.reformat 251 252# verilator simulation 253emu: sim-verilog 254 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 255 256emu-run: emu 257 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 258 259# vcs simulation 260simv: sim-verilog 261 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 262 263simv-run: 264 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 265 266# palladium simulation 267pldm-build: sim-verilog 268 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 269 270pldm-run: 271 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 272 273pldm-debug: 274 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 275 276include Makefile.test 277 278include src/main/scala/device/standalone/standalone_device.mk 279 280.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 281