1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 9# 10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13# 14# See the Mulan PSL v2 for more details. 15#*************************************************************************************** 16 17TOP = XSTop 18FPGATOP = top.TopMain 19BUILD_DIR = ./build 20TOP_V = $(BUILD_DIR)/$(TOP).v 21SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 22TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 23MEM_GEN = ./scripts/vlsi_mem_gen 24 25SIMTOP = top.SimTop 26IMAGE ?= temp 27CONFIG ?= DefaultConfig 28NUM_CORES ?= 1 29 30# co-simulation with DRAMsim3 31ifeq ($(WITH_DRAMSIM3),1) 32ifndef DRAMSIM3_HOME 33$(error DRAMSIM3_HOME is not set) 34endif 35override SIM_ARGS += --with-dramsim3 36endif 37 38# emu for the release version 39RELEASE_ARGS = --disable-all --remove-assert --fpga-platform 40DEBUG_ARGS = --enable-difftest 41ifeq ($(RELEASE),1) 42override SIM_ARGS += $(RELEASE_ARGS) 43else 44override SIM_ARGS += $(DEBUG_ARGS) 45endif 46 47TIMELOG = $(BUILD_DIR)/time.log 48TIME_CMD = time -a -o $(TIMELOG) 49 50.DEFAULT_GOAL = verilog 51 52help: 53 mill XiangShan.test.runMain $(SIMTOP) --help 54 55$(TOP_V): $(SCALA_FILE) 56 mkdir -p $(@D) 57 mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \ 58 --config $(CONFIG) --full-stacktrace --output-file $(@F) \ 59 --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --infer-rw \ 60 --gen-mem-verilog full --num-cores $(NUM_CORES) \ 61 $(RELEASE_ARGS) 62 sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@ 63 @git log -n 1 >> .__head__ 64 @git diff >> .__diff__ 65 @sed -i 's/^/\/\// ' .__head__ 66 @sed -i 's/^/\/\//' .__diff__ 67 @cat .__head__ .__diff__ $@ > .__out__ 68 @mv .__out__ $@ 69 @rm .__head__ .__diff__ 70 71verilog: $(TOP_V) 72 73SIM_TOP = SimTop 74SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v 75$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 76 mkdir -p $(@D) 77 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) 78 @date -R | tee -a $(TIMELOG) 79 $(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D) \ 80 --config $(CONFIG) --full-stacktrace --output-file $(@F) \ 81 --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --infer-rw \ 82 --gen-mem-verilog full --num-cores $(NUM_CORES) \ 83 $(SIM_ARGS) 84 @git log -n 1 >> .__head__ 85 @git diff >> .__diff__ 86 @sed -i 's/^/\/\// ' .__head__ 87 @sed -i 's/^/\/\//' .__diff__ 88 @cat .__head__ .__diff__ $@ > .__out__ 89 @mv .__out__ $@ 90 @rm .__head__ .__diff__ 91 sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V) 92 93sim-verilog: $(SIM_TOP_V) 94 95clean: 96 $(MAKE) -C ./difftest clean 97 rm -rf ./build 98 99init: 100 git submodule update --init 101 102bump: 103 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 104 105bsp: 106 mill -i mill.bsp.BSP/install 107 108# verilator simulation 109emu: 110 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 111 112emu-run: 113 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 114 115# vcs simulation 116simv: 117 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 118 119.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 120 121