1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef HANDOFF_H 8 #define HANDOFF_H 9 10 #define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ 11 #define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ 12 #define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ 13 #define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ 14 #define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ 15 #define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ 16 #define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ 17 #define HANDOFF_MAGIC_PERIPHERAL 0x50455249 /* PERIPHERAL */ 18 #define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */ 19 20 #include <socfpga_plat_def.h> 21 22 typedef struct handoff_t { 23 /* header */ 24 uint32_t header_magic; 25 uint32_t header_device; 26 uint32_t _pad_0x08_0x10[2]; 27 28 /* pinmux configuration - select */ 29 uint32_t pinmux_sel_magic; 30 uint32_t pinmux_sel_length; 31 uint32_t _pad_0x18_0x20[2]; 32 uint32_t pinmux_sel_array[96]; /* offset, value */ 33 34 /* pinmux configuration - io control */ 35 uint32_t pinmux_io_magic; 36 uint32_t pinmux_io_length; 37 uint32_t _pad_0x1a8_0x1b0[2]; 38 uint32_t pinmux_io_array[96]; /* offset, value */ 39 40 /* pinmux configuration - use fpga switch */ 41 uint32_t pinmux_fpga_magic; 42 uint32_t pinmux_fpga_length; 43 uint32_t _pad_0x338_0x340[2]; 44 uint32_t pinmux_fpga_array[44]; /* offset, value */ 45 /* TODO: Temp remove due to add in extra handoff data */ 46 // uint32_t _pad_0x3e8_0x3f0[2]; 47 48 /* pinmux configuration - io delay */ 49 uint32_t pinmux_delay_magic; 50 uint32_t pinmux_delay_length; 51 uint32_t _pad_0x3f8_0x400[2]; 52 uint32_t pinmux_iodelay_array[96]; /* offset, value */ 53 54 /* clock configuration */ 55 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 56 uint32_t clock_magic; 57 uint32_t clock_length; 58 uint32_t _pad_0x588_0x590[2]; 59 uint32_t main_pll_mpuclk; 60 uint32_t main_pll_nocclk; 61 uint32_t main_pll_cntr2clk; 62 uint32_t main_pll_cntr3clk; 63 uint32_t main_pll_cntr4clk; 64 uint32_t main_pll_cntr5clk; 65 uint32_t main_pll_cntr6clk; 66 uint32_t main_pll_cntr7clk; 67 uint32_t main_pll_cntr8clk; 68 uint32_t main_pll_cntr9clk; 69 uint32_t main_pll_nocdiv; 70 uint32_t main_pll_pllglob; 71 uint32_t main_pll_fdbck; 72 uint32_t main_pll_pllc0; 73 uint32_t main_pll_pllc1; 74 uint32_t _pad_0x5cc_0x5d0[1]; 75 uint32_t per_pll_cntr2clk; 76 uint32_t per_pll_cntr3clk; 77 uint32_t per_pll_cntr4clk; 78 uint32_t per_pll_cntr5clk; 79 uint32_t per_pll_cntr6clk; 80 uint32_t per_pll_cntr7clk; 81 uint32_t per_pll_cntr8clk; 82 uint32_t per_pll_cntr9clk; 83 uint32_t per_pll_emacctl; 84 uint32_t per_pll_gpiodiv; 85 uint32_t per_pll_pllglob; 86 uint32_t per_pll_fdbck; 87 uint32_t per_pll_pllc0; 88 uint32_t per_pll_pllc1; 89 uint32_t hps_osc_clk_h; 90 uint32_t fpga_clk_hz; 91 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX 92 uint32_t clock_magic; 93 uint32_t clock_length; 94 uint32_t _pad_0x588_0x590[2]; 95 uint32_t main_pll_mpuclk; 96 uint32_t main_pll_nocclk; 97 uint32_t main_pll_nocdiv; 98 uint32_t main_pll_pllglob; 99 uint32_t main_pll_fdbck; 100 uint32_t main_pll_pllc0; 101 uint32_t main_pll_pllc1; 102 uint32_t main_pll_pllc2; 103 uint32_t main_pll_pllc3; 104 uint32_t main_pll_pllm; 105 uint32_t per_pll_emacctl; 106 uint32_t per_pll_gpiodiv; 107 uint32_t per_pll_pllglob; 108 uint32_t per_pll_fdbck; 109 uint32_t per_pll_pllc0; 110 uint32_t per_pll_pllc1; 111 uint32_t per_pll_pllc2; 112 uint32_t per_pll_pllc3; 113 uint32_t per_pll_pllm; 114 uint32_t alt_emacactr; 115 uint32_t alt_emacbctr; 116 uint32_t alt_emacptpctr; 117 uint32_t alt_gpiodbctr; 118 uint32_t alt_sdmmcctr; 119 uint32_t alt_s2fuser0ctr; 120 uint32_t alt_s2fuser1ctr; 121 uint32_t alt_psirefctr; 122 uint32_t hps_osc_clk_h; 123 uint32_t fpga_clk_hz; 124 uint32_t _pad_0x604_0x610[3]; 125 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 126 uint32_t clock_magic; 127 uint32_t clock_length; 128 uint32_t _pad_0x588_0x590[2]; 129 uint32_t main_pll_nocclk; 130 uint32_t main_pll_nocdiv; 131 uint32_t main_pll_pllglob; 132 uint32_t main_pll_fdbck; 133 uint32_t main_pll_pllc0; 134 uint32_t main_pll_pllc1; 135 uint32_t main_pll_pllc2; 136 uint32_t main_pll_pllc3; 137 uint32_t main_pll_pllm; 138 uint32_t per_pll_emacctl; 139 uint32_t per_pll_gpiodiv; 140 uint32_t per_pll_pllglob; 141 uint32_t per_pll_fdbck; 142 uint32_t per_pll_pllc0; 143 uint32_t per_pll_pllc1; 144 uint32_t per_pll_pllc2; 145 uint32_t per_pll_pllc3; 146 uint32_t per_pll_pllm; 147 uint32_t alt_emacactr; 148 uint32_t alt_emacbctr; 149 uint32_t alt_emacptpctr; 150 uint32_t alt_gpiodbctr; 151 uint32_t alt_sdmmcctr; 152 uint32_t alt_s2fuser0ctr; 153 uint32_t alt_s2fuser1ctr; 154 uint32_t alt_psirefctr; 155 /* TODO: Temp added for clk manager. */ 156 uint32_t qspi_clk_khz; 157 uint32_t hps_osc_clk_hz; 158 uint32_t fpga_clk_hz; 159 /* TODO: Temp added for clk manager. */ 160 uint32_t ddr_reset_type; 161 /* TODO: Temp added for clk manager. */ 162 uint32_t hps_status_coldreset; 163 /* TODO: Temp remove due to add in extra handoff data */ 164 //uint32_t _pad_0x604_0x610[3]; 165 #endif 166 /* misc configuration */ 167 uint32_t misc_magic; 168 uint32_t misc_length; 169 uint32_t _pad_0x618_0x620[2]; 170 171 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 172 /* peripheral configuration - select */ 173 uint32_t peripheral_pwr_gate_magic; 174 uint32_t peripheral_pwr_gate_length; 175 uint32_t _pad_0x08_0x0C[2]; 176 uint32_t peripheral_pwr_gate_array; /* offset, value */ 177 178 /* ddr configuration - select */ 179 uint32_t ddr_magic; 180 uint32_t ddr_length; 181 uint32_t _pad_0x1C_0x20[2]; 182 uint32_t ddr_array[4]; /* offset, value */ 183 #endif 184 } handoff; 185 186 int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); 187 int socfpga_get_handoff(handoff *hoff_ptr); 188 189 #endif 190