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/aosp_15_r20/external/llvm/test/CodeGen/AArch64/
H A Darm64-ldxr-stxr.ll99 %res = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr)
109 %res = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr)
117 ; CHECK: stxr w0, w1, [x2]
119 %res = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr)
125 ; CHECK: stxr w0, x1, [x2]
126 %res = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr)
130 declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*) nounwind
131 declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*) nounwind
132 declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*) nounwind
133 declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*) nounwind
H A Darm64-atomic.ll10 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
28 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0]
65 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
124 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
H A Datomic-ops.ll87 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
147 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
247 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
307 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
407 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
483 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]]
557 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
679 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
968 ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
/aosp_15_r20/prebuilts/rust/linux-x86/1.80.1/lib/rustlib/src/rust/vendor/compiler_builtins/src/
H A Daarch64_linux.rs103 macro_rules! stxr { macro
149 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 1), ", [x2]"),
206 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 16), ", [x1]"),
234 concat!(stxr!($ordering, $bytes), " w15, ", reg!($bytes, 17), ", [x1]"),
/aosp_15_r20/prebuilts/rust/linux-x86/1.81.0/lib/rustlib/src/rust/vendor/compiler_builtins/src/
H A Daarch64_linux.rs103 macro_rules! stxr { macro
149 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 1), ", [x2]"),
206 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 16), ", [x1]"),
234 concat!(stxr!($ordering, $bytes), " w15, ", reg!($bytes, 17), ", [x1]"),
/aosp_15_r20/prebuilts/rust/linux-musl-x86/1.81.0/lib/rustlib/src/rust/vendor/compiler_builtins/src/
H A Daarch64_linux.rs103 macro_rules! stxr { macro
149 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 1), ", [x2]"),
206 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 16), ", [x1]"),
234 concat!(stxr!($ordering, $bytes), " w15, ", reg!($bytes, 17), ", [x1]"),
/aosp_15_r20/prebuilts/rust/linux-x86/1.81.0.u1/lib/rustlib/src/rust/vendor/compiler_builtins/src/
H A Daarch64_linux.rs103 macro_rules! stxr { macro
149 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 1), ", [x2]"),
206 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 16), ", [x1]"),
234 concat!(stxr!($ordering, $bytes), " w15, ", reg!($bytes, 17), ", [x1]"),
/aosp_15_r20/prebuilts/rust/linux-musl-x86/1.80.1/lib/rustlib/src/rust/vendor/compiler_builtins/src/
H A Daarch64_linux.rs103 macro_rules! stxr { macro
149 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 1), ", [x2]"),
206 concat!(stxr!($ordering, $bytes), " w17, ", reg!($bytes, 16), ", [x1]"),
234 concat!(stxr!($ordering, $bytes), " w15, ", reg!($bytes, 17), ", [x1]"),
/aosp_15_r20/external/trusty/lk/arch/arm64/
Dspinlock.S32 stxr w0, x1, [x2]
43 stxr w2, x1, [x0]
/aosp_15_r20/art/runtime/arch/arm64/
H A Dasm_support_arm64.S456 stxr w10, w11, [x8]
466 stxr w10, w11, [x8]
508 stxr w10, w11, [x8] // Need to use atomic instructions for read barrier.
H A Dquick_entrypoints_arm64.S2493 stxr w9, w0, [x10]
2504 stxr w9, w0, [x10]
2515 stxr w9, w0, [x10]
2526 stxr w9, w0, [x10]
/aosp_15_r20/external/llvm/test/MC/AArch64/
H A Darm64-memory.s468 stxr w1, x4, [x3]
469 stxr w1, w4, [x3]
475 ; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8]
476 ; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
H A Dbasic-a64-instructions.s2259 stxr wzr, w4, [sp]
2260 stxr w5, x6, [x7]
/aosp_15_r20/external/llvm/test/MC/Disassembler/AArch64/
H A Darm64-canonical-form.txt5 # CHECK: stxr w0, x0, [x0]
H A Darm64-memory.txt456 # CHECK: stxr w1, x4, [x3]
457 # CHECK: stxr w1, w4, [x3]
H A Dbasic-a64-instructions.txt1920 #CHECK: stxr w5, w6, [x17]
1921 #CHECK: stxr w1, x10, [x21]
1922 #CHECK: stxr w1, x10, [x21]
/aosp_15_r20/external/arm-trusted-firmware/lib/locks/exclusive/aarch64/
H A Dspinlock.S56 stxr w1, w2, [x0]
/aosp_15_r20/external/trusty/arm-trusted-firmware/lib/locks/exclusive/aarch64/
Dspinlock.S58 stxr w1, w2, [x0]
/aosp_15_r20/external/trusty/bootloader/test-runner/arm64/
Dasm.S146 stxr w4, xzr, [x0] // skip_cpu0_wfi = 0
/aosp_15_r20/external/vixl/
H A DREADME.md165 `stxrb`, `stxrh`, `stxr`, `ldxrb`, `ldxrh`, `ldxr`, `stxp`, `ldxp`, `stlxrb`,
/aosp_15_r20/external/vixl/test/aarch64/
H A Dtest-disasm-aarch64.cc1585 COMPARE(stxr(w20, w21, MemOperand(x22)), "stxr w20, w21, [x22]"); in TEST()
1586 COMPARE(stxr(x23, w24, MemOperand(sp)), "stxr w23, w24, [sp]"); in TEST()
1587 COMPARE(stxr(w25, x26, MemOperand(x27)), "stxr w25, x26, [x27]"); in TEST()
1588 COMPARE(stxr(x28, x29, MemOperand(sp)), "stxr w28, x29, [sp]"); in TEST()
H A Dtest-trace-aarch64.cc340 __ stxr(w12, w13, MemOperand(x0)); in GenerateTestSequenceBase() local
341 __ stxr(x14, x15, MemOperand(x0)); in GenerateTestSequenceBase() local
/aosp_15_r20/external/capstone/suite/MC/AArch64/
H A Dbasic-a64-instructions.s.cs878 0xe4,0x7f,0x1f,0x88 = stxr wzr, w4, [sp]
879 0xe6,0x7c,0x05,0xc8 = stxr w5, x6, [x7]
/aosp_15_r20/external/vixl/test/test-trace-reference/
H A Dlog-disasm284 0x~~~~~~~~~~~~~~~~ 880c7c0d stxr w12, w13, [x0]
285 0x~~~~~~~~~~~~~~~~ c80e7c0f stxr w14, x15, [x0]
H A Dlog-disasm-colour284 0x~~~~~~~~~~~~~~~~ 880c7c0d stxr w12, w13, [x0]
285 0x~~~~~~~~~~~~~~~~ c80e7c0f stxr w14, x15, [x0]

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