| /aosp_15_r20/external/llvm/test/MC/AArch64/ |
| H A D | armv8.1a-lor.s | 17 stllrh w0,[x1]
39 stllrh x0,[x1]
|
| /aosp_15_r20/external/llvm/test/MC/Disassembler/AArch64/ |
| H A D | armv8.1a-lor.txt | 16 # CHECK: stllrh w0, [x1]
|
| /aosp_15_r20/external/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 1657 COMPARE(stllrh(w13, MemOperand(x14)), "stllrh w13, [x14]"); in TEST()
1658 COMPARE(stllrh(w15, MemOperand(sp)), "stllrh w15, [sp]"); in TEST()
1659 COMPARE(stllrh(x16, MemOperand(x17)), "stllrh w16, [x17]"); in TEST()
1660 COMPARE(stllrh(x18, MemOperand(sp)), "stllrh w18, [sp]"); in TEST()
|
| H A D | test-cpu-features-aarch64.cc | 3526 TEST_LOREGIONS(stllrh_0, stllrh(w0, MemOperand(x1, 0)))
|
| /aosp_15_r20/external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 1372 void stllrh(const Register& rt, const MemOperand& dst);
|
| H A D | assembler-aarch64.cc | 1605 void Assembler::stllrh(const Register& rt, const MemOperand& dst) { in stllrh() function in vixl::aarch64::Assembler
|
| H A D | macro-assembler-aarch64.h | 2401 stllrh(rt, dst); in Stllrh()
|
| /aosp_15_r20/out/soong/.intermediates/external/llvm/lib/Target/AArch64/llvm-gen-aarch64/gen/ |
| D | AArch64GenAsmMatcher.inc | 6222 "\007steorlb\007steorlh\005stllr\006stllrb\006stllrh\004stlr\005stlrb\005"
9589 …{ 3057 /* stllrh */, AArch64::STLLRH, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR32,…
13634 …{ 3057 /* stllrh */, AArch64::STLLRH, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR32,…
14681 { Feature_HasV8_1a, 3057 /* stllrh */, MCK_GPR64sp0, 4 /* 2 */ },
14682 { Feature_HasV8_1a, 3057 /* stllrh */, MCK_GPR64sp0, 4 /* 2 */ },
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 4036 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
4042 def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]", (STLLRH GPR32: $Rt, GPR64sp:$Rn)>;
|
| /aosp_15_r20/external/vixl/doc/aarch64/ |
| H A D | supported-instructions-aarch64.md | 2527 void stllrh(const Register& rt, const MemOperand& dst)
|
| /aosp_15_r20/external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 2486 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 3295 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| H A D | AArch64GenAsmMatcher.inc | 12586 "stllrb\006stllrh\004stlr\005stlrb\005stlrh\005stlur\006stlurb\006stlurh"
18747 …{ 5491 /* stllrh */, AArch64::STLLRH, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK…
26120 …{ 5491 /* stllrh */, AArch64::STLLRH, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK…
38697 { 5491 /* stllrh */, 4 /* 2 */, MCK_GPR64sp0, AMFBS_HasLOR },
38698 { 5491 /* stllrh */, 4 /* 2 */, MCK_GPR64sp0, AMFBS_HasLOR },
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/AArch64/ |
| H A D | AArch64GenAsmMatcher.inc | 19044 "stilp\004stl1\005stllr\006stllrb\006stllrh\004stlr\005stlrb\005stlrh\005"
26904 …{ 7702 /* stllrh */, AArch64::STLLRH, Convert__Reg1_0__Reg1_2, AMFBS_HasLOR, { MCK_GPR32, MCK__91_…
26905 …{ 7702 /* stllrh */, AArch64::STLLRH, Convert__Reg1_0__Reg1_2, AMFBS_HasLOR, { MCK_GPR32, MCK__91_…
36434 …{ 7702 /* stllrh */, AArch64::STLLRH, Convert__Reg1_0__Reg1_2, AMFBS_HasLOR, { MCK_GPR32, MCK__91_…
36435 …{ 7702 /* stllrh */, AArch64::STLLRH, Convert__Reg1_0__Reg1_2, AMFBS_HasLOR, { MCK_GPR32, MCK__91_…
|