| /aosp_15_r20/external/tensorflow/tensorflow/python/ops/ragged/ |
| H A D | ragged_tensor_test.py | 80 rt2 = RaggedTensor.from_row_lengths(values, row_lengths=[4, 0, 3, 1, 0])
85 for rt in (rt1, rt2, rt3, rt4, rt5):
87 del rt1, rt2, rt3, rt4, rt5
310 rt2 = RaggedTensor.from_row_splits(values, splits2)
315 self.assertEqual(rt2.row_splits.dtype, dtypes.int64)
387 rt2 = RaggedTensor.from_row_lengths(rt, [2, 1, 0])
388 self.assertAllEqual([2, 1, 0], rt2.row_lengths())
436 rt2 = RaggedTensor.from_uniform_row_length(ph_values, ph_rowlen)
439 self.assertAllEqual(rt2, [[1, 2, 3], [4, 5, 6]])
443 self.assertEqual(rt2.shape.as_list(), [2, 3])
[all …]
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| H A D | ragged_range_op_test.py | 31 rt2 = ragged_math_ops.range([0, 5, 8], [3, 3, 12])
32 self.assertAllEqual(rt2, [[0, 1, 2], [], [8, 9, 10, 11]])
91 rt2 = ragged_math_ops.range([0, 5, 5], [0, 3, 5], -1)
93 self.assertAllEqual(rt2, [[], [5, 4], []])
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| H A D | ragged_to_sparse_op_test.py | 184 rt2 = ragged_factory_ops.constant(
186 rt = ragged_functional_ops.map_flat_values(math_ops.add, rt1, rt2 * 2.0)
190 [rt1.flat_values, rt2.flat_values])
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| /aosp_15_r20/frameworks/compile/mclinker/lib/Target/AArch64/ |
| D | AArch64InsnHelpers.h | 161 unsigned& rt2, in isMemOp() argument
175 rt2 = rt; in isMemOp()
178 rt2 = getRt2(insn); in isMemOp()
187 rt2 = getRt2(insn); in isMemOp()
198 rt2 = rt; in isMemOp()
218 rt2 = rt + 3; in isMemOp()
223 rt2 = rt + 2; in isMemOp()
227 rt2 = rt; in isMemOp()
232 rt2 = rt + 1; in isMemOp()
249 rt2 = rt + r; in isMemOp()
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| D | AArch64CA53Erratum835769Stub.cpp | 48 unsigned rt2; in isMyDuty() local
55 AArch64InsnHelpers::isMemOp(code.insns[0], rt, rt2, is_pair, is_load)) { in isMyDuty()
73 (is_pair && ((rt2 == ra) || (rt2 == rm) || (rt2 == rn))))) { in isMyDuty()
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| D | AArch64CA53Erratum843419Stub.cpp | 52 unsigned rt2; in isErratum843419Sequence() local
55 return AArch64InsnHelpers::isMemOp(insn2, rt, rt2, is_pair, is_load) && in isErratum843419Sequence()
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| /aosp_15_r20/external/rust/android-crates-io/crates/tokio/tests/ |
| D | rt_handle.rs | 11 let rt2 = rt(); in basic_enter() localVariable
14 let enter2 = rt2.enter(); in basic_enter()
25 let rt2 = rt(); in interleave_enter_different_rt() localVariable
28 let enter2 = rt2.enter(); in interleave_enter_different_rt()
54 let rt2 = rt(); in interleave_then_enter() localVariable
57 let enter2 = rt2.enter(); in interleave_then_enter()
85 let rt2 = rt(); in runtime_ids_different() localVariable
87 assert_ne!(rt1.handle().id(), rt2.handle().id()); in runtime_ids_different()
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| D | rt_basic.rs | 340 let rt2 = rt1.clone(); in spawns_do_nothing() localVariable
343 rt2.block_on(async { in spawns_do_nothing()
411 let rt2 = tokio::runtime::Builder::new_current_thread() in rng_seed() localVariable
415 let rt2_values = rt2.block_on(async { in rng_seed()
443 let rt2 = tokio::runtime::Builder::new_current_thread() in rng_seed_multi_enter() localVariable
447 let rt2_values_1 = rt2.block_on(async { two_rand_values() }); in rng_seed_multi_enter()
448 let rt2_values_2 = rt2.block_on(async { two_rand_values() }); in rng_seed_multi_enter()
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| /aosp_15_r20/prebuilts/go/linux-x86/src/net/http/ |
| D | transport_dial_test.go | 27 rt2 := dt.roundTrip()
28 rt2.wantDone(c1)
29 rt2.finish()
43 rt2 := dt.roundTrip()
46 rt2.wantDone(c2)
61 rt2 := dt.roundTrip()
64 rt2.wantDone(c1)
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| /aosp_15_r20/external/e2fsprogs/lib/ss/ |
| H A D | request_tbl.c | 55 register ssrt **rt1, **rt2; in ss_delete_request_table() local
60 for (rt2 = rt1; *rt1; rt1++) { in ss_delete_request_table()
62 *rt2++ = *rt1; in ss_delete_request_table()
66 *rt2 = (ssrt *)NULL; in ss_delete_request_table()
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| /aosp_15_r20/external/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.cc | 1677 Register rt2, in Delegate() argument
1686 temps.Include(rt, rt2); in Delegate()
1689 ldrd(rt, rt2, MemOperandComputationHelper(cond, scratch, location, mask)); in Delegate()
1693 Assembler::Delegate(type, instruction, cond, rt, rt2, location); in Delegate()
1898 Register rt2, in Delegate() argument
1919 if (((rt.GetCode() + 1) % kNumberOfRegisters) != rt2.GetCode()) { in Delegate()
1950 if (!rt2.Is(rn)) temps.Include(rt2); in Delegate()
1965 rt2, in Delegate()
1975 if (!rt2.Is(rn)) temps.Include(rt2); in Delegate()
1990 rt2, in Delegate()
[all …]
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| /aosp_15_r20/external/llvm/test/Verifier/ |
| H A D | recursive-type-3.ll | 3 %rt2 = type { i32, { i8, %rt2*, i8 }, i32 }
9 %0 = alloca %rt2
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| H A D | recursive-type-1.ll | 3 %rt2 = type { i32, { i8, %rt2, i8 }, i32 }
10 %0 = alloca %rt2
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| H A D | recursive-type-2.ll | 3 %rt1 = type { i32, { i8, %rt2, i8 }, i32 }
4 %rt2 = type { i64, { i6, %rt3 } }
12 %0 = alloca %rt2
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| /aosp_15_r20/external/tensorflow/tensorflow/compiler/xla/service/ |
| H A D | eigh_expander.cc | 61 XlaOp rt2; member
129 auto rt2 = w_br + t * w_tr; in HermitianEigenDecomposition2x2() local
133 rt2 = Complex(rt2, ZerosLike(rt2)); in HermitianEigenDecomposition2x2()
138 return Eigh2x2{rt1, rt2, c, s}; in HermitianEigenDecomposition2x2()
249 w_br = SetMatrixDiagonal(w_br, rotation.rt2); in ApplyRotations()
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| /aosp_15_r20/external/XNNPACK/src/jit/ |
| H A D | aarch64-assembler.cc | 43 template <typename Reg> inline uint32_t rt2(Reg rn) { return rn.code << 10; } in rt2() function
269 emit32(0xA8400000 | postindex(xn) | wb(xn) | offset << 15 | rt2(xt2) | rn(xn.base) | xt1.code); in ldp()
327 emit32(0xA9000000 | wb(xn) | offset << 15 | rt2(xt2) | rn(xn.base) | rt(xt1)); in stp()
513 emit32(0x6C400000 | postindex(xn) | wb(xn) | offset << 15 | rt2(dt2) | rn(xn.base) | rt(dt1)); in ldp()
527 emit32(0xACC00000 | offset << 15 | rt2(qt2) | rn(xn.base) | qt1.code); in ldp()
594 emit32(0x6D000000 | wb(xn) | offset << 15 | rt2(dt2) | rn(xn.base) | rt(dt1)); in stp()
604 emit32(0xAD000000 | wb(xn) | offset << 15 | rt2(qt2) | rn(xn.base) | rt(qt1)); in stp()
614 emit32(0xAC800000 | offset << 15 | rt2(qt2) | rn(xn.base) | rt(qt1)); in stp()
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| /aosp_15_r20/external/rust/crates/quiche/src/ |
| D | cid.rs | 818 let (scid2, rt2) = create_cid_and_reset_token(16); in ids_new_scids()
820 assert_eq!(ids.new_scid(scid2, Some(rt2), true, None, false), Ok(1)); in ids_new_scids()
874 let (dcid2, rt2) = create_cid_and_reset_token(16); in new_dcid_event()
877 ids.new_dcid(dcid2.clone(), 1, rt2, 0), in new_dcid_event()
938 let (scid2, rt2) = create_cid_and_reset_token(16); in retire_scids()
942 ids.new_scid(scid2.clone(), Some(rt2), true, None, false), in retire_scids()
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| /aosp_15_r20/external/rust/android-crates-io/crates/quiche/src/ |
| D | cid.rs | 818 let (scid2, rt2) = create_cid_and_reset_token(16); in ids_new_scids()
820 assert_eq!(ids.new_scid(scid2, Some(rt2), true, None, false), Ok(1)); in ids_new_scids()
874 let (dcid2, rt2) = create_cid_and_reset_token(16); in new_dcid_event()
877 ids.new_dcid(dcid2.clone(), 1, rt2, 0), in new_dcid_event()
938 let (scid2, rt2) = create_cid_and_reset_token(16); in retire_scids()
942 ids.new_scid(scid2.clone(), Some(rt2), true, None, false), in retire_scids()
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| /aosp_15_r20/external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 1097 const CPURegister& rt2, in ldp() argument
1099 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2)); in ldp()
1104 const CPURegister& rt2, in stp() argument
1106 LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2)); in stp()
1119 const CPURegister& rt2, in LoadStorePair() argument
1122 VIXL_ASSERT(CPUHas(rt, rt2)); in LoadStorePair()
1125 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2)); in LoadStorePair()
1126 VIXL_ASSERT(AreSameSizeAndType(rt, rt2)); in LoadStorePair()
1130 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) | in LoadStorePair()
1155 const CPURegister& rt2, in ldnp() argument
[all …]
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| /aosp_15_r20/external/rust/android-crates-io/crates/tokio-util/tests/ |
| D | context.rs | 16 let rt2 = Builder::new_multi_thread() in tokio_context_with_another_runtime() localVariable
24 rt1.block_on(rt2.wrap(async move { sleep(Duration::from_millis(2)).await })); in tokio_context_with_another_runtime()
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| /aosp_15_r20/external/llvm/test/CodeGen/AArch64/ |
| H A D | returnaddr.ll | 11 define i8* @rt2() nounwind readnone {
13 ; CHECK-LABEL: rt2:
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| H A D | arm64-returnaddr.ll | 12 define i8* @rt2() nounwind readnone {
14 ; CHECK-LABEL: rt2:
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| /aosp_15_r20/external/pdfium/xfa/fxfa/ |
| H A D | cxfa_ffpageview.cpp | 221 const CFX_RectF& rt2 = arg2.GetWidget()->GetWidgetRect(); in OrderContainer() local
222 if (rt1.top - rt2.top >= kXFAWidgetPrecision) in OrderContainer()
223 return rt1.top < rt2.top; in OrderContainer()
224 return rt1.left < rt2.left; in OrderContainer()
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| /aosp_15_r20/external/llvm/test/CodeGen/ARM/ |
| H A D | arm-returnaddr.ll | 16 define i8* @rt2() nounwind readnone {
18 ; CHECK-LABEL: rt2:
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| /aosp_15_r20/external/swiftshader/third_party/subzero/src/DartARM32/ |
| H A D | assembler_arm.cc | 620 void Assembler::vmovsrr(SRegister sm, Register rt, Register rt2, in vmovsrr() argument
628 ASSERT(rt2 != kNoRegister); in vmovsrr()
629 ASSERT(rt2 != SP); in vmovsrr()
630 ASSERT(rt2 != PC); in vmovsrr()
633 B26 | B22 | (static_cast<int32_t>(rt2) * B16) | in vmovsrr()
640 void Assembler::vmovrrs(Register rt, Register rt2, SRegister sm, in vmovrrs() argument
648 ASSERT(rt2 != kNoRegister); in vmovrrs()
649 ASSERT(rt2 != SP); in vmovrrs()
650 ASSERT(rt2 != PC); in vmovrrs()
651 ASSERT(rt != rt2); in vmovrrs()
[all …]
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