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Searched refs:address32_hi (Results 1 – 25 of 28) sorted by relevance

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/aosp_15_r20/external/mesa3d/src/amd/common/
H A Dac_cmdbuf.c26 ac_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, S_00B834_DATA(info->address32_hi >> 8)); in gfx6_init_compute_preamble_state()
64 ac_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, S_00B834_DATA(info->address32_hi >> 8)); in gfx10_init_compute_preamble_state()
108 ac_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, S_00B834_DATA(info->address32_hi >> 8)); in gfx12_init_compute_preamble_state()
287 S_00B414_MEM_BASE(info->address32_hi >> 8)); in gfx6_init_graphics_preamble_state()
289 S_00B214_MEM_BASE(info->address32_hi >> 8)); in gfx6_init_graphics_preamble_state()
292 S_00B524_MEM_BASE(info->address32_hi >> 8)); in gfx6_init_graphics_preamble_state()
435 S_00B324_MEM_BASE(info->address32_hi >> 8)); in gfx10_init_graphics_preamble_state()
445 S_00B524_MEM_BASE(info->address32_hi >> 8)); in gfx10_init_graphics_preamble_state()
598 S_00B324_MEM_BASE(info->address32_hi >> 8)); in gfx12_init_graphics_preamble_state()
608 S_00B524_MEM_BASE(info->address32_hi >> 8)); in gfx12_init_graphics_preamble_state()
H A Dac_gpu_info.h170 uint32_t address32_hi; member
H A Dac_gpu_info.c783 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi); in ac_query_gpu_info()
1907 fprintf(f, " address32_hi = 0x%x\n", info->address32_hi); in ac_print_gpu_info()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/nir/
H A Dradv_nir_lower_abi.c25 uint32_t address32_hi; member
411 nir_imm_int(b, s->address32_hi)); in lower_abi_instr()
420 nir_imm_int(b, s->address32_hi)); in lower_abi_instr()
553 const struct radv_graphics_state_key *gfx_state, uint32_t address32_hi) in radv_nir_lower_abi() argument
560 .address32_hi = address32_hi, in radv_nir_lower_abi()
H A Dradv_nir_apply_pipeline_layout.c20 uint32_t address32_hi; member
40 return nir_pack_64_2x32_split(b, ptr, nir_imm_int(b, state->address32_hi)); in convert_pointer_to_64_bit()
144 …ac_build_raw_buffer_descriptor(state->gfx_level, (uint64_t)state->address32_hi << 32, 0xffffffff, … in load_inline_buffer_descriptor()
541 .address32_hi = pdev->info.address32_hi, in radv_nir_apply_pipeline_layout()
H A Dradv_nir.h33 const struct radv_graphics_state_key *gfx_state, uint32_t address32_hi);
H A Dradv_nir_lower_vs_inputs.c230 …buffers = nir_pack_64_2x32_split(b, vertex_buffers_arg, nir_imm_int(b, s->gpu_info->address32_hi)); in lower_load_vs_input()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/
H A Dradv_aco_shader_info.h112 aco_info->address32_hi = radv->info->address32_hi; in radv_aco_convert_opts()
H A Dradv_nir_to_llvm.c54 if (options->info->address32_hi) { in create_llvm_function()
56 options->info->address32_hi); in create_llvm_function()
H A Dradv_device_generated_commands.c942 …= nir_pack_64_2x32_split(b, load_param32(b, upload_addr), nir_imm_int(b, pdev->info.address32_hi)); in build_dgc_buffer_tail()
1006 …= nir_pack_64_2x32_split(b, load_param32(b, upload_addr), nir_imm_int(b, pdev->info.address32_hi)); in build_dgc_buffer_preamble()
1022 nir_imm_int(b, pdev->info.address32_hi), in build_dgc_buffer_preamble()
1996 …ir_pack_64_2x32_split(&b, load_param32(&b, upload_addr), nir_imm_int(&b, pdev->info.address32_hi)), in build_dgc_prepare_shader()
2077 …ir_pack_64_2x32_split(&b, load_param32(&b, upload_addr), nir_imm_int(&b, pdev->info.address32_hi)), in build_dgc_prepare_shader()
H A Dradv_queue.c626 assert((va >> 32) == pdev->info.address32_hi); in radv_emit_attribute_ring()
774 …eon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(pdev->info.address32_hi >> 8)); in radv_emit_graphics()
777 …eon_set_sh_reg(cs, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(pdev->info.address32_hi >> 8)); in radv_emit_graphics()
H A Dradv_cmd_buffer.h655 assert(va == 0 || (va >> 32) == pdev->info.address32_hi); in radv_emit_shader_pointer_body()
H A Dradv_pipeline.c574 NIR_PASS_V(stage->nir, radv_nir_lower_abi, gfx_level, stage, gfx_state, pdev->info.address32_hi); in radv_postprocess_nir()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_nir_lower_abi.c50 (uint64_t)sel->screen->info.address32_hi << 32, in build_attr_ring_desc()
136 (uint64_t)screen->info.address32_hi << 32, in build_tess_ring_desc()
454 nir_def *address32_hi = nir_imm_int(b, s->shader->selector->screen->info.address32_hi); in lower_intrinsic() local
455 replacement = nir_pack_64_2x32_split(b, address, address32_hi); in lower_intrinsic()
H A Dsi_shader_aco.c55 options->address32_hi = screen->info.address32_hi; in si_fill_aco_options()
H A Dsi_buffer.c167 assert((start >> 32) == sscreen->info.address32_hi); in si_alloc_resource()
168 assert((last >> 32) == sscreen->info.address32_hi); in si_alloc_resource()
H A Dsi_shader_llvm.c171 if (ctx->screen->info.address32_hi) { in si_llvm_create_func()
173 ctx->screen->info.address32_hi); in si_llvm_create_func()
H A Dsi_state_shaders.cpp737 S_00B424_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_hs()
814 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_es()
1157 S_00B224_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_gs()
1857 S_00B124_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_vs()
2213 S_00B024_MEM_BASE(sscreen->info.address32_hi >> 8)); in si_shader_ps()
5042 assert((attr_address >> 32) == sscreen->info.address32_hi); in si_emit_spi_ge_ring_state()
H A Dsi_nir_lower_resource.c32 .va = (uint64_t)sel->screen->info.address32_hi << 32, in load_ubo_desc_fast_path()
H A Dsi_build_pm4.h257 assert((va) == 0 || ((va) >> 32) == sctx->screen->info.address32_hi); \
H A Dsi_descriptors.c158 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_upload_descriptors()
159 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_upload_descriptors()
H A Dsi_pipe.c1126 sscreen->info.address32_hi); in si_disk_cache_create()
/aosp_15_r20/external/mesa3d/src/amd/compiler/
H A Daco_shader_info.h160 uint32_t address32_hi; member
H A Daco_instruction_selection.cpp801 Operand::c32((unsigned)ctx->options->address32_hi)); in convert_pointer_to_64_bit()
7312 Operand::c32(ctx->options->address32_hi)); in visit_load_smem()
13002 if (options->address32_hi >= 0xffff8000 || options->address32_hi <= 0x7fff) { in select_vs_prolog()
13004 options->address32_hi & 0xFFFF); in select_vs_prolog()
13007 Operand::c32((unsigned)options->address32_hi)); in select_vs_prolog()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/winsys/null/
H A Dradv_null_winsys.c140 gpu_info->address32_hi = gpu_info->gfx_level >= GFX9 ? 0xffff8000u : 0x0; in radv_null_winsys_query_info()

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