| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2908 Register Zero64; in buildMultiply() local
2916 if (!Zero64) in buildMultiply()
2917 Zero64 = B.buildConstant(S64, 0).getReg(0); in buildMultiply()
2918 return Zero64; in buildMultiply()
3521 auto Zero64 = B.buildConstant(S64, 0); in legalizeUnsignedDIV_REM64Impl() local
3522 auto NegDenom = B.buildSub(S64, Zero64, Denom); in legalizeUnsignedDIV_REM64Impl()
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| H A D | SIInstrInfo.cpp | 5798 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in extractRsrcPtr() local
5805 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64) in extractRsrcPtr()
5818 .addReg(Zero64) in extractRsrcPtr()
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| H A D | AMDGPUISelLowering.cpp | 1869 SDValue Zero64 = DAG.getConstant(0, DL, VT); in LowerUDIVREM64() local
1875 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); in LowerUDIVREM64()
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2364 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in legalizeOperands() local
2371 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::S_MOV_B64), Zero64) in legalizeOperands()
2384 .addReg(Zero64) in legalizeOperands()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 4492 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in extractRsrcPtr() local
4499 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64) in extractRsrcPtr()
4512 .addReg(Zero64) in extractRsrcPtr()
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| H A D | AMDGPUISelLowering.cpp | 1699 SDValue Zero64 = DAG.getConstant(0, DL, VT); in LowerUDIVREM64() local
1704 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); in LowerUDIVREM64()
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| /aosp_15_r20/external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5674 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in emitExt128() local
5676 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64) in emitExt128()
5679 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64); in emitExt128()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3859 auto Zero64 = MIRBuilder.buildConstant(S64, 0); in lowerU64ToF32BitOps() local
3866 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); in lowerU64ToF32BitOps()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 7432 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in emitExt128() local
7434 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64) in emitExt128()
7437 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64); in emitExt128()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 8162 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in emitExt128() local
8164 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64) in emitExt128()
8167 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64); in emitExt128()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6043 auto Zero64 = MIRBuilder.buildConstant(S64, 0); in lowerU64ToF32BitOps() local
6050 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); in lowerU64ToF32BitOps()
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