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Searched refs:XER (Results 1 – 25 of 31) sorted by relevance

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/aosp_15_r20/prebuilts/go/linux-x86/src/runtime/
Dpreempt_ppc64x.s39 MOVD XER, R31
111 MOVD R31, XER
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
237 // Carry bit. In the architecture this is really bit 0 of the XER register
241 let Aliases = [XER];
382 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
H A DPPCInstrInfo.td1043 let Defs = [XER] in
1047 let Defs = [XER, CR0] in
1070 let Defs = [XER] in
1074 let Defs = [XER, CR0] in
1095 let Defs = [CARRY, XER] in
1099 let Defs = [CARRY, XER, CR0] in
1119 let Defs = [XER] in
1123 let Defs = [XER, CR0] in
1144 let Defs = [CARRY, XER] in
1148 let Defs = [CARRY, XER, CR0] in
H A DREADME_P9.txt587 Move to CR from XER Extended (mcrxrx):
/aosp_15_r20/external/python/pyasn1/
DTODO.rst13 * XER
/aosp_15_r20/external/pdfium/testing/resources/
H A Dbigtable_mini.in103 n+a.f[/4_7lnp:OXP)%6XER"WK`:C2*&F%pl[L]/LH0S#rJk:S[coEjaA0p=l`BI4BP[$LCn09862jKs
/aosp_15_r20/prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/
Dppc64.s1090 MOVD R3, XER // 7c6103a6
1093 MOVD XER, R3 // 7c6102a6
1155 MOVD XER, 4(R1) // 7fe102a6fbe10004
1157 MOVD 4(R1), XER // ebe100047fe103a6
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td262 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
264 // Carry bit. In the architecture this is really bit 0 of the XER register
268 let Aliases = [XER];
429 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
H A DPPCInstrInfo.td824 let Defs = [XER] in
828 let Defs = [XER, CR0] in
851 let Defs = [XER] in
855 let Defs = [XER, CR0] in
876 let Defs = [CARRY, XER] in
880 let Defs = [CARRY, XER, CR0] in
900 let Defs = [XER] in
904 let Defs = [XER, CR0] in
925 let Defs = [CARRY, XER] in
929 let Defs = [CARRY, XER, CR0] in
H A DREADME_P9.txt582 Move to CR from XER Extended (mcrxrx):
/aosp_15_r20/external/cronet/third_party/libc++abi/src/test/vendor/ibm/
H A Daix_xlclang_passing_excp_obj_64.pass.sh.S90 .set MQ,0; .set XER,1; .set DSCR,3; .set FROM_RTCU,4; .set FROM_RTCL,5
583 .set MQ,0; .set XER,1; .set DSCR,3; .set FROM_RTCU,4; .set FROM_RTCL,5
H A Daix_xlclang_passing_excp_obj_32.pass.sh.S90 .set MQ,0; .set XER,1; .set DSCR,3; .set FROM_RTCU,4; .set FROM_RTCL,5
566 .set MQ,0; .set XER,1; .set DSCR,3; .set FROM_RTCU,4; .set FROM_RTCL,5
H A Daix_xlclang_nested_excp_32.pass.sh.s86 .set MQ,0; .set XER,1; .set DSCR,3; .set FROM_RTCU,4; .set FROM_RTCL,5
H A Daix_xlclang_nested_excp_64.pass.sh.s85 .set MQ,0; .set XER,1; .set DSCR,3; .set FROM_RTCU,4; .set FROM_RTCL,5
/aosp_15_r20/external/scapy/scapy/asn1/
H A Dasn1.py92 XER = 9 variable in ASN1_Codecs
/aosp_15_r20/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td216 // Carry bit. In the architecture this is really bit 0 of the XER register
H A Dp9-instrs.txt158 // Move to CR from XER Extended X-form p119
H A DREADME_P9.txt587 Move to CR from XER Extended (mcrxrx):
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
H A DPPCGenRegisterInfo.inc29 XER = 9,
1161 { PPC::CARRY, PPC::XER },
1406 PPC::CARRY, PPC::XER,
1820 { 76U, PPC::XER },
2108 { 76U, PPC::XER },
2327 { PPC::XER, 76U },
2880 { PPC::XER, 76U },
H A DPPCGenInstrInfo.inc2644 static const MCPhysReg ImplicitList2[] = { PPC::XER, 0 };
2645 static const MCPhysReg ImplicitList3[] = { PPC::XER, PPC::CR0, 0 };
2648 static const MCPhysReg ImplicitList6[] = { PPC::CARRY, PPC::XER, 0 };
2649 static const MCPhysReg ImplicitList7[] = { PPC::CARRY, PPC::XER, PPC::CR0, 0 };
H A DPPCGenAsmMatcher.inc3999 case PPC::XER: OpKind = MCK_CARRYRC; break;
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/PowerPC/
H A DPPCGenRegisterInfo.inc29 XER = 9,
1458 /* 2557 */ "XER\0"
1988 { PPC::CARRY, PPC::XER },
2297 PPC::CARRY, PPC::XER,
2918 { 76U, PPC::XER },
3206 { 76U, PPC::XER },
3425 { PPC::XER, 76U },
3914 { PPC::XER, 76U },
H A DPPCGenInstrInfo.inc3176 static const MCPhysReg ImplicitList3[] = { PPC::XER };
3177 static const MCPhysReg ImplicitList4[] = { PPC::XER, PPC::CR0 };
3179 static const MCPhysReg ImplicitList6[] = { PPC::CARRY, PPC::XER };
3180 static const MCPhysReg ImplicitList7[] = { PPC::CARRY, PPC::XER, PPC::CR0 };
3183 static const MCPhysReg ImplicitList10[] = { PPC::CARRY, PPC::CARRY, PPC::XER };
3184 static const MCPhysReg ImplicitList11[] = { PPC::CARRY, PPC::CARRY, PPC::XER, PPC::CR0 };
H A DPPCGenAsmMatcher.inc4626 case PPC::XER: OpKind = MCK_CARRYRC; break;
/aosp_15_r20/prebuilts/asuite/aidegen/linux-x86/
H A Daidegen4329 @J�XER�G

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