| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 146 unsigned SrcIdx, unsigned DstIdx,
1214 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1221 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1229 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1255 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1415 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1417 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1420 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1442 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
1464 unsigned SrcIdx = TP.first; in processTiedPairs() local
[all …]
|
| H A D | RegisterCoalescer.h | 42 unsigned SrcIdx = 0; variable
106 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
|
| H A D | RegisterCoalescer.cpp | 454 SrcIdx = DstIdx = 0; in setRegisters()
502 SrcIdx, DstIdx); in setRegisters()
507 SrcIdx = DstSub; in setRegisters()
524 if (DstIdx && !SrcIdx) { in setRegisters()
526 std::swap(SrcIdx, DstIdx); in setRegisters()
544 std::swap(SrcIdx, DstIdx); in flip()
569 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
583 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
1276 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
1323 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
[all …]
|
| H A D | PeepholeOptimizer.cpp | 1858 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1859 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1868 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1871 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1876 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1886 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
|
| /aosp_15_r20/external/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 132 unsigned SrcIdx, unsigned DstIdx,
1211 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1218 unsigned regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1227 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1253 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1408 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1410 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1413 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1427 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1435 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
[all …]
|
| H A D | RegisterCoalescer.h | 42 unsigned SrcIdx; variable
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair()
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
109 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
|
| H A D | RegisterCoalescer.cpp | 315 SrcIdx = DstIdx = 0; in setRegisters()
362 SrcIdx, DstIdx); in setRegisters()
367 SrcIdx = DstSub; in setRegisters()
384 if (DstIdx && !SrcIdx) { in setRegisters()
386 std::swap(SrcIdx, DstIdx); in setRegisters()
405 std::swap(SrcIdx, DstIdx); in flip()
429 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
443 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
885 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
927 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
[all …]
|
| H A D | PeepholeOptimizer.cpp | 1696 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1697 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1706 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1709 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1711 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
|
| H A D | TargetRegisterInfo.cpp | 299 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
302 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 156 unsigned SrcIdx, unsigned DstIdx,
1271 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1278 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1287 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1313 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1467 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1469 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1472 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1486 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1494 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
[all …]
|
| H A D | RegisterCoalescer.cpp | 428 SrcIdx = DstIdx = 0; in setRegisters()
475 SrcIdx, DstIdx); in setRegisters()
480 SrcIdx = DstSub; in setRegisters()
497 if (DstIdx && !SrcIdx) { in setRegisters()
499 std::swap(SrcIdx, DstIdx); in setRegisters()
518 std::swap(SrcIdx, DstIdx); in flip()
542 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
556 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
1238 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
1281 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
[all …]
|
| H A D | RegisterCoalescer.h | 40 unsigned SrcIdx = 0; variable
104 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
|
| H A D | PeepholeOptimizer.cpp | 1845 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1846 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1855 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1858 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1863 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1873 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 453 unsigned PredIdx, DOPIdx, SrcIdx, Src2Idx; in expand_DestructiveOp() local
460 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 3, 2); in expand_DestructiveOp()
467 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 2, 3); in expand_DestructiveOp()
470 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(2, 3, 3); in expand_DestructiveOp()
473 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 2, 3, 4); in expand_DestructiveOp()
476 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 3, 4, 2); in expand_DestructiveOp()
480 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 4, 3, 2); in expand_DestructiveOp()
494 DOPRegIsUnique = DstReg != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
500 MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
509 (MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg() && in expand_DestructiveOp()
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 807 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) { in ConstantFoldCTLZ() local
808 if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) { in ConstantFoldCTLZ()
1183 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) { in isConstantOrConstantVector() local
1184 if (getIConstantVRegValWithLookThrough(BV->getSourceReg(SrcIdx), MRI) || in isConstantOrConstantVector()
1185 getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI)) in isConstantOrConstantVector()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 2275 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
2284 SrcIdx = 1; MaskIdx = 5; break; in EmitInstruction()
2288 SrcIdx = 2; MaskIdx = 6; break; in EmitInstruction()
2292 SrcIdx = 3; MaskIdx = 7; break; in EmitInstruction()
2304 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in EmitInstruction()
2333 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
2342 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break; in EmitInstruction()
2346 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break; in EmitInstruction()
2350 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break; in EmitInstruction()
2356 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break; in EmitInstruction()
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 2121 unsigned SrcIdx = 1; in addConstantComments() local
2124 ++SrcIdx; in addConstantComments()
2127 ++SrcIdx; in addConstantComments()
2130 unsigned MaskIdx = SrcIdx + 1 + X86::AddrDisp; in addConstantComments()
2132 assert(MI->getNumOperands() >= (SrcIdx + 1 + X86::AddrNumOperands) && in addConstantComments()
2141 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in addConstantComments()
2199 unsigned SrcIdx = 1; in addConstantComments() local
2202 ++SrcIdx; in addConstantComments()
2205 ++SrcIdx; in addConstantComments()
2208 unsigned MaskIdx = SrcIdx + 1 + X86::AddrDisp; in addConstantComments()
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 233 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
249 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
292 int SrcIdx = getOperandIdx(MI.getOpcode(), Op[0]); in getSrcs() local
293 if (SrcIdx < 0) in getSrcs()
295 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1374 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1396 switch (SrcIdx) { in getFlagOp()
1413 switch (SrcIdx) { in getFlagOp()
|
| H A D | R600InstrInfo.h | 111 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
309 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 254 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
270 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
315 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs() local
316 if (SrcIdx < 0) in getSrcs()
318 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1400 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1422 switch (SrcIdx) { in getFlagOp()
1439 switch (SrcIdx) { in getFlagOp()
|
| H A D | R600InstrInfo.h | 112 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
310 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
|
| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 262 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
278 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
323 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs() local
324 if (SrcIdx < 0) in getSrcs()
326 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1427 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1449 switch (SrcIdx) { in getFlagOp()
1466 switch (SrcIdx) { in getFlagOp()
|
| H A D | R600InstrInfo.h | 108 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
312 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| H A D | InferAddressSpaces.cpp | 961 int SrcIdx = U.getOperandNo(); in rewriteWithNewAddressSpaces() local
962 int OtherIdx = (SrcIdx == 0) ? 1 : 0; in rewriteWithNewAddressSpaces()
968 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
976 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
|
| /aosp_15_r20/external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 229 int SrcIdx = SVI->getMaskValue(Elt->getZExtValue()); in visitExtractElementInst() local
234 if (SrcIdx < 0) in visitExtractElementInst()
236 if (SrcIdx < (int)LHSWidth) in visitExtractElementInst()
239 SrcIdx -= LHSWidth; in visitExtractElementInst()
245 SrcIdx, false)); in visitExtractElementInst()
|