| /aosp_15_r20/prebuilts/go/linux-x86/src/math/ |
| D | acosh_s390x.s | 99 SRAW $8, R2, R2
152 SRAW $8, R3, R2
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| D | asinh_s390x.s | 106 SRAW $8, R1, R1
137 SRAW $8, R4, R1
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| D | log10_s390x.s | 148 SRAW $1, R2, R2
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| D | atanh_s390x.s | 143 SRAW $8, R2, R1
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| /aosp_15_r20/prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| D | riscv64.s | 151 SRAW X5, X6, X7 // bb535340
160 SRAW X5, X7 // bbd35340
165 SRAW $1, X6 // 1b531340
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| D | s390x.s | 219 SRAW $4, R5, R8 // eb85000400dc
220 SRAW R3, R5, R8 // eb85300000dc
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| D | ppc64.s | 433 SRAW $8, R3, R4 // 7c644670
434 SRAW R3, R4, R5 // 7c851e30
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| /aosp_15_r20/prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/_gen/ |
| D | RISCV64.rules | 181 // SRA only considers the bottom 6 bits of y, similarly SRAW only considers the
190 // before passing it to SRAW.
193 // more than the 5 or 6 bits SRAW and SRA care about.
202 (Rsh32x8 <t> x y) && !shiftIsBounded(v) => (SRAW <t> x (OR <y.Type> y (ADDI <y.Typ…
203 (Rsh32x16 <t> x y) && !shiftIsBounded(v) => (SRAW <t> x (OR <y.Type> y (ADDI <y.Typ…
204 (Rsh32x32 <t> x y) && !shiftIsBounded(v) => (SRAW <t> x (OR <y.Type> y (ADDI <y.Typ…
205 (Rsh32x64 <t> x y) && !shiftIsBounded(v) => (SRAW <t> x (OR <y.Type> y (ADDI <y.Typ…
213 (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y)
746 (SRAW x (MOVDconst [val])) => (SRAIW [int64(val&31)] x)
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| D | S390X.rules | 266 (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y)
267 (Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW (MOVHreg x) y)
268 (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW (MOVBreg x) y)
295 (Rsh(16|8)x64 x y) => (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.…
296 (Rsh(16|8)x32 x y) => (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.…
297 (Rsh(16|8)x16 x y) => (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.…
298 (Rsh(16|8)x8 x y) => (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.…
671 (SRAW x (MOVDconst [c])) && c&32 != 0 => (SRAWconst x [31])
687 (SRAW x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRAW x y)
1154 ((SLD|SLW|SRD|SRW|SRAD|SRAW)const x [0]) => x
|
| D | PPC64.rules | 190 (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y)
214 (Rsh32x(64|32) <t> x y) => (ISEL [0] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMP(U|WU)const …
215 (Rsh32x16 <t> x y) => (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (A…
216 (Rsh32x8 <t> x y) => (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (A…
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCBack2BackFusion.def | 207 SRAW,
741 SRAW,
|
| H A D | P9InstrResources.td | 192 (instregex "SRAW(I)?$"),
1092 (instregex "SRAW(I)?_rec$"),
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 38 SRAW, enumerator
|
| H A D | RISCVInstrInfo.td | 53 def riscv_sraw : SDNode<"RISCVISD::SRAW", SDTIntShiftOp>;
518 def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">,
1085 def : PatGprGpr<riscv_sraw, SRAW>;
|
| H A D | RISCVISelLowering.cpp | 833 return RISCVISD::SRAW; in getRISCVWOpcode()
985 case RISCVISD::SRAW: in PerformDAGCombine()
1087 case RISCVISD::SRAW: in ComputeNumSignBitsForTargetNode()
2521 case RISCVISD::SRAW: in getTargetNodeName()
|
| /aosp_15_r20/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/ |
| D | plan9.go | 266 case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC:
|
| D | tables.go | 1368 SRAW const
2788 SRAW: "sraw",
5676 …{SRAW, 0xfc0007ff00000000, 0x7c00063000000000, 0x0, // Shift Right Algebraic Word X-form (sraw RA,…
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/RISCV/ |
| H A D | RISCVGenMCCodeEmitter.inc | 510 UINT64_C(1073762363), // SRAW
1255 case RISCV::SRAW:
1988 CEFBS_IsRV64, // SRAW = 497
|
| H A D | RISCVGenAsmWriter.inc | 775 6274U, // SRAW
1289 32U, // SRAW
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 66 SRAW, enumerator
|
| H A D | RISCVInstrInfo.td | 73 def riscv_sraw : SDNode<"RISCVISD::SRAW", SDT_RISCVIntBinOpW>;
783 def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">,
1769 def : PatGprGpr<shiftopw<riscv_sraw>, SRAW>;
|
| /aosp_15_r20/external/pcre/src/sljit/ |
| H A D | sljitNativePPC_32.c | 295 return push_inst(compiler, SRAW | RC(flags) | S(src1) | A(dst) | B(src2)); in emit_single_op()
|
| H A D | sljitNativePPC_64.c | 475 …return push_inst(compiler, ((flags & ALT_FORM2) ? SRAW : SRAD) | RC(flags) | S(src1) | A(dst) | B(… in emit_single_op()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 190 (instregex "SRAW(I)?$"),
1093 (instregex "SRAW(I)?_rec$"),
|
| H A D | PPCInstrInfo.cpp | 3091 case PPC::SRAW: in instrHasImmForm()
3133 case PPC::SRAW: in instrHasImmForm()
3880 Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec || in isSignExtendingOp()
|