| /aosp_15_r20/external/coreboot/util/spd_tools/ |
| H A D | README.md | 1 # SPD tools
3 A set of tools to generate SPD files for platforms with memory down
11 * LPDDR5/5X - based on the LPDDR5 spec JESD209-5B, the SPD spec SPD4.1.2.M-2
12 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for
19 * `spd_gen`: This tool generates de-duplicated SPD files using a global memory
21 in the global list to one of the generated SPD files. For each supported
23 to a set of SoC platforms with different SPD requirements, e.g. due to
29 integrate the SPD files generated by `spd_gen` into the coreboot build.
128 for all speed grades. But the SPD byte to encode this field is only 1 byte.
325 * `lp5x`: If this is an LP5X part. SPD format is identical for LP5/5X aside
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| /aosp_15_r20/external/coreboot/src/mainboard/pcengines/apu2/spd/ |
| H A D | HYNIX-4G-1333-ECC.spd.hex | 1 # HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix
3 # SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down
4 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
5 # bits[3:0]: 1 = 128 SPD Bytes Used
6 # bits[6:4]: 1 = 256 SPD Bytes Total
10 # 1 SPD Revision -
|
| H A D | HYNIX-2G-1333.spd.hex | 3 # SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down
4 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
5 # bits[3:0]: 1 = 128 SPD Bytes Used
6 # bits[6:4]: 1 = 256 SPD Bytes Total
10 # 1 SPD Revision
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| /aosp_15_r20/external/trusty/arm-trusted-firmware/ |
| D | Makefile | 448 ifneq (${SPD},none)
459 ifeq (${SPD},spmd)
501 SPD_MAKE := $(wildcard services/${SPD_DIR}/${SPD}/${SPD}.mk)
504 $(error Error: No services/${SPD_DIR}/${SPD}/${SPD}.mk located)
521 ifneq (${SPD},spmd)
522 $(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
653 ifneq (${SPD}, none)
654 ifneq (${SPD}, spmd)
655 $(error ENABLE_RME is incompatible with SPD=${SPD}. Use SPD=spmd)
663 ifeq (${SPD},none)
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| /aosp_15_r20/external/coreboot/src/lib/ |
| H A D | Kconfig | 42 and locating it runtime to load SPD.
56 Total SPD size that will be used for DIMM.
67 to speed loading of SPD data. Currently requires board-level
68 romstage implementation to read/write/utilize cached SPD data.
70 to store the cached SPD data.
77 Name of the FMAP region created in the default FMAP to cache SPD data.
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| /aosp_15_r20/external/coreboot/src/mainboard/portwell/m107/spd/ |
| H A D | SAMSUNG_K4B8G1646D-MYKO.spd.hex | 18 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
19 # bits[3:0]: 3 = 384 SPD Bytes Used
20 # bits[6:4]: 1 = 256 SPD Bytes Total
24 # 1 SPD Revision
217 # 126-127 SPD CRC
|
| H A D | MICRON_MT41K512M16HA-125A.spd.hex | 19 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
20 # bits[3:0]: 3 = 384 SPD Bytes Used
21 # bits[6:4]: 1 = 256 SPD Bytes Total
25 # 1 SPD Revision
220 # 126-127 SPD CRC
|
| H A D | KINGSTON_B5116ECMDXGGB.spd.hex | 19 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
20 # bits[3:0]: 3 = 384 SPD Bytes Used
21 # bits[6:4]: 1 = 256 SPD Bytes Total
25 # 1 SPD Revision
220 # 126-127 SPD CRC
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| /aosp_15_r20/external/coreboot/src/mainboard/facebook/fbg1701/spd/ |
| H A D | KINGSTON_B5116ECMDXGGB.spd.hex | 19 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
20 # bits[3:0]: 3 = 384 SPD Bytes Used
21 # bits[6:4]: 1 = 256 SPD Bytes Total
25 # 1 SPD Revision
220 # 126-127 SPD CRC
|
| H A D | SAMSUNG_K4B8G1646D-MYKO.spd.hex | 18 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
19 # bits[3:0]: 3 = 384 SPD Bytes Used
20 # bits[6:4]: 1 = 256 SPD Bytes Total
24 # 1 SPD Revision
217 # 126-127 SPD CRC
|
| H A D | MICRON_MT41K512M16HA-125A.spd.hex | 19 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
20 # bits[3:0]: 3 = 384 SPD Bytes Used
21 # bits[6:4]: 1 = 256 SPD Bytes Total
25 # 1 SPD Revision
220 # 126-127 SPD CRC
|
| /aosp_15_r20/external/coreboot/util/autoport/ |
| H A D | readme.md | 111 ### SPD subsection
114 timing data. This data is usually known as SPD. Unfortunately, the SMBus addresses may not
117 the RAM chips are soldered directly to the mainboard), there is no EEPROM to get SPD data from,
118 so function `mb_get_spd_map` in `early_init.c` has to populate the SPD data from a file in CBFS.
161 the SPD array must be `0x50`. After testing all the slots, your `spd_addresses`
175 Most of the time, soldered RAM does not have an EEPROM. Instead, the SPD data is
177 to generate the SPD data to use with coreboot. Look at `inteltool.log`. There
180 /* SPD matching current mode: */
216 This is not a full-fledged SPD dump, as it only lists the currently-used speed configuration,
217 and lacks info such as a serial number, vendor and model. To create a SPD hex file, one has to
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| /aosp_15_r20/external/coreboot/Documentation/mainboard/lenovo/ |
| H A D | t431s.md | 32 the corresponding SPD datum from CBFS is not implemented yet. You may
33 have to dump the SPD data when running the vendor firmware with
34 inteltool, and replace the content of the SPD hex with what is dumped.
37 I do not know how to find gpio ports for that, and SPD data stored in
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| /aosp_15_r20/external/arm-trusted-firmware/docs/design/ |
| H A D | interrupt-framework-design.rst | 275 #. Secure Payload Dispatcher (SPD) service. This service interfaces with the
282 the SPD service. TF-A implements an example Test Secure Payload Dispatcher
285 An SPD service plugs into the EL3 runtime firmware and could be common to
290 SPD service to manage communication with non-secure software. TF-A
295 just like the SPD service.
392 runtime firmware is responsible for programming the routing model. The SPD is
401 A SPD service is responsible for determining and maintaining the interrupt
408 If the routing model is not known to the SPD service at build time, then it must
409 be provided by the SP as the result of its initialisation. The SPD should
411 SPD initialisation function pointed to by the ``bl32_init`` variable.
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| /aosp_15_r20/external/trusty/arm-trusted-firmware/docs/design/ |
| D | interrupt-framework-design.rst | 275 #. Secure Payload Dispatcher (SPD) service. This service interfaces with the
282 the SPD service. TF-A implements an example Test Secure Payload Dispatcher
285 An SPD service plugs into the EL3 runtime firmware and could be common to
290 SPD service to manage communication with non-secure software. TF-A
295 just like the SPD service.
392 runtime firmware is responsible for programming the routing model. The SPD is
401 A SPD service is responsible for determining and maintaining the interrupt
408 If the routing model is not known to the SPD service at build time, then it must
409 be provided by the SP as the result of its initialisation. The SPD should
411 SPD initialisation function pointed to by the ``bl32_init`` variable.
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| /aosp_15_r20/external/trusty/arm-trusted-firmware/plat/mediatek/build_helpers/ |
| D | conditional_eval_options.mk | 30 ifeq (${SPD},none)
36 ifeq ($(SPD), tbase)
41 ifeq ($(SPD), teeid)
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| /aosp_15_r20/external/coreboot/Documentation/northbridge/intel/sandybridge/ |
| H A D | nri_freq.md | 18 | SPD | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes | …
27 ## SPD section in Frequency selection
28 The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
33 [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
45 In case the XMP profile doesn't fulfill those limits, the regular SPD will be
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| /aosp_15_r20/external/trusty/arm-trusted-firmware/docs/components/spd/ |
| D | trusty-dispatcher.rst | 14 The ``TRUSTY_SPD_WITH_SHARED_MEM`` build flag controls whether Trusty SPD
18 Trusty SPD supports smc calls to return gic base address and print to
51 Sharing memory using the Trusty SPD requires the ``plat_mem_set_shared()``
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| /aosp_15_r20/external/eigen/doc/ |
| H A D | SparseLinearSystems.dox | 18 …dule SparseCholesky\endlink></tt></td><td>Direct LLt factorization</td><td>SPD</td><td>Fill-in red…
22 …ule SparseCholesky\endlink></tt></td><td>Direct LDLt factorization</td><td>SPD</td><td>Fill-in red…
43 …rSolvers_Module IterativeLinearSolvers\endlink></tt></td> <td>Classic iterative CG</td><td>SPD</td>
64 …iXSupport \endlink</td><td>Direct LLt, LDLt, LU factorizations</td><td>SPD \n SPD \n Square</td><t…
67 …rt_Module CholmodSupport \endlink</td><td>Direct LLt factorization</td><td>SPD</td><td>Fill-in red…
82 …soSupport \endlink</td><td>Direct LLt, LDLt, LU factorizations</td><td>SPD \n SPD \n Square</td><t…
87 Here \c SPD means symmetric positive definite.
116 For \c SPD solvers, a second optional template argument allows to specify which triangular part hav…
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| /aosp_15_r20/external/angle/src/libANGLE/renderer/vulkan/shaders/src/ |
| H A D | GenerateMipmap.comp | 6 // GenerateMipmap.comp: Generate mipmap of texture in a single pass. Uses AMD's FFX SPD located in
10 // the 12 mips supported by FFX SPD). The issue is that FFX SPD tries to `imageLoad` from `dst[5]`
18 // - By removing support for >6 mips, we can remove the atomic counter logic required by FFX SPD to
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| /aosp_15_r20/external/coreboot/src/mainboard/intel/harcuvar/ |
| H A D | Kconfig | 26 hex "SPD binary location in cbfs"
29 Location of SPD binary for memory down function.
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| /aosp_15_r20/external/arm-trusted-firmware/ |
| H A D | Makefile | 515 ifneq (${SPD},none)
525 ifeq (${SPD},spmd)
556 SPD_MAKE := $(wildcard services/${SPD_DIR}/${SPD}/${SPD}.mk)
559 $(error Error: No services/${SPD_DIR}/${SPD}/${SPD}.mk located)
1123 SPD_${SPD} \
1183 ifeq (${SPD},spmd)
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| /aosp_15_r20/external/arm-trusted-firmware/plat/arm/board/fvp/ |
| H A D | platform.mk | 266 ifeq (${SPD},tspd)
274 ifeq (${SPD},spmd)
348 ifeq (${SPD},trusty)
358 ifeq (${SPD},tspd)
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| /aosp_15_r20/external/trusty/arm-trusted-firmware/plat/qemu/qemu/ |
| D | platform.mk | 31 ifeq (${SPD},opteed)
50 ifeq (${SPD},trusty)
172 ifeq (${SPD},spmd)
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| /aosp_15_r20/external/coreboot/Documentation/northbridge/intel/haswell/ |
| H A D | mrc.bin.md | 30 ## SPD Addresses
32 When porting a board from vendor firmware, the SPD addresses can be obtained
102 The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied
|