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Searched refs:Rm (Results 1 – 25 of 235) sorted by relevance

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/aosp_15_r20/external/vixl/test/aarch32/config/
H A Dcond-rd-rn-operand-rm-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>
30 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
31 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
34 // MNEMONIC{<c>}.N SP, SP, <Rm>
35 // MNEMONIC{<c>}.N <Rd>, <Rn>, <Rm>
36 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; rm is not SP
37 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; low registers
45 "Adc", // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
46 // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
[all …]
H A Dcond-rd-rn-rm-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
35 "Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; T2
36 "Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
37 "Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
38 "Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
39 "Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
40 "Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
41 "Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
42 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
43 "Shadd16", // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
[all …]
H A Dcond-rd-rn-rm-a32.json35 "Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
36 "Muls", // MULS{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
37 "Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
38 "Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
39 "Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
40 "Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
41 "Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
42 "Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
43 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
44 "Shadd16", // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
[all …]
H A Dcond-rd-rn-operand-rm-a32.json28 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rm>, <Rs>
29 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
30 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
38 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
39 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
40 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
41 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
42 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
43 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
44 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
[all …]
H A Dcond-rd-operand-rn-t32.json28 // MNEMONIC{<c>}{<q>} <Rd>, <Rm>
29 // MNEMONIC{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> }
30 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> }
38 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm> ; T1
39 // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; T2
40 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm> ; T1
41 // CMP{<c>}{<q>} <Rn>, <Rm> ; T2
42 "Mov", // MOV{<c>}{<q>} <Rd>, <Rm> ; T1
43 // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
44 // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
[all …]
H A Dcond-rd-memop-rs-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Ldrh", // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
36 // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1
37 // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1
38 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
[all …]
H A Dcond-rd-rn-operand-rm-shift-amount-1to32-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, ASR|LSR #<amount>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>, ASR|LSR #<amount>
33 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
35 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
36 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
37 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
39 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
[all …]
H A Dcond-rd-rn-operand-rm-shift-amount-1to31-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, LSL|ROR #<amount>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>, LSL|ROR #<amount>
33 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
35 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
36 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
37 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
39 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
[all …]
H A Dcond-rd-rn-operand-rm-shift-amount-1to32-a32.json29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
32 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
35 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
[all …]
H A Dcond-rd-rn-operand-rm-shift-amount-1to31-a32.json29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
32 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
35 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
[all …]
H A Dcond-rd-rn-operand-rm-shift-rs-a32.json29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
32 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
33 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
34 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
35 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
36 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
37 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
38 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
[all …]
H A Dcond-rd-operand-rn-a32.json28 // MNEMONIC{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> }
29 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> }
37 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
38 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
39 "Mov", // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
40 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
41 "Mvn", // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
42 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
43 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
44 "Tst", // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
[all …]
/aosp_15_r20/external/cronet/third_party/rust/chromium_crates_io/vendor/regex-1.10.4/testdata/
H A Dmultiline.toml9 regex = '(?Rm)^[a-z]+$'
15 regex = '(?Rm)^[a-z]+$'
27 regex = '(?Rm)^$'
33 regex = '(?Rm)^$'
45 regex = '(?Rm)^'
51 regex = '(?Rm)^'
63 regex = '(?Rm)$'
69 regex = '(?Rm)$'
81 regex = '(?Rm)^[a-z]'
87 regex = '(?Rm)^[a-z]'
[all …]
/aosp_15_r20/out/soong/.intermediates/external/llvm/lib/Target/AArch64/llvm-gen-aarch64/gen/
DAArch64GenDAGISel.inc31 /*29*/ OPC_RecordChild2, // #2 = $ro_Windexed16:Rn:Rm:extend
43 …One128:v8i16:$Vt, 0:iPTR), (ro_Windexed16:iPTR GPR64sp:i64:$Rn, GPR32:i32:$Rm, ro_Wextend16:i32:$e…
44 …SUBREG:f16 VecListOne128:v8i16:$Vt, hsub:i32), GPR64sp:i64:$Rn, GPR32:i32:$Rm, ro_Wextend16:i32:$e…
53 …One128:v8i16:$Vt, 0:iPTR), (ro_Xindexed16:iPTR GPR64sp:i64:$Rn, GPR64:i64:$Rm, ro_Xextend16:i32:$e…
54 …SUBREG:f16 VecListOne128:v8i16:$Vt, hsub:i32), GPR64sp:i64:$Rn, GPR64:i64:$Rm, ro_Xextend16:i32:$e…
58 /*93*/ OPC_RecordChild2, // #2 = $ro_Windexed16:Rn:Rm:extend
69 …One128:v8i16:$Vt, 0:iPTR), (ro_Windexed16:iPTR GPR64sp:i64:$Rn, GPR32:i32:$Rm, ro_Wextend16:i32:$e…
70 …SUBREG:f16 VecListOne128:v8i16:$Vt, hsub:i32), GPR64sp:i64:$Rn, GPR32:i32:$Rm, ro_Wextend16:i32:$e…
79 …One128:v8i16:$Vt, 0:iPTR), (ro_Xindexed16:iPTR GPR64sp:i64:$Rn, GPR64:i64:$Rm, ro_Xextend16:i32:$e…
80 …SUBREG:f16 VecListOne128:v8i16:$Vt, hsub:i32), GPR64sp:i64:$Rn, GPR64:i64:$Rm, ro_Xextend16:i32:$e…
[all …]
/aosp_15_r20/external/llvm/lib/Target/ARM/
H A DARMInstrThumb.td362 let Inst{6-3} = 0b1111; // Rm = pc
421 // ADD <Rm>, sp
433 // ADD sp, <Rm>
434 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
435 "add", "\t$Rdn, $Rm", []>,
438 bits<4> Rm;
440 let Inst{6-3} = Rm;
451 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
454 bits<4> Rm;
455 let Inst{6-3} = Rm;
[all …]
H A DARMInstrThumb2.td281 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
287 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
377 bits<4> Rm;
380 let Inst{3-0} = Rm;
387 bits<4> Rm;
390 let Inst{3-0} = Rm;
397 bits<4> Rm;
400 let Inst{3-0} = Rm;
436 bits<4> Rm;
440 let Inst{3-0} = Rm;
[all …]
H A DARMInstrInfo.td1270 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1271 iir, opc, "\t$Rd, $Rn, $Rm",
1272 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1276 bits<4> Rm;
1282 let Inst{3-0} = Rm;
1343 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1344 iir, opc, "\t$Rd, $Rn, $Rm",
1349 bits<4> Rm;
1352 let Inst{3-0} = Rm;
1405 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
H A DARMInstrThumb.td395 let Inst{6-3} = 0b1111; // Rm = pc
454 // ADD <Rm>, sp
466 // ADD sp, <Rm>
467 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
468 "add", "\t$Rdn, $Rm", []>,
471 bits<4> Rm;
473 let Inst{6-3} = Rm;
484 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
487 bits<4> Rm;
488 let Inst{6-3} = Rm;
[all …]
H A DARMInstrThumb2.td359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
365 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
524 bits<4> Rm;
527 let Inst{3-0} = Rm;
534 bits<4> Rm;
537 let Inst{3-0} = Rm;
544 bits<4> Rm;
547 let Inst{3-0} = Rm;
583 bits<4> Rm;
587 let Inst{3-0} = Rm;
[all …]
H A DARMInstrInfo.td1548 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1549 iir, opc, "\t$Rd, $Rn, $Rm",
1550 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1554 bits<4> Rm;
1560 let Inst{3-0} = Rm;
1621 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1622 iir, opc, "\t$Rd, $Rn, $Rm",
1627 bits<4> Rm;
1630 let Inst{3-0} = Rm;
1683 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMInstrThumb.td391 let Inst{6-3} = 0b1111; // Rm = pc
450 // ADD <Rm>, sp
462 // ADD sp, <Rm>
463 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
464 "add", "\t$Rdn, $Rm", []>,
467 bits<4> Rm;
469 let Inst{6-3} = Rm;
480 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
483 bits<4> Rm;
484 let Inst{6-3} = Rm;
[all …]
H A DARMInstrThumb2.td352 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
358 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
517 bits<4> Rm;
520 let Inst{3-0} = Rm;
527 bits<4> Rm;
530 let Inst{3-0} = Rm;
537 bits<4> Rm;
540 let Inst{3-0} = Rm;
576 bits<4> Rm;
580 let Inst{3-0} = Rm;
[all …]
H A DARMInstrInfo.td1412 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1413 iir, opc, "\t$Rd, $Rn, $Rm",
1414 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1418 bits<4> Rm;
1424 let Inst{3-0} = Rm;
1485 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1486 iir, opc, "\t$Rd, $Rn, $Rm",
1491 bits<4> Rm;
1494 let Inst{3-0} = Rm;
1547 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
H A DAArch64GenGlobalISel.inc1320 …d_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, ar…
1324 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm
1334 …arith_shifted_reg32:{ *:[i32] }:$Rm) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted…
1338 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm
1348 …R32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:…
1597 …i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32]…
1601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1626 …i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32]…
1630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1655 …(sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR3…
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td66 def : Pat<(relaxed_load<atomic_load_az_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
68 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
69 def : Pat<(relaxed_load<atomic_load_az_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
71 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
82 def : Pat<(relaxed_load<atomic_load_az_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
84 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
85 def : Pat<(relaxed_load<atomic_load_az_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
87 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
98 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
100 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
[all …]

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