FR32 (reference) in projects: aosp_15_r20

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Searched refs:FR32 (Results 1 – 25 of 30) sorted by relevance

/aosp_15_r20/external/llvm/test/TableGen/
H A D	Slice.td	57 def FR32 : RegisterClass<[f32], 66 def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 69 def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 75 def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 78 def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 87 defm NOT : myscalar<0x10, "not", [[], [(set FR32:$dst, (f32 (not FR32:$src)))]]>; 89 // CHECK: Pattern = [(set FR32:$dst, (f32 (not FR32:$src)))]; 91 // CHECK: Pattern = [(set FR32:$dst, (f32 (not FR32:$src)))];
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A D	X86InstrFMA.td	311 FR32, f32mem, sched>, 375 defm : scalar_fma_patterns<X86any_Fmadd, "VFMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 376 defm : scalar_fma_patterns<X86Fmsub, "VFMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 377 defm : scalar_fma_patterns<X86Fnmadd, "VFNMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 378 defm : scalar_fma_patterns<X86Fnmsub, "VFNMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 541 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86any_Fmadd, loadf32, 545 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32, 549 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, 553 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, 632 defm : scalar_fma4_patterns<X86any_Fmadd, "VFMADDSS4", v4f32, f32, FR32, loadf32>; [all …]
H A D	X86InstrSSE.td	115 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "", 116 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1, NoAVX512]>; 183 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64 255 // _alt version uses FR32/FR64 register class. 268 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss", 274 defm MOVSS : sse12_move_rm<FR32, v4f32, f32mem, loadf32, X86vzload32, "movss", 871 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, any_fp_to_sint, f32mem, loadf32, 875 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, any_fp_to_sint, f32mem, loadf32, 894 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss", "l", 897 defm VCVTSI642SS : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss", "q", [all …]
H A D	X86GenRegisterBankInfo.def	`21 // FR32/64 , xmm registers`
H A D	X86InstrVecCompiler.td	`21 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>; 36 def : Pat<(v4f32 (scalar_to_vector FR32:$src)), 37 (COPY_TO_REGCLASS FR32:$src, VR128)>;`
H A D	X86InstrCompiler.td	572 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 1010 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1011 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>, 1013 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1014 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>, 1093 def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1094 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>; 1095 def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1096 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>; 1097 def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), [all …]
H A D	X86RegisterInfo.td	`523 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 525 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 558 128, (add FR32)>;`
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
H A D	X86InstrFMA.td	311 FR32, f32mem, sched>, 375 defm : scalar_fma_patterns<any_fma, "VFMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 376 defm : scalar_fma_patterns<X86any_Fmsub, "VFMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 377 defm : scalar_fma_patterns<X86any_Fnmadd, "VFNMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 378 defm : scalar_fma_patterns<X86any_Fnmsub, "VFNMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 541 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, any_fma, loadf32, 544 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86any_Fmsub, loadf32, 547 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, 550 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, 624 defm : scalar_fma4_patterns<any_fma, "VFMADDSS4", v4f32, FR32, loadf32>; [all …]
H A D	X86InstrSSE.td	117 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "", 118 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1, NoAVX512]>; 187 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64 258 // _alt version uses FR32/FR64 register class. 271 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss", 277 defm MOVSS : sse12_move_rm<FR32, v4f32, f32mem, loadf32, X86vzload32, "movss", 892 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, any_fp_to_sint, f32mem, loadf32, 896 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, any_fp_to_sint, f32mem, loadf32, 909 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, lrint, f32mem, loadf32, 913 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, llrint, f32mem, loadf32, [all …]
H A D	X86GenRegisterBankInfo.def	`21 // FR32/64 , xmm registers`
H A D	X86InstrVecCompiler.td	`23 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>; 42 def : Pat<(v4f32 (scalar_to_vector FR32:$src)), 43 (COPY_TO_REGCLASS FR32:$src, VR128)>;`
H A D	X86RegisterInfo.td	`533 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 535 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 537 def FR16 : RegisterClass<"X86", [f16], 16, (add FR32)> {let Size = 32;} 570 128, (add FR32)>;`
H A D	X86InstrCompiler.td	575 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 1109 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1110 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>, 1112 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1113 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>, 1192 def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1193 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>; 1194 def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1195 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>; 1196 def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), [all …]
/aosp_15_r20/external/llvm/lib/Target/X86/
H A D	X86InstrSSE.td	334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>; 373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)), 374 (COPY_TO_REGCLASS FR32:$src, VR128)>; 375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)), 376 (COPY_TO_REGCLASS FR32:$src, VR128)>; 455 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "", 456 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>; 505 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64 568 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss", 574 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss", [all …]
H A D	X86InstrFMA.td	`228 FR32, f32mem>, 382 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>, 385 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>, 388 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, 392 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,`
H A D	X86RegisterInfo.td	`442 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 444 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 446 def FR128 : RegisterClass<"X86", [i128, f128], 128, (add FR32)>; 470 128, (add FR32)>;`
H A D	X86InstrCompiler.td	`551 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 911 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src), 916 FR32:$src))))]>, Requires<[HasSSE1]>;`
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/X86/
H A D	X86GenGlobalISel.inc	9790 …// (bitconvert:{ :[i32] } FR32:{ :[f32] }:$src) => (VMOVSS2DIrr:{ :[i32] } FR32:{ :[f32] }:$… 9801 …// (bitconvert:{ :[i32] } FR32:{ :[f32] }:$src) => (MOVSS2DIrr:{ :[i32] } FR32:{ :[f32] }:$s… 10084 … // (lrint:{ :[i32] } FR32:{ :[f32] }:$src) => (VCVTSS2SIrr:{ :[i32] } FR32:{ :[f32] }:$src) 10108 … // (lrint:{ :[i32] } FR32:{ :[f32] }:$src) => (CVTSS2SIrr:{ :[i32] } FR32:{ :[f32] }:$src) 10158 …// (lrint:{ :[i64] } FR32:{ :[f32] }:$src) => (VCVTSS2SI64rr:{ :[i64] } FR32:{ :[f32] }:$src) 10182 … // (lrint:{ :[i64] } FR32:{ :[f32] }:$src) => (CVTSS2SI64rr:{ :[i64] } FR32:{ :[f32] }:$src) 10206 …// (lrint:{ :[i64] } FR32:{ :[f32] }:$src) => (VCVTSS2SI64Zrr:{ :[i64] } FR32:{ :[f32] }:$sr… 18691 …// (fadd:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (VADDSSrr:{ :[f32] } FR… 18703 …// (fadd:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (ADDSSrr:{ :[f32] } FR3… 19081 …// (fsub:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (VSUBSSrr:{ :[f32] } FR… [all …]
H A D	X86GenRegisterInfo.inc	`1735 // FR32 Register Class... 1736 const MCPhysReg FR32[] = { 1740 // FR32 Bit set. 2763 { FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 32, 1, true }, 4755 { 32, 32, 32, VTLists+12 }, // FR32 8940 { // FR32 10427 { // FR32 10428 0, // FR32:sub_8bit 10429 0, // FR32:sub_8bit_hi 10430 0, // FR32:sub_8bit_hi_phony [all …]`
H A D	X86GenInstrInfo.inc	`57887 FR32 = 110, 94125 FR32, 94437 FR32, FR32, f32mem, 94441 FR32, FR32, FR32, 95054 FR32, FR32, FR32, i8imm, 95198 FR32, FR32, f32mem, u8imm, 95202 FR32, FR32, FR32, u8imm, 95236 FR32, f32mem, 95240 FR32, FR32, 95327 FR32, f64mem, [all …]`
/aosp_15_r20/external/capstone/arch/X86/
H A D	X86GenRegisterInfo.inc	`853 // FR32 Register Class... 854 static const MCPhysReg FR32[] = { 858 // FR32 Bit set. 1464 { FR32, FR32Bits, 49, 16, sizeof(FR32Bits), X86_FR32RegClassID, 4, 4, 1, 1 },`
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
H A D	X86GenGlobalISel.inc	7005 …// (bitconvert:{ :[i32] } FR32:{ :[f32] }:$src) => (VMOVSS2DIrr:{ :[i32] } FR32:{ :[f32] }:$… 7016 …// (bitconvert:{ :[i32] } FR32:{ :[f32] }:$src) => (MOVSS2DIrr:{ :[i32] } FR32:{ :[f32] }:$s… 12786 …// (fadd:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (VADDSSrr:{ :[f32] } FR… 12798 …// (fadd:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (ADDSSrr:{ :[f32] } FR3… 13107 …// (fsub:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (VSUBSSrr:{ :[f32] } FR… 13119 …// (fsub:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (SUBSSrr:{ :[f32] } FR3… 13428 …// (fmul:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (VMULSSrr:{ :[f32] } FR… 13440 …// (fmul:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (MULSSrr:{ :[f32] } FR3… 13749 …// (fdiv:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (VDIVSSrr:{ :[f32] } FR… 13761 …// (fdiv:{ :[f32] } FR32:{ :[f32] }:$src1, FR32:{ :[f32] }:$src2) => (DIVSSrr:{ :[f32] } FR3… [all …]
H A D	X86GenDAGISel.inc	522 …// Src: (st FR32:{ :[f32] }:$src, addr:{ :[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Predic… 523 …// Dst: (MOVNTSS addr:{ :[iPTR] }:$dst, (COPY_TO_REGCLASS:{ :[v4f32] } FR32:{ :[f32] }:$src, VR… 6260 …// Src: (st FR32:{ :[f32] }:$src, addr:{ :[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Predic… 6261 // Dst: (VMOVSSmr addr:{ :[iPTR] }:$dst, FR32:{ :[f32] }:$src) 6268 …// Src: (st FR32:{ :[f32] }:$src, addr:{ :[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Predic… 6269 // Dst: (MOVSSmr addr:{ :[iPTR] }:$dst, FR32:{ :[f32] }:$src) 9827 …// Src: (atomic_store addr:{ :[iPTR] }:$dst, (bitconvert:{ :[i32] } FR32:{ :[f32] }:$src))<<P:P… 9828 // Dst: (MOVSSmr addr:{ :[iPTR] }:$dst, FR32:{ :[f32] }:$src) 9835 …// Src: (atomic_store addr:{ :[iPTR] }:$dst, (bitconvert:{ :[i32] } FR32:{ :[f32] }:$src))<<P:P… 9836 // Dst: (VMOVSSmr addr:{ :[iPTR] }:$dst, FR32:{ *:[f32] }:$src) [all …]
H A D	X86GenInstrInfo.inc	49528 FR32 = 105, 65062 OpTypes::FR32, 65206 OpTypes::FR32, OpTypes::FR32, -1, OpTypes::i8imm, -1, OpTypes::i32imm, OpTypes::SEGMENT_REG, 65208 OpTypes::FR32, OpTypes::FR32, OpTypes::FR32, 65529 OpTypes::FR32, OpTypes::FR32, OpTypes::FR32, OpTypes::i8imm, 65597 …OpTypes::FR32, OpTypes::FR32, -1, OpTypes::i8imm, -1, OpTypes::i32imm, OpTypes::SEGMENT_REG, OpTyp… 65599 OpTypes::FR32, OpTypes::FR32, OpTypes::FR32, OpTypes::u8imm, 65616 OpTypes::FR32, -1, OpTypes::i8imm, -1, OpTypes::i32imm, OpTypes::SEGMENT_REG, 65618 OpTypes::FR32, OpTypes::FR32, 65659 OpTypes::FR32, -1, OpTypes::i8imm, -1, OpTypes::i32imm, OpTypes::SEGMENT_REG, [all …]
H A D	X86GenRegisterInfo.inc	`1634 // FR32 Register Class... 1635 const MCPhysReg FR32[] = { 1639 // FR32 Bit set. 2625 { FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 1, true }, 4551 { 32, 32, 32, VTLists+10 }, // FR32 8562 { // FR32 9639 {1, 16}, // FR32 9764 "FR32", 9806 16, // 17: FR32`