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Searched refs:EXTR (Results 1 – 25 of 44) sorted by relevance

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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td30 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
31 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
H A DAArch64SchedCyclone.td176 // EXTR Shifts a pair of registers and requires two micro-ops.
178 // EXTR Xn, Xm, #imm
184 // EXTR's first register read is delayed by one cycle, effectively
186 // EXTR Xn, Xm, #imm
H A DAArch64SchedPredExynos.td140 // Identify EXTR as the alias for ROR (immediate).
H A DAArch64SchedAmpere1.td596 def : WriteRes<WriteExtr, [Ampere1UnitB]>; // EXTR shifts a reg pair
980 def : InstRW<[Ampere1Write_1cyc_1B], (instregex "EXTR(W|X)")>;
H A DAArch64ISelLowering.h169 EXTR, enumerator
H A DAArch64SchedA55.td70 def : WriteRes<WriteExtr, [CortexA55UnitALU]> { let Latency = 3; } // EXTR from a reg pair
H A DAArch64SchedTSV110.td432 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^EXTR(W|X)rri$")>;
H A DAArch64SchedFalkorDetails.td1208 def : InstRW<[FalkorWr_2XYZ_2cyc], (instregex "^EXTR(W|X)rri$")>;
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td30 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
31 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
H A DAArch64SchedCyclone.td173 // EXTR Shifts a pair of registers and requires two micro-ops.
175 // EXTR Xn, Xm, #imm
181 // EXTR's first register read is delayed by one cycle, effectively
183 // EXTR Xn, Xm, #imm
H A DAArch64SchedPredExynos.td143 // Identify EXTR as the alias for ROR (immediate).
H A DAArch64ISelLowering.h71 EXTR, enumerator
/aosp_15_r20/external/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td31 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
32 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
H A DAArch64SchedCyclone.td172 // EXTR Shifts a pair of registers and requires two micro-ops.
174 // EXTR Xn, Xm, #imm
180 // EXTR's first register read is delayed by one cycle, effectively
182 // EXTR Xn, Xm, #imm
H A DAArch64ISelLowering.h71 EXTR, enumerator
/aosp_15_r20/external/llvm/test/Transforms/InstCombine/
H A Dtype_pun.ll120 ; CHECK-NEXT: %[[EXTR:.*]] = extractelement <4 x i32> %[[BC]], i32 0
125 ; CHECK-NEXT: %i = phi i32 [ %[[EXTL]], %left ], [ %[[EXTR]], %right ]
/aosp_15_r20/external/llvm/test/CodeGen/AArch64/
H A Darm64-extract.ll47 ; this pattern to a single EXTR.
H A Dextract.ll46 ; this pattern to a single EXTR.
/aosp_15_r20/prebuilts/go/linux-x86/src/crypto/internal/nistec/
Dp256_asm_arm64.s1358 EXTR $1, t0, t1, y0
1359 EXTR $1, t1, t2, y1
1360 EXTR $1, t2, t3, y2
1361 EXTR $1, t3, hlp0, y3
/aosp_15_r20/prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/
Darm64enc.s152 EXTR $35, R22, R12, R8 // 888dd693
305 EXTR $17, R10, R29, R15 // af47ca93
/aosp_15_r20/external/llvm/lib/Target/Mips/
H A DMipsDSPInstrFormats.td281 // EXTR.W sub-class format (type 1).
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsDSPInstrFormats.td280 // EXTR.W sub-class format (type 1).
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/
H A DMipsDSPInstrFormats.td280 // EXTR.W sub-class format (type 1).
/aosp_15_r20/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/
Dtables.go92 EXTR const
561 EXTR: "EXTR",
1245 {0xffe08000, 0x13800000, EXTR, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_immediate_0_31_imms}, nil},
1249 {0xffe00000, 0x93c00000, EXTR, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_immediate_0_63_imms}, nil},
/aosp_15_r20/external/pcre/src/sljit/
H A DsljitNativeARM_64.c99 #define EXTR 0x93c00000 macro
968 …return push_inst(compiler, (EXTR ^ (inv_bits | (inv_bits >> 9))) | RD(dst) | RN(arg1) | RM(arg1) |… in emit_op_imm()
1786 return push_inst(compiler, (EXTR ^ (inv_bits | (inv_bits >> 9))) | RD(dst_reg) in sljit_emit_shift_into()

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