| /aosp_15_r20/prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| D | s390x.s | 123 DIVWU R1, R2 // a7a90000b90400b2b99700a1b904002b
124 DIVWU R1, R2, R3 // a7a90000b90400b2b99700a1b904003b
|
| D | ppc64.s | 394 DIVWU R3, R4, R5 // 7ca41b96
|
| /aosp_15_r20/external/pcre/src/sljit/ |
| H A D | sljitNativePPC_common.c | 167 #define DIVWU (HI(31) | LO(459)) macro
1388 …FAIL_IF(push_inst(compiler, (int_op ? (op == SLJIT_DIVMOD_UW ? DIVWU : DIVW) : (op == SLJIT_DIVMOD… in sljit_emit_op0()
1391 …FAIL_IF(push_inst(compiler, (op == SLJIT_DIVMOD_UW ? DIVWU : DIVW) | D(SLJIT_R0) | A(SLJIT_R0) | B… in sljit_emit_op0()
1398 …return push_inst(compiler, (int_op ? (op == SLJIT_DIV_UW ? DIVWU : DIVW) : (op == SLJIT_DIV_UW ? D… in sljit_emit_op0()
1400 …return push_inst(compiler, (op == SLJIT_DIV_UW ? DIVWU : DIVW) | D(SLJIT_R0) | A(SLJIT_R0) | B(SLJ… in sljit_emit_op0()
|
| /aosp_15_r20/prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/_gen/ |
| D | PPC64.rules | 34 (Mod32u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVWU x y)))
47 (Div32u ...) => (DIVWU ...)
49 (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
51 (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))
|
| D | S390X.rules | 27 // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
30 (Div32u x y) => (DIVWU (MOVWZreg x) y)
32 (Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y))
34 (Div8u x y) => (DIVWU (MOVBZreg x) (MOVBZreg y))
|
| D | 386.rules | 28 (Div8u x y) => (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))
|
| D | AMD64.rules | 27 (Div8u x y) => (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
60 (Mod8u x y) => (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
|
| /aosp_15_r20/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/ |
| D | tables.go | 1086 DIVWU const
2506 DIVWU: "divwu",
5112 …{DIVWU, 0xfc0007ff00000000, 0x7c00039600000000, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,…
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | P10InstrResources.td | 483 DIVWU,
|
| H A D | P9InstrResources.td | 948 DIVWU,
|
| H A D | PPCInstrInfo.td | 2785 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 950 DIVWU,
|
| H A D | PPCInstrInfo.td | 2879 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| H A D | PPCGenMCCodeEmitter.inc | 596 UINT64_C(2080375702), // DIVWU
4879 case PPC::DIVWU:
7006 CEFBS_None, // DIVWU = 583
|
| H A D | PPCGenFastISel.inc | 2870 return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
|
| H A D | PPCGenInstrInfo.inc | 598 DIVWU = 583,
3567 …583, 3, 1, 4, 236, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #583 = DIVWU
12615 { PPC::DIVWU_rec, PPC::DIVWU },
12816 { PPC::DIVWU, PPC::DIVWU_rec },
|
| H A D | PPCGenAsmWriter.inc | 2251 26819U, // DIVWU
4542 38U, // DIVWU
|
| H A D | PPCGenDisassemblerTables.inc | 1430 /* 6487 */ MCD::OPC_Decode, 199, 4, 64, // Opcode: DIVWU
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/PowerPC/ |
| H A D | PPCGenInstrInfo.inc | 708 DIVWU = 693,
5544 { 693, 3, 1, 4, 238, 0, 0, 0, 0x8ULL, nullptr, OperandInfo65 }, // Inst #693 = DIVWU
10969 /* DIVWU */
16194 /* DIVWU */
20857 CEFBS_None, // DIVWU = 693
22926 { PPC::DIVWU_rec, PPC::DIVWU },
23132 { PPC::DIVWU, PPC::DIVWU_rec },
|
| H A D | PPCGenMCCodeEmitter.inc | 706 UINT64_C(2080375702), // DIVWU
5858 case PPC::DIVWU:
|
| H A D | PPCGenAsmWriter.inc | 2546 1073785971U, // DIVWU
5182 70U, // DIVWU
7818 0U, // DIVWU
|
| H A D | PPCGenFastISel.inc | 4298 return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op1);
|
| /aosp_15_r20/external/capstone/arch/PowerPC/ |
| H A D | PPCGenAsmWriter.inc | 278 23526U, // DIVWU
1800 0U, // DIVWU
|
| H A D | PPCGenDisassemblerTables.inc | 961 /* 3872 */ MCD_OPC_Decode, 130, 2, 42, // Opcode: DIVWU
|
| /aosp_15_r20/external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 2460 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|