Searched refs:wayIdx (Results 1 – 3 of 3) sorted by relevance
| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | TLBStorage.scala | 114 val refill_mask = Mux(io.w.valid, UIntToOH(io.w.bits.wayIdx), 0.U(nWays.W))
170 v(io.w.bits.wayIdx) := true.B
171 entries(io.w.bits.wayIdx).apply(io.w.bits.data)
178 val refill_wayIdx_reg = RegEnable(io.w.bits.wayIdx, io.w.valid)
257 XSPerfAccumulate(s"refill${i}", io.w.valid && io.w.bits.wayIdx === i.U)
417 wayIdx = refill_idx,
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| H A D | MMUBundle.scala | 430 val wayIdx = Output(UInt(log2Up(nWays).W)) constant
446 def w_apply(valid: Bool, wayIdx: UInt, data: PtwRespS2): Unit = {
448 this.w.bits.wayIdx := wayIdx
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/data/ |
| H A D | BankedDataArray.scala | 99 class DataSRAM(bankIdx: Int, wayIdx: Int)(implicit p: Parameters) extends DCacheModule {
142 wayIdx.U,
152 wayIdx.U,
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