Searched refs:valid_array (Results 1 – 2 of 2) sorted by relevance
87 val valid_array = Module(new SyncDataModuleTemplate( constant105 valid_array.io.wen(i) := false.B106 valid_array.io.waddr(i) := 0.U107 valid_array.io.wdata(i) := false.B131 valid_array.io.ren.get(i) := io.ren(i)133 valid_array.io.raddr(i) := io.raddr(i)137 io.rdata(i).valid := valid_array.io.rdata(i)162 valid_array.io.wen(SSIT_MISC_WRITE_PORT) := true.B163 valid_array.io.waddr(SSIT_MISC_WRITE_PORT) := resetStepCounter164 valid_array.io.wdata(SSIT_MISC_WRITE_PORT) := false.B[all …]
312 private val valid_array = RegInit(VecInit(Seq.fill(nWays)(0.U(nSets.W))))317 valid_metas(i)(way) := valid_array(way)(read_set_idx_next(i))328 valid_array(way_num) := valid_array(way_num).bitSet(io.write.bits.virIdx, true.B)368 valid_array(w) := (0 until PortNumber).map { i =>372 valid_array(w).bitSet(io.flush(i).bits.virIdx, false.B),373 valid_array(w)381 (0 until nWays).foreach(w => valid_array(w) := 0.U)