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Searched refs:tEnable (Results 1 – 3 of 3) sorted by relevance

/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/
H A DDebug.scala112 case (tEnable, mod) => tEnable && mod.isFetchTrigger
115 case (tEnable, mod) => tEnable && mod.isMemAccTrigger
/XiangShan/src/main/scala/xiangshan/mem/
H A DMemBlock.scala794 val tEnable = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) constant
795 tEnable := csrCtrl.mem_trigger.tEnableVec
805 XSDebug(tEnable.asUInt.orR, "Debug Mode: At least one store trigger is enabled\n")
807 PrintTriggerInfo(tEnable(j), tdata(j))
1018 loadUnits(i).io.fromCsrTrigger.tEnableVec := tEnable
1155 hybridUnits(i).io.fromCsrTrigger.tEnableVec := tEnable
1243 stu.io.fromCsrTrigger.tEnableVec := tEnable
1998 vSegmentUnit.io.fromCsrTrigger.tEnableVec := tEnable
/XiangShan/src/main/scala/xiangshan/mem/pipeline/
H A DLoadUnit.scala108 val tEnable = Input(Bool()) // timing is calculated before this constant