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/XiangShan/src/main/scala/xiangshan/backend/fu/
H A DRadix2Divider.scala46 val shiftReg = Reg(UInt((1 + len * 2).W)) constant
47 val hi = shiftReg(len * 2, len)
48 val lo = shiftReg(len - 1, 0)
79 shiftReg := aValx2Reg << cnt.value
83 shiftReg := Cat(Mux(enough, hi - bReg, hi)(len - 1, 0), lo, enough)