Home
last modified time | relevance | path

Searched refs:s2_reg_en (Results 1 – 1 of 1) sorted by relevance

/XiangShan/src/main/scala/xiangshan/mem/prefetch/
H A DSMSPrefetcher.scala699 val s2_reg_en = s1_valid && !s1_wait constant
700 val s2_hist_update_mask = RegEnable(s1_hist_update_mask, s2_reg_en)
701 val s2_single_update = RegEnable(s1_single_update, s2_reg_en)
702 val s2_has_been_single_update = RegEnable(s1_has_been_single_update, s2_reg_en)
703 val s2_hist_bits = RegEnable(s1_hist_bits, s2_reg_en)
704 val s2_hist_bit_single = RegEnable(s1_hist_single_bit, s2_reg_en)
705 val s2_tag = RegEnable(s1_tag, s2_reg_en)
706 val s2_region_bits = RegEnable(s1_region_bits, s2_reg_en)
707 val s2_decr_mode = RegEnable(s1_decr_mode, s2_reg_en)
708 val s2_region_paddr = RegEnable(s1_region_paddr, s2_reg_en)
[all …]