Home
last modified time | relevance | path

Searched refs:reqSelPort (Results 1 – 1 of 1) sorted by relevance

/XiangShan/src/main/scala/xiangshan/mem/lsqueue/
H A DStoreMisalignBuffer.scala152 val reqSelPort = reqSel._3(0) constant
160 val s2_reqSelPort = GatedRegNext(reqSelPort)
168 req.portIndex := reqSelPort
179 req.portIndex := reqSelPort
188 val reqSelCanEnq = UIntToOH(reqSelPort)