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/XiangShan/src/main/scala/xiangshan/mem/lsqueue/
H A DLoadQueueRAR.scala132 val release2Cycle = RegEnable(io.release, io.release.valid) constant
133 release2Cycle.valid := RegNext(io.release.valid)
180 (release2Cycle.valid &&
181 …enq.bits.paddr(PAddrBits-1, DCacheLineOffset) === release2Cycle.bits.paddr(PAddrBits-1, DCacheLine…