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Searched refs:mem_resp_hit (Results 1 – 1 of 1) sorted by relevance

/XiangShan/src/main/scala/xiangshan/cache/mmu/
H A DPageTableWalker.scala809 val mem_resp_hit = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(false.B))) constant
841 mem_resp_hit(enq_ptr) := to_bitmap_req || to_mem_out || to_last_hptw_req
857 mem_resp_hit(enq_ptr) := false.B
914 mem_resp_hit(i) := true.B
924 way_info.get(i) := DataHoldBypass(io.l0_way_info.get, mem_resp_hit(i))
998 mem_resp_hit.map(a => when (a) { a := false.B } )
1059 io.mem.buffer_it := mem_resp_hit