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Searched refs:issueStd (Results 1 – 3 of 3) sorted by relevance

/XiangShan/src/main/scala/xiangshan/
H A DXSCore.scala210 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd
/XiangShan/src/main/scala/xiangshan/mem/
H A DMemBlock.scala120 val issueStd = MixedVec(Seq.fill(StdCnt)(Flipped(DecoupledIO(new MemExuInput)))) constant
124 def issueUops = issueLda ++ issueSta ++ issueStd ++ issueHya ++ issueVldu
1220 stdExeUnits(i).io.in.valid := io.ooo_to_mem.issueStd(i).valid
1221 io.ooo_to_mem.issueStd(i).ready := stdExeUnits(i).io.in.ready
1222 stdExeUnits(i).io.in.bits := io.ooo_to_mem.issueStd(i).bits
/XiangShan/src/main/scala/xiangshan/backend/
H A DBackend.scala1012 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) constant
1032 issueStd