Searched refs:isV0 (Results 1 – 6 of 6) sorted by relevance
449 o.toVPRF.r(idx).bits.isV0 := (regMaps(oldVdLoc).lreg === 0.U) && (idx == 0).B452 …o.toVPRF.r(idx + maxMergeNumPerCycle).bits.isV0 := (regMaps(newVdLoc).lreg === 0.U) && (idx == 0).B464 o.toVPRF.r(idx).bits.isV0 := (regMaps(oldVdLoc).lreg === 0.U) && (idx == 0).B467 o.toVPRF.r(idx + maxMergeNumPerCycle).bits.isV0 := false.B481 w.bits.isV0 := (regMaps(newVdLoc).lreg === 0.U) && (idx == 0).B528 val isV0 = Bool() constant532 val isV0 = Bool() constant
330 SrcType.isV0(srcType) && this.v0Wen354 SrcType.isV0(srcType) && this.v0Wen
388 when (fromVecExcp.r(i).valid && !fromVecExcp.r(i).bits.isV0) {393 when (fromVecExcp.r(i).valid && fromVecExcp.r(i).bits.isV0) {400 when (fromVecExcp.w(i).valid && !fromVecExcp.w(i).bits.isV0) {407 when(fromVecExcp.w(i).valid && fromVecExcp.w(i).bits.isV0) {692 (SrcType.isV0(s1_srcType(i)(j)(k)) -> s1_v0PregRData(i)(j)(k)))767 RegEnable(!fromVecExcp.r(i).bits.isV0, fromVecExcp.r(i).valid),
341 val isV0 = Bool() constant
51 def isV0(srcType: UInt) = srcType(3) method
301 case 3 => SrcType.isV0(fromRename(i).bits.srcType(j))