Searched refs:intrBitSetReg (Results 1 – 2 of 2) sorted by relevance
47 val intrBitSetReg = Input(Bool()) constant66 val intrEnable = io.intrBitSetReg && !io.hasNoSpecExec && io.interrupt_safe
561 val intrBitSetReg = RegNext(io.csr.intrBitSet) constant562 val intrEnable = intrBitSetReg && !hasWaitForward && deqPtrEntry.interrupt_safe && !deqHasFlushed762 …nlyOneCommit = VecInit(robDeqGroup.map(x => x.commit_v && x.needFlush)).asUInt.orR || intrBitSetReg851 deqPtrGenModule.io.intrBitSetReg := intrBitSetReg