Searched refs:intSchdVlWbPort (Results 1 – 3 of 3) sorted by relevance
| /XiangShan/src/main/scala/xiangshan/backend/rename/ |
| H A D | BusyTable.scala | 207 var intSchdVlWbPort = p(XSCoreParamsKey).intSchdVlWbPort variable
213 …val intVlWb = Mux(io.wbPregs(intSchdVlWbPort).valid, UIntToOH(io.wbPregs(intSchdVlWbPort).bits), 0…
216 …val otherPortsWb = io.wbPregs.zipWithIndex.filter(x => x._2 != intSchdVlWbPort && x._2 != vfSchdVl…
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| /XiangShan/src/main/scala/xiangshan/backend/issue/ |
| H A D | EntryBundles.scala | 212 var intSchdVlWbPort = p(XSCoreParamsKey).intSchdVlWbPort variable
215 common.vlWakeupByIntWb := wakeUpFromVl(numVecWb + numV0Wb + intSchdVlWbPort)
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| /XiangShan/src/main/scala/xiangshan/ |
| H A D | Parameters.scala | 211 intSchdVlWbPort: Int = 0,
407 …, Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(por…
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