Searched refs:in1 (Results 1 – 3 of 3) sorted by relevance
744 val in1 = new Bundle { constant762 when(io.in1.aw.fire) {771 aw_choice := Mux(validMask, !io.in0.aw.valid, io.in1.aw.valid)784 io.in1.aw.ready := reg_idle && aw_choice && aw_queue.io.enq.ready785 aw_queue.io.enq.valid := (io.in0.aw.valid || io.in1.aw.valid) && reg_idle786 aw_queue.io.enq.bits := Mux(aw_choice, io.in1.aw.bits, io.in0.aw.bits)794 io.in1.w.ready := (aw_queue.io.enq.fire || !reg_idle) && used_w_choice && io.out.w.ready796 …io.out.w.valid := (aw_queue.io.enq.fire || !reg_idle) && Mux(used_w_choice, io.in1.w.valid, io.in0…797 io.out.w.bits := Mux(used_w_choice, io.in1.w.bits, io.in0.w.bits)
1111 …write_arb.io.in1.aw.valid := waddr_q.io.deq.valid && (waddr_q.io.deq.bits.len =/=0.U || write_mach…1112 …waddr_q.io.deq.ready := write_arb.io.in1.aw.ready && (waddr_q.io.deq.bits.len =/=0.U || write_mach…1113 write_machine.io.uncache_commit := write_arb.io.in1.aw.fire1114 write_arb.io.in1.aw.bits := waddr_q.io.deq.bits1115 write_arb.io.in1.w :<>= wdata_encpipe.io.out_w
214 val in1 = Mux(isWiden, constant231 vectorCvt1.src := in1