Searched refs:fromVlWb (Results 1 – 2 of 2) sorted by relevance
257 private val vlRfWen = Wire(Vec(io.fromVlWb.length, Bool()))258 private val vlRfWaddr = Wire(Vec(io.fromVlWb.length, UInt(log2Up(VlPhyRegs).W)))259 private val vlRfWdata = Wire(Vec(io.fromVlWb.length, UInt(VlData().dataWidth.W)))416 vlRfWaddr := io.fromVlWb.map(x => RegEnable(x.addr, x.wen)).toSeq417 vlRfWdata := io.fromVlWb.map(x => RegEnable(x.data, x.wen)).toSeq418 vlRfWen := io.fromVlWb.map(x => RegNext(x.wen)).toSeq951 val fromVlWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVlWriteBackBundle) constant
491 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg