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Searched refs:connectSamePort (Results 1 – 8 of 8) sorted by relevance

/XiangShan/src/main/scala/xiangshan/mem/
H A DBundles.scala133 connectSamePort(this, inputReg)
162 connectSamePort(this, inputReg)
/XiangShan/src/main/scala/xiangshan/backend/issue/
H A DMultiWakeupQueue.scala6 import xiangshan.backend.Bundles.{ExuInput, connectSamePort}
H A DScheduler.scala211 connectSamePort(wakeUp,wakeUpIn)
231 connectSamePort(wakeUp, wakeUpIn)
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/
H A DStoreMisalignBuffer.scala167 connectSamePort(req, reqSelBits)
178 connectSamePort(req, reqSelBits)
/XiangShan/src/main/scala/xiangshan/backend/datapath/
H A DBypassNetwork.scala134 connectSamePort(sink.bits, source.bits)
/XiangShan/src/main/scala/xiangshan/mem/pipeline/
H A DStoreUnit.scala26 import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput, connectSamePort}
506 connectSamePort(s2_misalign_stout.bits, s2_out)
H A DLoadUnit.scala26 import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput, connectSamePort}
1169 connectSamePort(s3_misalign_wakeup_req_bits, io.misalign_ldin.bits)
/XiangShan/src/main/scala/xiangshan/backend/
H A DBundles.scala36 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { method