Searched refs:VAddrData (Results 1 – 8 of 8) sorted by relevance
/XiangShan/src/main/scala/xiangshan/backend/datapath/ |
H A D | PcTargetMem.scala | 9 import xiangshan.backend.datapath.DataConfig.VAddrData 28 …private val targetPCVec : Vec[UInt] = Wire(Vec(params.numTargetReadPort, UInt(VAddrData().dataWidt… 29 …private val pcVec : Vec[UInt] = Wire(Vec(params.numPcMemReadPort, UInt(VAddrData().dataWidth… 71 val toDataPathTargetPC = Output(Vec(params.numTargetReadPort, UInt(VAddrData().dataWidth.W))) 73 val toDataPathPC = Output(Vec(params.numPcMemReadPort, UInt(VAddrData().dataWidth.W)))
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H A D | DataConfig.scala | 19 …case class VAddrData()(implicit p: Parameters) extends DataConfig("vaddr", 48 + 2) // Todo: associ… caseClass
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/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/ |
H A D | JumpUnit.scala | 8 import xiangshan.backend.datapath.DataConfig.VAddrData 46 …redirect.cfiUpdate.isMisPred := jumpDataModule.io.target(VAddrData().dataWidth - 1, 0) =/= jmpTarg…
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H A D | BranchUnit.scala | 9 import xiangshan.backend.datapath.DataConfig.VAddrData
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/XiangShan/src/main/scala/xiangshan/backend/fu/ |
H A D | FuncUnit.scala | 32 val target = UInt(VAddrData().dataWidth.W) 58 val pc = OptionWrapper(cfg.needPc, UInt(VAddrData().dataWidth.W))
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/XiangShan/src/main/scala/xiangshan/backend/ |
H A D | Bundles.scala | 626 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 633 val target = UInt(VAddrData().dataWidth.W) 861 val pc = UInt(VAddrData().dataWidth.W)
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H A D | CtrlBlock.scala | 29 import xiangshan.backend.datapath.DataConfig.{FpData, IntData, V0Data, VAddrData, VecData, VlData}
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/XiangShan/src/main/scala/xiangshan/backend/issue/ |
H A D | Entries.scala | 11 import xiangshan.backend.datapath.DataConfig.VAddrData
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