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Searched refs:MissReadyGen (Results 1 – 1 of 1) sorted by relevance

/XiangShan/src/main/scala/xiangshan/cache/dcache/
H A DDCacheWrapper.scala887 class MissReadyGen(val n: Int)(implicit p: Parameters) extends XSModule { class
1441 val missReadyGen = Module(new MissReadyGen(MissReqPortCount))