1 /*
2 * Copyright 2024 Intel Corporation
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include <gtest/gtest.h>
7 #include "brw_fs.h"
8 #include "brw_fs_builder.h"
9 #include "brw_cfg.h"
10
11 using namespace brw;
12
13 class cse_test : public ::testing::Test {
14 protected:
15 cse_test();
16 ~cse_test() override;
17
18 struct brw_compiler *compiler;
19 struct brw_compile_params params;
20 struct intel_device_info *devinfo;
21 void *ctx;
22 struct brw_wm_prog_data *prog_data;
23 struct gl_shader_program *shader_prog;
24 fs_visitor *v;
25 fs_builder bld;
26 };
27
28 class cse_fs_visitor : public fs_visitor
29 {
30 public:
cse_fs_visitor(struct brw_compiler * compiler,struct brw_compile_params * params,struct brw_wm_prog_data * prog_data,nir_shader * shader)31 cse_fs_visitor(struct brw_compiler *compiler,
32 struct brw_compile_params *params,
33 struct brw_wm_prog_data *prog_data,
34 nir_shader *shader)
35 : fs_visitor(compiler, params, NULL,
36 &prog_data->base, shader, 16, false, false) {}
37 };
38
39
cse_test()40 cse_test::cse_test()
41 : bld(NULL, 0)
42 {
43 ctx = ralloc_context(NULL);
44 compiler = rzalloc(ctx, struct brw_compiler);
45 devinfo = rzalloc(ctx, struct intel_device_info);
46 compiler->devinfo = devinfo;
47
48 params = {};
49 params.mem_ctx = ctx;
50
51 prog_data = ralloc(ctx, struct brw_wm_prog_data);
52 nir_shader *shader =
53 nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL);
54
55 v = new cse_fs_visitor(compiler, ¶ms, prog_data, shader);
56
57 bld = fs_builder(v).at_end();
58
59 devinfo->verx10 = 125;
60 devinfo->ver = devinfo->verx10 / 10;
61 }
62
~cse_test()63 cse_test::~cse_test()
64 {
65 delete v;
66 v = NULL;
67
68 ralloc_free(ctx);
69 ctx = NULL;
70 }
71
72
73 static fs_inst *
instruction(bblock_t * block,int num)74 instruction(bblock_t *block, int num)
75 {
76 fs_inst *inst = (fs_inst *)block->start();
77 for (int i = 0; i < num; i++) {
78 inst = (fs_inst *)inst->next;
79 }
80 return inst;
81 }
82
83 static bool
cse(fs_visitor * v)84 cse(fs_visitor *v)
85 {
86 const bool print = false;
87
88 if (print) {
89 fprintf(stderr, "= Before =\n");
90 v->cfg->dump();
91 }
92
93 bool ret = brw_fs_opt_cse_defs(*v);
94
95 if (print) {
96 fprintf(stderr, "\n= After =\n");
97 v->cfg->dump();
98 }
99
100 return ret;
101 }
102
TEST_F(cse_test,add3_invalid)103 TEST_F(cse_test, add3_invalid)
104 {
105 brw_reg dst0 = bld.null_reg_d();
106 brw_reg src0 = bld.vgrf(BRW_TYPE_D);
107 brw_reg src1 = bld.vgrf(BRW_TYPE_D);
108 brw_reg src2 = bld.vgrf(BRW_TYPE_D);
109 brw_reg src3 = bld.vgrf(BRW_TYPE_D);
110
111 bld.ADD3(dst0, src0, src1, src2)
112 ->conditional_mod = BRW_CONDITIONAL_NZ;
113 bld.ADD3(dst0, src0, src1, src3)
114 ->conditional_mod = BRW_CONDITIONAL_NZ;
115
116 /* = Before =
117 *
118 * 0: add3.nz(16) null src0 src1 src2
119 * 1: add3.nz(16) null src0 src1 src3
120 *
121 * = After =
122 * Same
123 */
124
125 brw_calculate_cfg(*v);
126 bblock_t *block0 = v->cfg->blocks[0];
127
128 EXPECT_EQ(0, block0->start_ip);
129 EXPECT_EQ(1, block0->end_ip);
130
131 EXPECT_FALSE(cse(v));
132 EXPECT_EQ(0, block0->start_ip);
133 EXPECT_EQ(1, block0->end_ip);
134 EXPECT_EQ(BRW_OPCODE_ADD3, instruction(block0, 0)->opcode);
135 EXPECT_EQ(BRW_OPCODE_ADD3, instruction(block0, 1)->opcode);
136 }
137