1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_ll_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F4xx_LL_ADC_H 22 #define __STM32F4xx_LL_ADC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx.h" 30 31 /** @addtogroup STM32F4xx_LL_Driver 32 * @{ 33 */ 34 35 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 36 37 /** @defgroup ADC_LL ADC 38 * @{ 39 */ 40 41 /* Private types -------------------------------------------------------------*/ 42 /* Private variables ---------------------------------------------------------*/ 43 44 /* Private constants ---------------------------------------------------------*/ 45 /** @defgroup ADC_LL_Private_Constants ADC Private Constants 46 * @{ 47 */ 48 49 /* Internal mask for ADC group regular sequencer: */ 50 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ 51 /* - sequencer register offset */ 52 /* - sequencer rank bits position into the selected register */ 53 54 /* Internal register offset for ADC group regular sequencer configuration */ 55 /* (offset placed into a spare area of literal definition) */ 56 #define ADC_SQR1_REGOFFSET 0x00000000U 57 #define ADC_SQR2_REGOFFSET 0x00000100U 58 #define ADC_SQR3_REGOFFSET 0x00000200U 59 #define ADC_SQR4_REGOFFSET 0x00000300U 60 61 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) 62 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 63 64 /* Definition of ADC group regular sequencer bits information to be inserted */ 65 /* into ADC group regular sequencer ranks literals definition. */ 66 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ 67 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ 68 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ 69 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ 70 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ 71 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ 72 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ 73 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ 74 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ 75 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ 76 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ 77 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ 78 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ 79 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ 80 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ 81 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ 82 83 /* Internal mask for ADC group injected sequencer: */ 84 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ 85 /* - data register offset */ 86 /* - offset register offset */ 87 /* - sequencer rank bits position into the selected register */ 88 89 /* Internal register offset for ADC group injected data register */ 90 /* (offset placed into a spare area of literal definition) */ 91 #define ADC_JDR1_REGOFFSET 0x00000000U 92 #define ADC_JDR2_REGOFFSET 0x00000100U 93 #define ADC_JDR3_REGOFFSET 0x00000200U 94 #define ADC_JDR4_REGOFFSET 0x00000300U 95 96 /* Internal register offset for ADC group injected offset configuration */ 97 /* (offset placed into a spare area of literal definition) */ 98 #define ADC_JOFR1_REGOFFSET 0x00000000U 99 #define ADC_JOFR2_REGOFFSET 0x00001000U 100 #define ADC_JOFR3_REGOFFSET 0x00002000U 101 #define ADC_JOFR4_REGOFFSET 0x00003000U 102 103 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) 104 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) 105 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 106 107 /* Internal mask for ADC group regular trigger: */ 108 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ 109 /* - regular trigger source */ 110 /* - regular trigger edge */ 111 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 112 113 /* Mask containing trigger source masks for each of possible */ 114 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 115 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 116 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \ 117 ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \ 118 ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \ 119 ((ADC_CR2_EXTSEL) >> (4U * 3U))) 120 121 /* Mask containing trigger edge masks for each of possible */ 122 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 123 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 124 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \ 125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ 126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ 127 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) 128 129 /* Definition of ADC group regular trigger bits information. */ 130 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ 131 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ 132 133 134 135 /* Internal mask for ADC group injected trigger: */ 136 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ 137 /* - injected trigger source */ 138 /* - injected trigger edge */ 139 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 140 141 /* Mask containing trigger source masks for each of possible */ 142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 144 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \ 145 ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \ 146 ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \ 147 ((ADC_CR2_JEXTSEL) >> (4U * 3U))) 148 149 /* Mask containing trigger edge masks for each of possible */ 150 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 151 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 152 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \ 153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ 154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ 155 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) 156 157 /* Definition of ADC group injected trigger bits information. */ 158 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ 159 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ 160 161 /* Internal mask for ADC channel: */ 162 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ 163 /* - channel identifier defined by number */ 164 /* - channel differentiation between external channels (connected to */ 165 /* GPIO pins) and internal channels (connected to internal paths) */ 166 /* - channel sampling time defined by SMPRx register offset */ 167 /* and SMPx bits positions into SMPRx register */ 168 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) 169 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ 170 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) 171 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ 172 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ 173 174 /* Channel differentiation between external and internal channels */ 175 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ 176 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ 177 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ 178 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) 179 180 /* Internal register offset for ADC channel sampling time configuration */ 181 /* (offset placed into a spare area of literal definition) */ 182 #define ADC_SMPR1_REGOFFSET 0x00000000U 183 #define ADC_SMPR2_REGOFFSET 0x02000000U 184 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) 185 186 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U 187 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ 188 189 /* Definition of channels ID number information to be inserted into */ 190 /* channels literals definition. */ 191 #define ADC_CHANNEL_0_NUMBER 0x00000000U 192 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) 193 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) 194 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 195 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) 196 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 197 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 198 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 199 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) 200 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) 201 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) 202 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 203 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) 204 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 205 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 206 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 207 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) 208 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) 209 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) 210 211 /* Definition of channels sampling time information to be inserted into */ 212 /* channels literals definition. */ 213 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ 214 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ 215 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ 216 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ 217 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ 218 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ 219 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ 220 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ 221 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ 222 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ 223 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ 224 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ 225 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ 226 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ 227 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ 228 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ 229 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ 230 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ 231 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ 232 233 /* Internal mask for ADC analog watchdog: */ 234 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ 235 /* (concatenation of multiple bits used in different analog watchdogs, */ 236 /* (feature of several watchdogs not available on all STM32 families)). */ 237 /* - analog watchdog 1: monitored channel defined by number, */ 238 /* selection of ADC group (ADC groups regular and-or injected). */ 239 240 /* Internal register offset for ADC analog watchdog channel configuration */ 241 #define ADC_AWD_CR1_REGOFFSET 0x00000000U 242 243 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) 244 245 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) 246 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) 247 248 /* Internal register offset for ADC analog watchdog threshold configuration */ 249 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U 250 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U 251 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) 252 253 /* ADC registers bits positions */ 254 #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ 255 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ 256 257 /* ADC internal channels related definitions */ 258 /* Internal voltage reference VrefInt */ 259 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ 260 #define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ 261 /* Temperature sensor */ 262 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ 263 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ 264 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 265 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 266 #define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ 267 268 /** 269 * @} 270 */ 271 272 273 /* Private macros ------------------------------------------------------------*/ 274 /** @defgroup ADC_LL_Private_Macros ADC Private Macros 275 * @{ 276 */ 277 278 /** 279 * @brief Driver macro reserved for internal use: isolate bits with the 280 * selected mask and shift them to the register LSB 281 * (shift mask on register position bit 0). 282 * @param __BITS__ Bits in register 32 bits 283 * @param __MASK__ Mask in register 32 bits 284 * @retval Bits in register 32 bits 285 */ 286 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ 287 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 288 289 /** 290 * @brief Driver macro reserved for internal use: set a pointer to 291 * a register from a register basis from which an offset 292 * is applied. 293 * @param __REG__ Register basis from which the offset is applied. 294 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). 295 * @retval Pointer to register address 296 */ 297 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 298 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 299 300 /** 301 * @} 302 */ 303 304 305 /* Exported types ------------------------------------------------------------*/ 306 #if defined(USE_FULL_LL_DRIVER) 307 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure 308 * @{ 309 */ 310 311 /** 312 * @brief Structure definition of some features of ADC common parameters 313 * and multimode 314 * (all ADC instances belonging to the same ADC common instance). 315 * @note The setting of these parameters by function @ref LL_ADC_CommonInit() 316 * is conditioned to ADC instances state (all ADC instances 317 * sharing the same ADC common instance): 318 * All ADC instances sharing the same ADC common instance must be 319 * disabled. 320 */ 321 typedef struct 322 { 323 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. 324 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE 325 326 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ 327 328 #if defined(ADC_MULTIMODE_SUPPORT) 329 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). 330 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE 331 332 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ 333 334 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. 335 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER 336 337 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ 338 339 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. 340 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY 341 342 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ 343 #endif /* ADC_MULTIMODE_SUPPORT */ 344 345 } LL_ADC_CommonInitTypeDef; 346 347 /** 348 * @brief Structure definition of some features of ADC instance. 349 * @note These parameters have an impact on ADC scope: ADC instance. 350 * Affects both group regular and group injected (availability 351 * of ADC group injected depends on STM32 families). 352 * Refer to corresponding unitary functions into 353 * @ref ADC_LL_EF_Configuration_ADC_Instance . 354 * @note The setting of these parameters by function @ref LL_ADC_Init() 355 * is conditioned to ADC state: 356 * ADC instance must be disabled. 357 * This condition is applied to all ADC features, for efficiency 358 * and compatibility over all STM32 families. However, the different 359 * features can be set under different ADC state conditions 360 * (setting possible with ADC enabled without conversion on going, 361 * ADC enabled with conversion on going, ...) 362 * Each feature can be updated afterwards with a unitary function 363 * and potentially with ADC in a different state than disabled, 364 * refer to description of each function for setting 365 * conditioned to ADC state. 366 */ 367 typedef struct 368 { 369 uint32_t Resolution; /*!< Set ADC resolution. 370 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION 371 372 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ 373 374 uint32_t DataAlignment; /*!< Set ADC conversion data alignment. 375 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN 376 377 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ 378 379 uint32_t SequencersScanMode; /*!< Set ADC scan selection. 380 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION 381 382 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ 383 384 } LL_ADC_InitTypeDef; 385 386 /** 387 * @brief Structure definition of some features of ADC group regular. 388 * @note These parameters have an impact on ADC scope: ADC group regular. 389 * Refer to corresponding unitary functions into 390 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 391 * (functions with prefix "REG"). 392 * @note The setting of these parameters by function @ref LL_ADC_REG_Init() 393 * is conditioned to ADC state: 394 * ADC instance must be disabled. 395 * This condition is applied to all ADC features, for efficiency 396 * and compatibility over all STM32 families. However, the different 397 * features can be set under different ADC state conditions 398 * (setting possible with ADC enabled without conversion on going, 399 * ADC enabled with conversion on going, ...) 400 * Each feature can be updated afterwards with a unitary function 401 * and potentially with ADC in a different state than disabled, 402 * refer to description of each function for setting 403 * conditioned to ADC state. 404 */ 405 typedef struct 406 { 407 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 408 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE 409 @note On this STM32 serie, setting of external trigger edge is performed 410 using function @ref LL_ADC_REG_StartConversionExtTrig(). 411 412 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ 413 414 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. 415 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH 416 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 417 418 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ 419 420 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 421 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE 422 @note This parameter has an effect only if group regular sequencer is enabled 423 (scan length of 2 ranks or more). 424 425 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ 426 427 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). 428 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE 429 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. 430 431 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ 432 433 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. 434 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER 435 436 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ 437 438 } LL_ADC_REG_InitTypeDef; 439 440 /** 441 * @brief Structure definition of some features of ADC group injected. 442 * @note These parameters have an impact on ADC scope: ADC group injected. 443 * Refer to corresponding unitary functions into 444 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 445 * (functions with prefix "INJ"). 446 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() 447 * is conditioned to ADC state: 448 * ADC instance must be disabled. 449 * This condition is applied to all ADC features, for efficiency 450 * and compatibility over all STM32 families. However, the different 451 * features can be set under different ADC state conditions 452 * (setting possible with ADC enabled without conversion on going, 453 * ADC enabled with conversion on going, ...) 454 * Each feature can be updated afterwards with a unitary function 455 * and potentially with ADC in a different state than disabled, 456 * refer to description of each function for setting 457 * conditioned to ADC state. 458 */ 459 typedef struct 460 { 461 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 462 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE 463 @note On this STM32 serie, setting of external trigger edge is performed 464 using function @ref LL_ADC_INJ_StartConversionExtTrig(). 465 466 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ 467 468 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. 469 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH 470 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 471 472 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ 473 474 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 475 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE 476 @note This parameter has an effect only if group injected sequencer is enabled 477 (scan length of 2 ranks or more). 478 479 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ 480 481 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. 482 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO 483 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 484 485 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ 486 487 } LL_ADC_INJ_InitTypeDef; 488 489 /** 490 * @} 491 */ 492 #endif /* USE_FULL_LL_DRIVER */ 493 494 /* Exported constants --------------------------------------------------------*/ 495 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants 496 * @{ 497 */ 498 499 /** @defgroup ADC_LL_EC_FLAG ADC flags 500 * @brief Flags defines which can be used with LL_ADC_ReadReg function 501 * @{ 502 */ 503 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ 504 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 505 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ 506 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ 507 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 508 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ 509 #if defined(ADC_MULTIMODE_SUPPORT) 510 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 511 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 512 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 513 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ 514 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ 515 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ 516 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 517 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 518 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 519 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ 520 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */ 521 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */ 522 #endif 523 /** 524 * @} 525 */ 526 527 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) 528 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions 529 * @{ 530 */ 531 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 532 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ 533 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 534 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose 540 * @{ 541 */ 542 /* List of ADC registers intended to be used (most commonly) with */ 543 /* DMA transfer. */ 544 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ 545 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ 546 #if defined(ADC_MULTIMODE_SUPPORT) 547 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ 548 #endif 549 /** 550 * @} 551 */ 552 553 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 554 * @{ 555 */ 556 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 557 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 558 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */ 559 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */ 560 /** 561 * @} 562 */ 563 564 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels 565 * @{ 566 */ 567 /* Note: Other measurement paths to internal channels may be available */ 568 /* (connections to other peripherals). */ 569 /* If they are not listed below, they do not require any specific */ 570 /* path enable. In this case, Access to measurement path is done */ 571 /* only by selecting the corresponding ADC internal channel. */ 572 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */ 573 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ 574 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ 575 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution 581 * @{ 582 */ 583 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ 584 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */ 585 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */ 586 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment 592 * @{ 593 */ 594 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 595 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ 596 /** 597 * @} 598 */ 599 600 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection 601 * @{ 602 */ 603 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ 604 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ 605 /** 606 * @} 607 */ 608 609 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups 610 * @{ 611 */ 612 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ 613 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ 614 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ 615 /** 616 * @} 617 */ 618 619 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number 620 * @{ 621 */ 622 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 623 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 624 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 625 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 626 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 627 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 628 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 629 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 630 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 631 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 632 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 633 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 634 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 635 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 636 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 637 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 638 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 639 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 640 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 641 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 642 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 643 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) 644 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 645 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ 646 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 647 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 648 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 649 /** 650 * @} 651 */ 652 653 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source 654 * @{ 655 */ 656 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */ 657 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 658 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 659 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 660 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 661 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 662 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 663 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 664 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 665 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 666 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 667 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 668 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 669 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 670 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 671 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 672 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 673 /** 674 * @} 675 */ 676 677 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge 678 * @{ 679 */ 680 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ 681 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ 682 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 683 /** 684 * @} 685 */ 686 687 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode 688 * @{ 689 */ 690 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ 691 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data 697 * @{ 698 */ 699 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ 700 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ 701 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ 702 /** 703 * @} 704 */ 705 706 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions) 707 * @{ 708 */ 709 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */ 710 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */ 711 /** 712 * @} 713 */ 714 715 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length 716 * @{ 717 */ 718 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 719 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ 720 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ 721 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ 722 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ 723 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ 724 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ 725 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ 726 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ 727 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ 728 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ 729 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ 730 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ 731 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ 732 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ 733 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ 734 /** 735 * @} 736 */ 737 738 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode 739 * @{ 740 */ 741 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ 742 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ 743 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ 744 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ 745 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ 746 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ 747 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ 748 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ 749 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ 750 /** 751 * @} 752 */ 753 754 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 755 * @{ 756 */ 757 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ 758 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ 759 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ 760 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ 761 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ 762 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ 763 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ 764 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ 765 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ 766 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ 767 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ 768 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ 769 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ 770 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ 771 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ 772 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ 773 /** 774 * @} 775 */ 776 777 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source 778 * @{ 779 */ 780 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */ 781 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 782 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 783 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 784 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 785 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 786 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 787 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 788 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 789 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 790 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 791 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 792 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ 793 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 794 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 795 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 796 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 797 /** 798 * @} 799 */ 800 801 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge 802 * @{ 803 */ 804 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ 805 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ 806 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ 807 /** 808 * @} 809 */ 810 811 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode 812 * @{ 813 */ 814 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ 815 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ 816 /** 817 * @} 818 */ 819 820 821 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length 822 * @{ 823 */ 824 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 825 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ 826 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ 827 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ 828 /** 829 * @} 830 */ 831 832 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode 833 * @{ 834 */ 835 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ 836 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ 837 /** 838 * @} 839 */ 840 841 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 842 * @{ 843 */ 844 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ 845 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ 846 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ 847 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ 848 /** 849 * @} 850 */ 851 852 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 853 * @{ 854 */ 855 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */ 856 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */ 857 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */ 858 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */ 859 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */ 860 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */ 861 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */ 862 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */ 863 /** 864 * @} 865 */ 866 867 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 868 * @{ 869 */ 870 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ 871 /** 872 * @} 873 */ 874 875 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels 876 * @{ 877 */ 878 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ 879 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ 880 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ 881 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ 882 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ 883 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ 884 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ 885 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ 886 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ 887 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ 888 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ 889 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ 890 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ 891 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ 892 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ 893 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ 894 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ 895 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ 896 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ 897 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ 898 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ 899 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ 900 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ 901 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ 902 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ 903 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ 904 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ 905 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ 906 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ 907 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ 908 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ 909 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ 910 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ 911 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ 912 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ 913 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ 914 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ 915 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ 916 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ 917 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ 918 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ 919 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ 920 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ 921 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ 922 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ 923 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ 924 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ 925 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ 926 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ 927 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ 928 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ 929 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ 930 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ 931 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ 932 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ 933 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ 934 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ 935 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ 936 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ 937 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ 938 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ 939 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ 940 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ 941 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ 942 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ 943 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ 944 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ 945 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) 946 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ 947 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ 948 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ 949 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ 950 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 951 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 952 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 953 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 954 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 955 /** 956 * @} 957 */ 958 959 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds 960 * @{ 961 */ 962 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ 963 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ 964 /** 965 * @} 966 */ 967 968 #if defined(ADC_MULTIMODE_SUPPORT) 969 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 970 * @{ 971 */ 972 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ 973 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ 974 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ 975 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */ 976 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 977 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 978 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 979 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 980 #if defined(ADC3) 981 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */ 982 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 983 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */ 984 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */ 985 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */ 986 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 987 #endif 988 /** 989 * @} 990 */ 991 992 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer 993 * @{ 994 */ 995 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ 996 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ 997 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 998 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 999 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ 1000 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */ 1001 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 1002 /** 1003 * @} 1004 */ 1005 1006 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 1007 * @{ 1008 */ 1009 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/ 1010 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 1011 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 1012 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 1013 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 1014 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 1015 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 1016 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 1017 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ 1018 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ 1019 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ 1020 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ 1021 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */ 1022 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */ 1023 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */ 1024 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */ 1025 /** 1026 * @} 1027 */ 1028 1029 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave 1030 * @{ 1031 */ 1032 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ 1033 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ 1034 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ 1035 /** 1036 * @} 1037 */ 1038 1039 #endif /* ADC_MULTIMODE_SUPPORT */ 1040 1041 1042 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays 1043 * @note Only ADC IP HW delays are defined in ADC LL driver driver, 1044 * not timeout values. 1045 * For details on delays values, refer to descriptions in source code 1046 * above each literal definition. 1047 * @{ 1048 */ 1049 1050 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ 1051 /* not timeout values. */ 1052 /* Timeout values for ADC operations are dependent to device clock */ 1053 /* configuration (system clock versus ADC clock), */ 1054 /* and therefore must be defined in user application. */ 1055 /* Indications for estimation of ADC timeout delays, for this */ 1056 /* STM32 serie: */ 1057 /* - ADC enable time: maximum delay is 2us */ 1058 /* (refer to device datasheet, parameter "tSTAB") */ 1059 /* - ADC conversion time: duration depending on ADC clock and ADC */ 1060 /* configuration. */ 1061 /* (refer to device reference manual, section "Timing") */ 1062 1063 /* Delay for internal voltage reference stabilization time. */ 1064 /* Delay set to maximum value (refer to device datasheet, */ 1065 /* parameter "tSTART"). */ 1066 /* Unit: us */ 1067 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ 1068 1069 /* Delay for temperature sensor stabilization time. */ 1070 /* Literal set to maximum value (refer to device datasheet, */ 1071 /* parameter "tSTART"). */ 1072 /* Unit: us */ 1073 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ 1074 1075 /** 1076 * @} 1077 */ 1078 1079 /** 1080 * @} 1081 */ 1082 1083 1084 /* Exported macro ------------------------------------------------------------*/ 1085 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros 1086 * @{ 1087 */ 1088 1089 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros 1090 * @{ 1091 */ 1092 1093 /** 1094 * @brief Write a value in ADC register 1095 * @param __INSTANCE__ ADC Instance 1096 * @param __REG__ Register to be written 1097 * @param __VALUE__ Value to be written in the register 1098 * @retval None 1099 */ 1100 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 1101 1102 /** 1103 * @brief Read a value in ADC register 1104 * @param __INSTANCE__ ADC Instance 1105 * @param __REG__ Register to be read 1106 * @retval Register value 1107 */ 1108 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 1109 /** 1110 * @} 1111 */ 1112 1113 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro 1114 * @{ 1115 */ 1116 1117 /** 1118 * @brief Helper macro to get ADC channel number in decimal format 1119 * from literals LL_ADC_CHANNEL_x. 1120 * @note Example: 1121 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) 1122 * will return decimal number "4". 1123 * @note The input can be a value from functions where a channel 1124 * number is returned, either defined with number 1125 * or with bitfield (only one bit must be set). 1126 * @param __CHANNEL__ This parameter can be one of the following values: 1127 * @arg @ref LL_ADC_CHANNEL_0 1128 * @arg @ref LL_ADC_CHANNEL_1 1129 * @arg @ref LL_ADC_CHANNEL_2 1130 * @arg @ref LL_ADC_CHANNEL_3 1131 * @arg @ref LL_ADC_CHANNEL_4 1132 * @arg @ref LL_ADC_CHANNEL_5 1133 * @arg @ref LL_ADC_CHANNEL_6 1134 * @arg @ref LL_ADC_CHANNEL_7 1135 * @arg @ref LL_ADC_CHANNEL_8 1136 * @arg @ref LL_ADC_CHANNEL_9 1137 * @arg @ref LL_ADC_CHANNEL_10 1138 * @arg @ref LL_ADC_CHANNEL_11 1139 * @arg @ref LL_ADC_CHANNEL_12 1140 * @arg @ref LL_ADC_CHANNEL_13 1141 * @arg @ref LL_ADC_CHANNEL_14 1142 * @arg @ref LL_ADC_CHANNEL_15 1143 * @arg @ref LL_ADC_CHANNEL_16 1144 * @arg @ref LL_ADC_CHANNEL_17 1145 * @arg @ref LL_ADC_CHANNEL_18 1146 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1147 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 1148 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 1149 * 1150 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 1151 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 1152 * @retval Value between Min_Data=0 and Max_Data=18 1153 */ 1154 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1155 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) 1156 1157 /** 1158 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x 1159 * from number in decimal format. 1160 * @note Example: 1161 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1162 * will return a data equivalent to "LL_ADC_CHANNEL_4". 1163 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1164 * @retval Returned value can be one of the following values: 1165 * @arg @ref LL_ADC_CHANNEL_0 1166 * @arg @ref LL_ADC_CHANNEL_1 1167 * @arg @ref LL_ADC_CHANNEL_2 1168 * @arg @ref LL_ADC_CHANNEL_3 1169 * @arg @ref LL_ADC_CHANNEL_4 1170 * @arg @ref LL_ADC_CHANNEL_5 1171 * @arg @ref LL_ADC_CHANNEL_6 1172 * @arg @ref LL_ADC_CHANNEL_7 1173 * @arg @ref LL_ADC_CHANNEL_8 1174 * @arg @ref LL_ADC_CHANNEL_9 1175 * @arg @ref LL_ADC_CHANNEL_10 1176 * @arg @ref LL_ADC_CHANNEL_11 1177 * @arg @ref LL_ADC_CHANNEL_12 1178 * @arg @ref LL_ADC_CHANNEL_13 1179 * @arg @ref LL_ADC_CHANNEL_14 1180 * @arg @ref LL_ADC_CHANNEL_15 1181 * @arg @ref LL_ADC_CHANNEL_16 1182 * @arg @ref LL_ADC_CHANNEL_17 1183 * @arg @ref LL_ADC_CHANNEL_18 1184 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1185 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 1186 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 1187 * 1188 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 1189 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 1190 * (1) For ADC channel read back from ADC register, 1191 * comparison with internal channel parameter to be done 1192 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1193 */ 1194 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1195 (((__DECIMAL_NB__) <= 9U) \ 1196 ? ( \ 1197 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 1198 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 1199 ) \ 1200 : \ 1201 ( \ 1202 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 1203 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 1204 ) \ 1205 ) 1206 1207 /** 1208 * @brief Helper macro to determine whether the selected channel 1209 * corresponds to literal definitions of driver. 1210 * @note The different literal definitions of ADC channels are: 1211 * - ADC internal channel: 1212 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... 1213 * - ADC external channel (channel connected to a GPIO pin): 1214 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... 1215 * @note The channel parameter must be a value defined from literal 1216 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 1217 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 1218 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), 1219 * must not be a value from functions where a channel number is 1220 * returned from ADC registers, 1221 * because internal and external channels share the same channel 1222 * number in ADC registers. The differentiation is made only with 1223 * parameters definitions of driver. 1224 * @param __CHANNEL__ This parameter can be one of the following values: 1225 * @arg @ref LL_ADC_CHANNEL_0 1226 * @arg @ref LL_ADC_CHANNEL_1 1227 * @arg @ref LL_ADC_CHANNEL_2 1228 * @arg @ref LL_ADC_CHANNEL_3 1229 * @arg @ref LL_ADC_CHANNEL_4 1230 * @arg @ref LL_ADC_CHANNEL_5 1231 * @arg @ref LL_ADC_CHANNEL_6 1232 * @arg @ref LL_ADC_CHANNEL_7 1233 * @arg @ref LL_ADC_CHANNEL_8 1234 * @arg @ref LL_ADC_CHANNEL_9 1235 * @arg @ref LL_ADC_CHANNEL_10 1236 * @arg @ref LL_ADC_CHANNEL_11 1237 * @arg @ref LL_ADC_CHANNEL_12 1238 * @arg @ref LL_ADC_CHANNEL_13 1239 * @arg @ref LL_ADC_CHANNEL_14 1240 * @arg @ref LL_ADC_CHANNEL_15 1241 * @arg @ref LL_ADC_CHANNEL_16 1242 * @arg @ref LL_ADC_CHANNEL_17 1243 * @arg @ref LL_ADC_CHANNEL_18 1244 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1245 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 1246 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 1247 * 1248 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 1249 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 1250 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1251 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1252 */ 1253 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1254 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) 1255 1256 /** 1257 * @brief Helper macro to convert a channel defined from parameter 1258 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 1259 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 1260 * to its equivalent parameter definition of a ADC external channel 1261 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). 1262 * @note The channel parameter can be, additionally to a value 1263 * defined from parameter definition of a ADC internal channel 1264 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), 1265 * a value defined from parameter definition of 1266 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 1267 * or a value from functions where a channel number is returned 1268 * from ADC registers. 1269 * @param __CHANNEL__ This parameter can be one of the following values: 1270 * @arg @ref LL_ADC_CHANNEL_0 1271 * @arg @ref LL_ADC_CHANNEL_1 1272 * @arg @ref LL_ADC_CHANNEL_2 1273 * @arg @ref LL_ADC_CHANNEL_3 1274 * @arg @ref LL_ADC_CHANNEL_4 1275 * @arg @ref LL_ADC_CHANNEL_5 1276 * @arg @ref LL_ADC_CHANNEL_6 1277 * @arg @ref LL_ADC_CHANNEL_7 1278 * @arg @ref LL_ADC_CHANNEL_8 1279 * @arg @ref LL_ADC_CHANNEL_9 1280 * @arg @ref LL_ADC_CHANNEL_10 1281 * @arg @ref LL_ADC_CHANNEL_11 1282 * @arg @ref LL_ADC_CHANNEL_12 1283 * @arg @ref LL_ADC_CHANNEL_13 1284 * @arg @ref LL_ADC_CHANNEL_14 1285 * @arg @ref LL_ADC_CHANNEL_15 1286 * @arg @ref LL_ADC_CHANNEL_16 1287 * @arg @ref LL_ADC_CHANNEL_17 1288 * @arg @ref LL_ADC_CHANNEL_18 1289 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1290 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 1291 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 1292 * 1293 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 1294 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 1295 * @retval Returned value can be one of the following values: 1296 * @arg @ref LL_ADC_CHANNEL_0 1297 * @arg @ref LL_ADC_CHANNEL_1 1298 * @arg @ref LL_ADC_CHANNEL_2 1299 * @arg @ref LL_ADC_CHANNEL_3 1300 * @arg @ref LL_ADC_CHANNEL_4 1301 * @arg @ref LL_ADC_CHANNEL_5 1302 * @arg @ref LL_ADC_CHANNEL_6 1303 * @arg @ref LL_ADC_CHANNEL_7 1304 * @arg @ref LL_ADC_CHANNEL_8 1305 * @arg @ref LL_ADC_CHANNEL_9 1306 * @arg @ref LL_ADC_CHANNEL_10 1307 * @arg @ref LL_ADC_CHANNEL_11 1308 * @arg @ref LL_ADC_CHANNEL_12 1309 * @arg @ref LL_ADC_CHANNEL_13 1310 * @arg @ref LL_ADC_CHANNEL_14 1311 * @arg @ref LL_ADC_CHANNEL_15 1312 * @arg @ref LL_ADC_CHANNEL_16 1313 * @arg @ref LL_ADC_CHANNEL_17 1314 * @arg @ref LL_ADC_CHANNEL_18 1315 */ 1316 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1317 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) 1318 1319 /** 1320 * @brief Helper macro to determine whether the internal channel 1321 * selected is available on the ADC instance selected. 1322 * @note The channel parameter must be a value defined from parameter 1323 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 1324 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 1325 * must not be a value defined from parameter definition of 1326 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 1327 * or a value from functions where a channel number is 1328 * returned from ADC registers, 1329 * because internal and external channels share the same channel 1330 * number in ADC registers. The differentiation is made only with 1331 * parameters definitions of driver. 1332 * @param __ADC_INSTANCE__ ADC instance 1333 * @param __CHANNEL__ This parameter can be one of the following values: 1334 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1335 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 1336 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 1337 * 1338 * (1) On STM32F4, parameter available only on ADC instance: ADC1. 1339 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 1340 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1341 * Value "1" if the internal channel selected is available on the ADC instance selected. 1342 */ 1343 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1344 ( \ 1345 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 1346 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 1347 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ 1348 ) 1349 /** 1350 * @brief Helper macro to define ADC analog watchdog parameter: 1351 * define a single channel to monitor with analog watchdog 1352 * from sequencer channel and groups definition. 1353 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). 1354 * Example: 1355 * LL_ADC_SetAnalogWDMonitChannels( 1356 * ADC1, LL_ADC_AWD1, 1357 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) 1358 * @param __CHANNEL__ This parameter can be one of the following values: 1359 * @arg @ref LL_ADC_CHANNEL_0 1360 * @arg @ref LL_ADC_CHANNEL_1 1361 * @arg @ref LL_ADC_CHANNEL_2 1362 * @arg @ref LL_ADC_CHANNEL_3 1363 * @arg @ref LL_ADC_CHANNEL_4 1364 * @arg @ref LL_ADC_CHANNEL_5 1365 * @arg @ref LL_ADC_CHANNEL_6 1366 * @arg @ref LL_ADC_CHANNEL_7 1367 * @arg @ref LL_ADC_CHANNEL_8 1368 * @arg @ref LL_ADC_CHANNEL_9 1369 * @arg @ref LL_ADC_CHANNEL_10 1370 * @arg @ref LL_ADC_CHANNEL_11 1371 * @arg @ref LL_ADC_CHANNEL_12 1372 * @arg @ref LL_ADC_CHANNEL_13 1373 * @arg @ref LL_ADC_CHANNEL_14 1374 * @arg @ref LL_ADC_CHANNEL_15 1375 * @arg @ref LL_ADC_CHANNEL_16 1376 * @arg @ref LL_ADC_CHANNEL_17 1377 * @arg @ref LL_ADC_CHANNEL_18 1378 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1379 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 1380 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 1381 * 1382 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 1383 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 1384 * (1) For ADC channel read back from ADC register, 1385 * comparison with internal channel parameter to be done 1386 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1387 * @param __GROUP__ This parameter can be one of the following values: 1388 * @arg @ref LL_ADC_GROUP_REGULAR 1389 * @arg @ref LL_ADC_GROUP_INJECTED 1390 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED 1391 * @retval Returned value can be one of the following values: 1392 * @arg @ref LL_ADC_AWD_DISABLE 1393 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 1394 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 1395 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 1396 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 1397 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 1398 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 1399 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 1400 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 1401 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 1402 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 1403 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 1404 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 1405 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 1406 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 1407 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 1408 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 1409 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 1410 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 1411 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 1412 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 1413 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 1414 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 1415 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 1416 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 1417 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 1418 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 1419 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 1420 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 1421 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 1422 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 1423 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 1424 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 1425 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 1426 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 1427 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 1428 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 1429 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 1430 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 1431 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 1432 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 1433 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 1434 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 1435 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 1436 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 1437 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 1438 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 1439 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 1440 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 1441 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 1442 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 1443 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 1444 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 1445 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 1446 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 1447 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 1448 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 1449 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 1450 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 1451 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 1452 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 1453 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 1454 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 1455 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 1456 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) 1457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) 1458 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) 1459 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) 1460 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) 1461 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) 1462 * 1463 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 1464 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 1465 */ 1466 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ 1467 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ 1468 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 1469 : \ 1470 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ 1471 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ 1472 : \ 1473 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 1474 ) 1475 1476 /** 1477 * @brief Helper macro to set the value of ADC analog watchdog threshold high 1478 * or low in function of ADC resolution, when ADC resolution is 1479 * different of 12 bits. 1480 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). 1481 * Example, with a ADC resolution of 8 bits, to set the value of 1482 * analog watchdog threshold high (on 8 bits): 1483 * LL_ADC_SetAnalogWDThresholds 1484 * (< ADCx param >, 1485 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) 1486 * ); 1487 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1488 * @arg @ref LL_ADC_RESOLUTION_12B 1489 * @arg @ref LL_ADC_RESOLUTION_10B 1490 * @arg @ref LL_ADC_RESOLUTION_8B 1491 * @arg @ref LL_ADC_RESOLUTION_6B 1492 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF 1493 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1494 */ 1495 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ 1496 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) 1497 1498 /** 1499 * @brief Helper macro to get the value of ADC analog watchdog threshold high 1500 * or low in function of ADC resolution, when ADC resolution is 1501 * different of 12 bits. 1502 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 1503 * Example, with a ADC resolution of 8 bits, to get the value of 1504 * analog watchdog threshold high (on 8 bits): 1505 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION 1506 * (LL_ADC_RESOLUTION_8B, 1507 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) 1508 * ); 1509 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1510 * @arg @ref LL_ADC_RESOLUTION_12B 1511 * @arg @ref LL_ADC_RESOLUTION_10B 1512 * @arg @ref LL_ADC_RESOLUTION_8B 1513 * @arg @ref LL_ADC_RESOLUTION_6B 1514 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF 1515 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1516 */ 1517 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ 1518 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) 1519 1520 #if defined(ADC_MULTIMODE_SUPPORT) 1521 /** 1522 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1523 * or ADC slave from raw value with both ADC conversion data concatenated. 1524 * @note This macro is intended to be used when multimode transfer by DMA 1525 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1526 * In this case the transferred data need to processed with this macro 1527 * to separate the conversion data of ADC master and ADC slave. 1528 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1529 * @arg @ref LL_ADC_MULTI_MASTER 1530 * @arg @ref LL_ADC_MULTI_SLAVE 1531 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1532 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1533 */ 1534 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1535 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) 1536 #endif 1537 1538 /** 1539 * @brief Helper macro to select the ADC common instance 1540 * to which is belonging the selected ADC instance. 1541 * @note ADC common register instance can be used for: 1542 * - Set parameters common to several ADC instances 1543 * - Multimode (for devices with several ADC instances) 1544 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1545 * @param __ADCx__ ADC instance 1546 * @retval ADC common register instance 1547 */ 1548 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 1549 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 1550 (ADC123_COMMON) 1551 #elif defined(ADC1) && defined(ADC2) 1552 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 1553 (ADC12_COMMON) 1554 #else 1555 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 1556 (ADC1_COMMON) 1557 #endif 1558 1559 /** 1560 * @brief Helper macro to check if all ADC instances sharing the same 1561 * ADC common instance are disabled. 1562 * @note This check is required by functions with setting conditioned to 1563 * ADC state: 1564 * All ADC instances of the ADC common group must be disabled. 1565 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1566 * @note On devices with only 1 ADC common instance, parameter of this macro 1567 * is useless and can be ignored (parameter kept for compatibility 1568 * with devices featuring several ADC common instances). 1569 * @param __ADCXY_COMMON__ ADC common instance 1570 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1571 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1572 * are disabled. 1573 * Value "1" if at least one ADC instance sharing the same ADC common instance 1574 * is enabled. 1575 */ 1576 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 1577 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1578 (LL_ADC_IsEnabled(ADC1) | \ 1579 LL_ADC_IsEnabled(ADC2) | \ 1580 LL_ADC_IsEnabled(ADC3) ) 1581 #elif defined(ADC1) && defined(ADC2) 1582 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1583 (LL_ADC_IsEnabled(ADC1) | \ 1584 LL_ADC_IsEnabled(ADC2) ) 1585 #else 1586 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1587 (LL_ADC_IsEnabled(ADC1)) 1588 #endif 1589 1590 /** 1591 * @brief Helper macro to define the ADC conversion data full-scale digital 1592 * value corresponding to the selected ADC resolution. 1593 * @note ADC conversion data full-scale corresponds to voltage range 1594 * determined by analog voltage references Vref+ and Vref- 1595 * (refer to reference manual). 1596 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1597 * @arg @ref LL_ADC_RESOLUTION_12B 1598 * @arg @ref LL_ADC_RESOLUTION_10B 1599 * @arg @ref LL_ADC_RESOLUTION_8B 1600 * @arg @ref LL_ADC_RESOLUTION_6B 1601 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1602 */ 1603 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1604 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) 1605 1606 /** 1607 * @brief Helper macro to convert the ADC conversion data from 1608 * a resolution to another resolution. 1609 * @param __DATA__ ADC conversion data to be converted 1610 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1611 * This parameter can be one of the following values: 1612 * @arg @ref LL_ADC_RESOLUTION_12B 1613 * @arg @ref LL_ADC_RESOLUTION_10B 1614 * @arg @ref LL_ADC_RESOLUTION_8B 1615 * @arg @ref LL_ADC_RESOLUTION_6B 1616 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1617 * This parameter can be one of the following values: 1618 * @arg @ref LL_ADC_RESOLUTION_12B 1619 * @arg @ref LL_ADC_RESOLUTION_10B 1620 * @arg @ref LL_ADC_RESOLUTION_8B 1621 * @arg @ref LL_ADC_RESOLUTION_6B 1622 * @retval ADC conversion data to the requested resolution 1623 */ 1624 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ 1625 (((__DATA__) \ 1626 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \ 1627 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \ 1628 ) 1629 1630 /** 1631 * @brief Helper macro to calculate the voltage (unit: mVolt) 1632 * corresponding to a ADC conversion data (unit: digital value). 1633 * @note Analog reference voltage (Vref+) must be either known from 1634 * user board environment or can be calculated using ADC measurement 1635 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1636 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) 1637 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1638 * (unit: digital value). 1639 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1640 * @arg @ref LL_ADC_RESOLUTION_12B 1641 * @arg @ref LL_ADC_RESOLUTION_10B 1642 * @arg @ref LL_ADC_RESOLUTION_8B 1643 * @arg @ref LL_ADC_RESOLUTION_6B 1644 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1645 */ 1646 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1647 __ADC_DATA__,\ 1648 __ADC_RESOLUTION__) \ 1649 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ 1650 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1651 ) 1652 1653 /** 1654 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1655 * from ADC conversion data of internal temperature sensor. 1656 * @note Computation is using temperature sensor calibration values 1657 * stored in system memory for each device during production. 1658 * @note Calculation formula: 1659 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1660 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1661 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1662 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1663 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1664 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1665 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1666 * TEMP_DEGC_CAL1 (calibrated in factory) 1667 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1668 * TEMP_DEGC_CAL2 (calibrated in factory) 1669 * Caution: Calculation relevancy under reserve that calibration 1670 * parameters are correct (address and data). 1671 * To calculate temperature using temperature sensor 1672 * datasheet typical values (generic values less, therefore 1673 * less accurate than calibrated values), 1674 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1675 * @note As calculation input, the analog reference voltage (Vref+) must be 1676 * defined as it impacts the ADC LSB equivalent voltage. 1677 * @note Analog reference voltage (Vref+) must be either known from 1678 * user board environment or can be calculated using ADC measurement 1679 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1680 * @note On this STM32 serie, calibration data of temperature sensor 1681 * corresponds to a resolution of 12 bits, 1682 * this is the recommended ADC resolution to convert voltage of 1683 * temperature sensor. 1684 * Otherwise, this macro performs the processing to scale 1685 * ADC conversion data to 12 bits. 1686 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) 1687 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1688 * temperature sensor (unit: digital value). 1689 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1690 * sensor voltage has been measured. 1691 * This parameter can be one of the following values: 1692 * @arg @ref LL_ADC_RESOLUTION_12B 1693 * @arg @ref LL_ADC_RESOLUTION_10B 1694 * @arg @ref LL_ADC_RESOLUTION_8B 1695 * @arg @ref LL_ADC_RESOLUTION_6B 1696 * @retval Temperature (unit: degree Celsius) 1697 */ 1698 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1699 __TEMPSENSOR_ADC_DATA__,\ 1700 __ADC_RESOLUTION__) \ 1701 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ 1702 (__ADC_RESOLUTION__), \ 1703 LL_ADC_RESOLUTION_12B) \ 1704 * (__VREFANALOG_VOLTAGE__)) \ 1705 / TEMPSENSOR_CAL_VREFANALOG) \ 1706 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ 1707 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ 1708 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ 1709 ) + TEMPSENSOR_CAL1_TEMP \ 1710 ) 1711 1712 /** 1713 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1714 * from ADC conversion data of internal temperature sensor. 1715 * @note Computation is using temperature sensor typical values 1716 * (refer to device datasheet). 1717 * @note Calculation formula: 1718 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1719 * / Avg_Slope + CALx_TEMP 1720 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1721 * (unit: digital value) 1722 * Avg_Slope = temperature sensor slope 1723 * (unit: uV/Degree Celsius) 1724 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1725 * temperature CALx_TEMP (unit: mV) 1726 * Caution: Calculation relevancy under reserve the temperature sensor 1727 * of the current device has characteristics in line with 1728 * datasheet typical values. 1729 * If temperature sensor calibration values are available on 1730 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1731 * temperature calculation will be more accurate using 1732 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1733 * @note As calculation input, the analog reference voltage (Vref+) must be 1734 * defined as it impacts the ADC LSB equivalent voltage. 1735 * @note Analog reference voltage (Vref+) must be either known from 1736 * user board environment or can be calculated using ADC measurement 1737 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1738 * @note ADC measurement data must correspond to a resolution of 12bits 1739 * (full scale digital value 4095). If not the case, the data must be 1740 * preliminarily rescaled to an equivalent resolution of 12 bits. 1741 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). 1742 * On STM32F4, refer to device datasheet parameter "Avg_Slope". 1743 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). 1744 * On STM32F4, refer to device datasheet parameter "V25". 1745 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) 1746 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) 1747 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). 1748 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1749 * This parameter can be one of the following values: 1750 * @arg @ref LL_ADC_RESOLUTION_12B 1751 * @arg @ref LL_ADC_RESOLUTION_10B 1752 * @arg @ref LL_ADC_RESOLUTION_8B 1753 * @arg @ref LL_ADC_RESOLUTION_6B 1754 * @retval Temperature (unit: degree Celsius) 1755 */ 1756 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1757 __TEMPSENSOR_TYP_CALX_V__,\ 1758 __TEMPSENSOR_CALX_TEMP__,\ 1759 __VREFANALOG_VOLTAGE__,\ 1760 __TEMPSENSOR_ADC_DATA__,\ 1761 __ADC_RESOLUTION__) \ 1762 ((( ( \ 1763 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ 1764 * 1000) \ 1765 - \ 1766 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ 1767 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ 1768 * 1000) \ 1769 ) \ 1770 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ 1771 ) + (__TEMPSENSOR_CALX_TEMP__) \ 1772 ) 1773 1774 /** 1775 * @} 1776 */ 1777 1778 /** 1779 * @} 1780 */ 1781 1782 1783 /* Exported functions --------------------------------------------------------*/ 1784 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions 1785 * @{ 1786 */ 1787 1788 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management 1789 * @{ 1790 */ 1791 /* Note: LL ADC functions to set DMA transfer are located into sections of */ 1792 /* configuration of ADC instance, groups and multimode (if available): */ 1793 /* @ref LL_ADC_REG_SetDMATransfer(), ... */ 1794 1795 /** 1796 * @brief Function to help to configure DMA transfer from ADC: retrieve the 1797 * ADC register address from ADC instance and a list of ADC registers 1798 * intended to be used (most commonly) with DMA transfer. 1799 * @note These ADC registers are data registers: 1800 * when ADC conversion data is available in ADC data registers, 1801 * ADC generates a DMA transfer request. 1802 * @note This macro is intended to be used with LL DMA driver, refer to 1803 * function "LL_DMA_ConfigAddresses()". 1804 * Example: 1805 * LL_DMA_ConfigAddresses(DMA1, 1806 * LL_DMA_CHANNEL_1, 1807 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), 1808 * (uint32_t)&< array or variable >, 1809 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); 1810 * @note For devices with several ADC: in multimode, some devices 1811 * use a different data register outside of ADC instance scope 1812 * (common data register). This macro manages this register difference, 1813 * only ADC instance has to be set as parameter. 1814 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n 1815 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n 1816 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr 1817 * @param ADCx ADC instance 1818 * @param Register This parameter can be one of the following values: 1819 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA 1820 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) 1821 * 1822 * (1) Available on devices with several ADC instances. 1823 * @retval ADC register address 1824 */ 1825 #if defined(ADC_MULTIMODE_SUPPORT) LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1826 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 1827 { 1828 register uint32_t data_reg_addr = 0U; 1829 1830 if (Register == LL_ADC_DMA_REG_REGULAR_DATA) 1831 { 1832 /* Retrieve address of register DR */ 1833 data_reg_addr = (uint32_t)&(ADCx->DR); 1834 } 1835 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ 1836 { 1837 /* Retrieve address of register CDR */ 1838 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); 1839 } 1840 1841 return data_reg_addr; 1842 } 1843 #else LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1844 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 1845 { 1846 /* Retrieve address of register DR */ 1847 return (uint32_t)&(ADCx->DR); 1848 } 1849 #endif 1850 1851 /** 1852 * @} 1853 */ 1854 1855 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances 1856 * @{ 1857 */ 1858 1859 /** 1860 * @brief Set parameter common to several ADC: Clock source and prescaler. 1861 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock 1862 * @param ADCxy_COMMON ADC common instance 1863 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1864 * @param CommonClock This parameter can be one of the following values: 1865 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 1866 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 1867 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 1868 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 1869 * @retval None 1870 */ LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1871 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) 1872 { 1873 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock); 1874 } 1875 1876 /** 1877 * @brief Get parameter common to several ADC: Clock source and prescaler. 1878 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock 1879 * @param ADCxy_COMMON ADC common instance 1880 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1881 * @retval Returned value can be one of the following values: 1882 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 1883 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 1884 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 1885 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 1886 */ LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)1887 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) 1888 { 1889 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE)); 1890 } 1891 1892 /** 1893 * @brief Set parameter common to several ADC: measurement path to internal 1894 * channels (VrefInt, temperature sensor, ...). 1895 * @note One or several values can be selected. 1896 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 1897 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 1898 * @note Stabilization time of measurement path to internal channel: 1899 * After enabling internal paths, before starting ADC conversion, 1900 * a delay is required for internal voltage reference and 1901 * temperature sensor stabilization time. 1902 * Refer to device datasheet. 1903 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. 1904 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. 1905 * @note ADC internal channel sampling time constraint: 1906 * For ADC conversion of internal channels, 1907 * a sampling time minimum value is required. 1908 * Refer to device datasheet. 1909 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n 1910 * CCR VBATE LL_ADC_SetCommonPathInternalCh 1911 * @param ADCxy_COMMON ADC common instance 1912 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1913 * @param PathInternal This parameter can be a combination of the following values: 1914 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 1915 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 1916 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 1917 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 1918 * @retval None 1919 */ LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1920 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) 1921 { 1922 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal); 1923 } 1924 1925 /** 1926 * @brief Get parameter common to several ADC: measurement path to internal 1927 * channels (VrefInt, temperature sensor, ...). 1928 * @note One or several values can be selected. 1929 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 1930 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 1931 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n 1932 * CCR VBATE LL_ADC_GetCommonPathInternalCh 1933 * @param ADCxy_COMMON ADC common instance 1934 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1935 * @retval Returned value can be a combination of the following values: 1936 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 1937 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 1938 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 1939 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 1940 */ LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1941 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) 1942 { 1943 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE)); 1944 } 1945 1946 /** 1947 * @} 1948 */ 1949 1950 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance 1951 * @{ 1952 */ 1953 1954 /** 1955 * @brief Set ADC resolution. 1956 * Refer to reference manual for alignments formats 1957 * dependencies to ADC resolutions. 1958 * @rmtoll CR1 RES LL_ADC_SetResolution 1959 * @param ADCx ADC instance 1960 * @param Resolution This parameter can be one of the following values: 1961 * @arg @ref LL_ADC_RESOLUTION_12B 1962 * @arg @ref LL_ADC_RESOLUTION_10B 1963 * @arg @ref LL_ADC_RESOLUTION_8B 1964 * @arg @ref LL_ADC_RESOLUTION_6B 1965 * @retval None 1966 */ LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)1967 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) 1968 { 1969 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution); 1970 } 1971 1972 /** 1973 * @brief Get ADC resolution. 1974 * Refer to reference manual for alignments formats 1975 * dependencies to ADC resolutions. 1976 * @rmtoll CR1 RES LL_ADC_GetResolution 1977 * @param ADCx ADC instance 1978 * @retval Returned value can be one of the following values: 1979 * @arg @ref LL_ADC_RESOLUTION_12B 1980 * @arg @ref LL_ADC_RESOLUTION_10B 1981 * @arg @ref LL_ADC_RESOLUTION_8B 1982 * @arg @ref LL_ADC_RESOLUTION_6B 1983 */ LL_ADC_GetResolution(ADC_TypeDef * ADCx)1984 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) 1985 { 1986 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES)); 1987 } 1988 1989 /** 1990 * @brief Set ADC conversion data alignment. 1991 * @note Refer to reference manual for alignments formats 1992 * dependencies to ADC resolutions. 1993 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 1994 * @param ADCx ADC instance 1995 * @param DataAlignment This parameter can be one of the following values: 1996 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 1997 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 1998 * @retval None 1999 */ LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2000 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) 2001 { 2002 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); 2003 } 2004 2005 /** 2006 * @brief Get ADC conversion data alignment. 2007 * @note Refer to reference manual for alignments formats 2008 * dependencies to ADC resolutions. 2009 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 2010 * @param ADCx ADC instance 2011 * @retval Returned value can be one of the following values: 2012 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 2013 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 2014 */ LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2015 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) 2016 { 2017 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); 2018 } 2019 2020 /** 2021 * @brief Set ADC sequencers scan mode, for all ADC groups 2022 * (group regular, group injected). 2023 * @note According to sequencers scan mode : 2024 * - If disabled: ADC conversion is performed in unitary conversion 2025 * mode (one channel converted, that defined in rank 1). 2026 * Configuration of sequencers of all ADC groups 2027 * (sequencer scan length, ...) is discarded: equivalent to 2028 * scan length of 1 rank. 2029 * - If enabled: ADC conversions are performed in sequence conversions 2030 * mode, according to configuration of sequencers of 2031 * each ADC group (sequencer scan length, ...). 2032 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 2033 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 2034 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode 2035 * @param ADCx ADC instance 2036 * @param ScanMode This parameter can be one of the following values: 2037 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 2038 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 2039 * @retval None 2040 */ LL_ADC_SetSequencersScanMode(ADC_TypeDef * ADCx,uint32_t ScanMode)2041 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) 2042 { 2043 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); 2044 } 2045 2046 /** 2047 * @brief Get ADC sequencers scan mode, for all ADC groups 2048 * (group regular, group injected). 2049 * @note According to sequencers scan mode : 2050 * - If disabled: ADC conversion is performed in unitary conversion 2051 * mode (one channel converted, that defined in rank 1). 2052 * Configuration of sequencers of all ADC groups 2053 * (sequencer scan length, ...) is discarded: equivalent to 2054 * scan length of 1 rank. 2055 * - If enabled: ADC conversions are performed in sequence conversions 2056 * mode, according to configuration of sequencers of 2057 * each ADC group (sequencer scan length, ...). 2058 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 2059 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 2060 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode 2061 * @param ADCx ADC instance 2062 * @retval Returned value can be one of the following values: 2063 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 2064 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 2065 */ LL_ADC_GetSequencersScanMode(ADC_TypeDef * ADCx)2066 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) 2067 { 2068 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); 2069 } 2070 2071 /** 2072 * @} 2073 */ 2074 2075 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular 2076 * @{ 2077 */ 2078 2079 /** 2080 * @brief Set ADC group regular conversion trigger source: 2081 * internal (SW start) or from external IP (timer event, 2082 * external interrupt line). 2083 * @note On this STM32 serie, setting of external trigger edge is performed 2084 * using function @ref LL_ADC_REG_StartConversionExtTrig(). 2085 * @note Availability of parameters of trigger sources from timer 2086 * depends on timers availability on the selected device. 2087 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n 2088 * CR2 EXTEN LL_ADC_REG_SetTriggerSource 2089 * @param ADCx ADC instance 2090 * @param TriggerSource This parameter can be one of the following values: 2091 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 2092 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 2093 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 2094 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 2095 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 2096 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 2097 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 2098 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 2099 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 2100 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 2101 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 2102 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 2103 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2 2104 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 2105 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 2106 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 2107 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 2108 * @retval None 2109 */ LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2110 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 2111 { 2112 /* Note: On this STM32 serie, ADC group regular external trigger edge */ 2113 /* is used to perform a ADC conversion start. */ 2114 /* This function does not set external trigger edge. */ 2115 /* This feature is set using function */ 2116 /* @ref LL_ADC_REG_StartConversionExtTrig(). */ 2117 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); 2118 } 2119 2120 /** 2121 * @brief Get ADC group regular conversion trigger source: 2122 * internal (SW start) or from external IP (timer event, 2123 * external interrupt line). 2124 * @note To determine whether group regular trigger source is 2125 * internal (SW start) or external, without detail 2126 * of which peripheral is selected as external trigger, 2127 * (equivalent to 2128 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") 2129 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. 2130 * @note Availability of parameters of trigger sources from timer 2131 * depends on timers availability on the selected device. 2132 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n 2133 * CR2 EXTEN LL_ADC_REG_GetTriggerSource 2134 * @param ADCx ADC instance 2135 * @retval Returned value can be one of the following values: 2136 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 2137 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 2138 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 2139 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 2140 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 2141 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 2142 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 2143 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 2144 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 2145 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 2146 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 2147 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 2148 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2 2149 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 2150 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 2151 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 2152 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 2153 */ LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2154 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) 2155 { 2156 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); 2157 2158 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 2159 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ 2160 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); 2161 2162 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ 2163 /* to match with triggers literals definition. */ 2164 return ((TriggerSource 2165 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL) 2166 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN) 2167 ); 2168 } 2169 2170 /** 2171 * @brief Get ADC group regular conversion trigger source internal (SW start) 2172 or external. 2173 * @note In case of group regular trigger source set to external trigger, 2174 * to determine which peripheral is selected as external trigger, 2175 * use function @ref LL_ADC_REG_GetTriggerSource(). 2176 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart 2177 * @param ADCx ADC instance 2178 * @retval Value "0" if trigger source external trigger 2179 * Value "1" if trigger source SW start. 2180 */ LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2181 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 2182 { 2183 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN)); 2184 } 2185 2186 /** 2187 * @brief Get ADC group regular conversion trigger polarity. 2188 * @note Applicable only for trigger source set to external trigger. 2189 * @note On this STM32 serie, setting of external trigger edge is performed 2190 * using function @ref LL_ADC_REG_StartConversionExtTrig(). 2191 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge 2192 * @param ADCx ADC instance 2193 * @retval Returned value can be one of the following values: 2194 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 2195 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 2196 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 2197 */ LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2198 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) 2199 { 2200 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN)); 2201 } 2202 2203 2204 /** 2205 * @brief Set ADC group regular sequencer length and scan direction. 2206 * @note Description of ADC group regular sequencer features: 2207 * - For devices with sequencer fully configurable 2208 * (function "LL_ADC_REG_SetSequencerRanks()" available): 2209 * sequencer length and each rank affectation to a channel 2210 * are configurable. 2211 * This function performs configuration of: 2212 * - Sequence length: Number of ranks in the scan sequence. 2213 * - Sequence direction: Unless specified in parameters, sequencer 2214 * scan direction is forward (from rank 1 to rank n). 2215 * Sequencer ranks are selected using 2216 * function "LL_ADC_REG_SetSequencerRanks()". 2217 * - For devices with sequencer not fully configurable 2218 * (function "LL_ADC_REG_SetSequencerChannels()" available): 2219 * sequencer length and each rank affectation to a channel 2220 * are defined by channel number. 2221 * This function performs configuration of: 2222 * - Sequence length: Number of ranks in the scan sequence is 2223 * defined by number of channels set in the sequence, 2224 * rank of each channel is fixed by channel HW number. 2225 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 2226 * - Sequence direction: Unless specified in parameters, sequencer 2227 * scan direction is forward (from lowest channel number to 2228 * highest channel number). 2229 * Sequencer ranks are selected using 2230 * function "LL_ADC_REG_SetSequencerChannels()". 2231 * @note On this STM32 serie, group regular sequencer configuration 2232 * is conditioned to ADC instance sequencer mode. 2233 * If ADC instance sequencer mode is disabled, sequencers of 2234 * all groups (group regular, group injected) can be configured 2235 * but their execution is disabled (limited to rank 1). 2236 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 2237 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 2238 * ADC conversion on only 1 channel. 2239 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 2240 * @param ADCx ADC instance 2241 * @param SequencerNbRanks This parameter can be one of the following values: 2242 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 2243 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 2244 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 2245 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 2246 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 2247 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 2248 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 2249 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 2250 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 2251 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 2252 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 2253 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 2254 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 2255 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 2256 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 2257 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 2258 * @retval None 2259 */ LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2260 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 2261 { 2262 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); 2263 } 2264 2265 /** 2266 * @brief Get ADC group regular sequencer length and scan direction. 2267 * @note Description of ADC group regular sequencer features: 2268 * - For devices with sequencer fully configurable 2269 * (function "LL_ADC_REG_SetSequencerRanks()" available): 2270 * sequencer length and each rank affectation to a channel 2271 * are configurable. 2272 * This function retrieves: 2273 * - Sequence length: Number of ranks in the scan sequence. 2274 * - Sequence direction: Unless specified in parameters, sequencer 2275 * scan direction is forward (from rank 1 to rank n). 2276 * Sequencer ranks are selected using 2277 * function "LL_ADC_REG_SetSequencerRanks()". 2278 * - For devices with sequencer not fully configurable 2279 * (function "LL_ADC_REG_SetSequencerChannels()" available): 2280 * sequencer length and each rank affectation to a channel 2281 * are defined by channel number. 2282 * This function retrieves: 2283 * - Sequence length: Number of ranks in the scan sequence is 2284 * defined by number of channels set in the sequence, 2285 * rank of each channel is fixed by channel HW number. 2286 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 2287 * - Sequence direction: Unless specified in parameters, sequencer 2288 * scan direction is forward (from lowest channel number to 2289 * highest channel number). 2290 * Sequencer ranks are selected using 2291 * function "LL_ADC_REG_SetSequencerChannels()". 2292 * @note On this STM32 serie, group regular sequencer configuration 2293 * is conditioned to ADC instance sequencer mode. 2294 * If ADC instance sequencer mode is disabled, sequencers of 2295 * all groups (group regular, group injected) can be configured 2296 * but their execution is disabled (limited to rank 1). 2297 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 2298 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 2299 * ADC conversion on only 1 channel. 2300 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 2301 * @param ADCx ADC instance 2302 * @retval Returned value can be one of the following values: 2303 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 2304 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 2305 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 2306 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 2307 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 2308 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 2309 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 2310 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 2311 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 2312 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 2313 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 2314 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 2315 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 2316 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 2317 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 2318 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 2319 */ LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)2320 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) 2321 { 2322 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); 2323 } 2324 2325 /** 2326 * @brief Set ADC group regular sequencer discontinuous mode: 2327 * sequence subdivided and scan conversions interrupted every selected 2328 * number of ranks. 2329 * @note It is not possible to enable both ADC group regular 2330 * continuous mode and sequencer discontinuous mode. 2331 * @note It is not possible to enable both ADC auto-injected mode 2332 * and ADC group regular sequencer discontinuous mode. 2333 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n 2334 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont 2335 * @param ADCx ADC instance 2336 * @param SeqDiscont This parameter can be one of the following values: 2337 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 2338 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 2339 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 2340 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 2341 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 2342 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 2343 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 2344 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 2345 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 2346 * @retval None 2347 */ LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2348 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 2349 { 2350 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); 2351 } 2352 2353 /** 2354 * @brief Get ADC group regular sequencer discontinuous mode: 2355 * sequence subdivided and scan conversions interrupted every selected 2356 * number of ranks. 2357 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n 2358 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont 2359 * @param ADCx ADC instance 2360 * @retval Returned value can be one of the following values: 2361 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 2362 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 2363 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 2364 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 2365 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 2366 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 2367 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 2368 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 2369 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 2370 */ LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2371 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) 2372 { 2373 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); 2374 } 2375 2376 /** 2377 * @brief Set ADC group regular sequence: channel on the selected 2378 * scan sequence rank. 2379 * @note This function performs configuration of: 2380 * - Channels ordering into each rank of scan sequence: 2381 * whatever channel can be placed into whatever rank. 2382 * @note On this STM32 serie, ADC group regular sequencer is 2383 * fully configurable: sequencer length and each rank 2384 * affectation to a channel are configurable. 2385 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 2386 * @note Depending on devices and packages, some channels may not be available. 2387 * Refer to device datasheet for channels availability. 2388 * @note On this STM32 serie, to measure internal channels (VrefInt, 2389 * TempSensor, ...), measurement paths to internal channels must be 2390 * enabled separately. 2391 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 2392 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n 2393 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n 2394 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n 2395 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n 2396 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n 2397 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n 2398 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n 2399 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n 2400 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n 2401 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n 2402 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n 2403 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n 2404 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n 2405 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n 2406 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n 2407 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks 2408 * @param ADCx ADC instance 2409 * @param Rank This parameter can be one of the following values: 2410 * @arg @ref LL_ADC_REG_RANK_1 2411 * @arg @ref LL_ADC_REG_RANK_2 2412 * @arg @ref LL_ADC_REG_RANK_3 2413 * @arg @ref LL_ADC_REG_RANK_4 2414 * @arg @ref LL_ADC_REG_RANK_5 2415 * @arg @ref LL_ADC_REG_RANK_6 2416 * @arg @ref LL_ADC_REG_RANK_7 2417 * @arg @ref LL_ADC_REG_RANK_8 2418 * @arg @ref LL_ADC_REG_RANK_9 2419 * @arg @ref LL_ADC_REG_RANK_10 2420 * @arg @ref LL_ADC_REG_RANK_11 2421 * @arg @ref LL_ADC_REG_RANK_12 2422 * @arg @ref LL_ADC_REG_RANK_13 2423 * @arg @ref LL_ADC_REG_RANK_14 2424 * @arg @ref LL_ADC_REG_RANK_15 2425 * @arg @ref LL_ADC_REG_RANK_16 2426 * @param Channel This parameter can be one of the following values: 2427 * @arg @ref LL_ADC_CHANNEL_0 2428 * @arg @ref LL_ADC_CHANNEL_1 2429 * @arg @ref LL_ADC_CHANNEL_2 2430 * @arg @ref LL_ADC_CHANNEL_3 2431 * @arg @ref LL_ADC_CHANNEL_4 2432 * @arg @ref LL_ADC_CHANNEL_5 2433 * @arg @ref LL_ADC_CHANNEL_6 2434 * @arg @ref LL_ADC_CHANNEL_7 2435 * @arg @ref LL_ADC_CHANNEL_8 2436 * @arg @ref LL_ADC_CHANNEL_9 2437 * @arg @ref LL_ADC_CHANNEL_10 2438 * @arg @ref LL_ADC_CHANNEL_11 2439 * @arg @ref LL_ADC_CHANNEL_12 2440 * @arg @ref LL_ADC_CHANNEL_13 2441 * @arg @ref LL_ADC_CHANNEL_14 2442 * @arg @ref LL_ADC_CHANNEL_15 2443 * @arg @ref LL_ADC_CHANNEL_16 2444 * @arg @ref LL_ADC_CHANNEL_17 2445 * @arg @ref LL_ADC_CHANNEL_18 2446 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2447 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 2448 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 2449 * 2450 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 2451 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 2452 * @retval None 2453 */ LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2454 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 2455 { 2456 /* Set bits with content of parameter "Channel" with bits position */ 2457 /* in register and register position depending on parameter "Rank". */ 2458 /* Parameters "Rank" and "Channel" are used with masks because containing */ 2459 /* other bits reserved for other purpose. */ 2460 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 2461 2462 MODIFY_REG(*preg, 2463 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), 2464 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); 2465 } 2466 2467 /** 2468 * @brief Get ADC group regular sequence: channel on the selected 2469 * scan sequence rank. 2470 * @note On this STM32 serie, ADC group regular sequencer is 2471 * fully configurable: sequencer length and each rank 2472 * affectation to a channel are configurable. 2473 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 2474 * @note Depending on devices and packages, some channels may not be available. 2475 * Refer to device datasheet for channels availability. 2476 * @note Usage of the returned channel number: 2477 * - To reinject this channel into another function LL_ADC_xxx: 2478 * the returned channel number is only partly formatted on definition 2479 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 2480 * with parts of literals LL_ADC_CHANNEL_x or using 2481 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 2482 * Then the selected literal LL_ADC_CHANNEL_x can be used 2483 * as parameter for another function. 2484 * - To get the channel number in decimal format: 2485 * process the returned value with the helper macro 2486 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 2487 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n 2488 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n 2489 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n 2490 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n 2491 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n 2492 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n 2493 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n 2494 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n 2495 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n 2496 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n 2497 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n 2498 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n 2499 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n 2500 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n 2501 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n 2502 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks 2503 * @param ADCx ADC instance 2504 * @param Rank This parameter can be one of the following values: 2505 * @arg @ref LL_ADC_REG_RANK_1 2506 * @arg @ref LL_ADC_REG_RANK_2 2507 * @arg @ref LL_ADC_REG_RANK_3 2508 * @arg @ref LL_ADC_REG_RANK_4 2509 * @arg @ref LL_ADC_REG_RANK_5 2510 * @arg @ref LL_ADC_REG_RANK_6 2511 * @arg @ref LL_ADC_REG_RANK_7 2512 * @arg @ref LL_ADC_REG_RANK_8 2513 * @arg @ref LL_ADC_REG_RANK_9 2514 * @arg @ref LL_ADC_REG_RANK_10 2515 * @arg @ref LL_ADC_REG_RANK_11 2516 * @arg @ref LL_ADC_REG_RANK_12 2517 * @arg @ref LL_ADC_REG_RANK_13 2518 * @arg @ref LL_ADC_REG_RANK_14 2519 * @arg @ref LL_ADC_REG_RANK_15 2520 * @arg @ref LL_ADC_REG_RANK_16 2521 * @retval Returned value can be one of the following values: 2522 * @arg @ref LL_ADC_CHANNEL_0 2523 * @arg @ref LL_ADC_CHANNEL_1 2524 * @arg @ref LL_ADC_CHANNEL_2 2525 * @arg @ref LL_ADC_CHANNEL_3 2526 * @arg @ref LL_ADC_CHANNEL_4 2527 * @arg @ref LL_ADC_CHANNEL_5 2528 * @arg @ref LL_ADC_CHANNEL_6 2529 * @arg @ref LL_ADC_CHANNEL_7 2530 * @arg @ref LL_ADC_CHANNEL_8 2531 * @arg @ref LL_ADC_CHANNEL_9 2532 * @arg @ref LL_ADC_CHANNEL_10 2533 * @arg @ref LL_ADC_CHANNEL_11 2534 * @arg @ref LL_ADC_CHANNEL_12 2535 * @arg @ref LL_ADC_CHANNEL_13 2536 * @arg @ref LL_ADC_CHANNEL_14 2537 * @arg @ref LL_ADC_CHANNEL_15 2538 * @arg @ref LL_ADC_CHANNEL_16 2539 * @arg @ref LL_ADC_CHANNEL_17 2540 * @arg @ref LL_ADC_CHANNEL_18 2541 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2542 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 2543 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 2544 * 2545 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 2546 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 2547 * (1) For ADC channel read back from ADC register, 2548 * comparison with internal channel parameter to be done 2549 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 2550 */ LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)2551 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 2552 { 2553 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 2554 2555 return (uint32_t) (READ_BIT(*preg, 2556 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) 2557 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) 2558 ); 2559 } 2560 2561 /** 2562 * @brief Set ADC continuous conversion mode on ADC group regular. 2563 * @note Description of ADC continuous conversion mode: 2564 * - single mode: one conversion per trigger 2565 * - continuous mode: after the first trigger, following 2566 * conversions launched successively automatically. 2567 * @note It is not possible to enable both ADC group regular 2568 * continuous mode and sequencer discontinuous mode. 2569 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode 2570 * @param ADCx ADC instance 2571 * @param Continuous This parameter can be one of the following values: 2572 * @arg @ref LL_ADC_REG_CONV_SINGLE 2573 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 2574 * @retval None 2575 */ LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)2576 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) 2577 { 2578 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); 2579 } 2580 2581 /** 2582 * @brief Get ADC continuous conversion mode on ADC group regular. 2583 * @note Description of ADC continuous conversion mode: 2584 * - single mode: one conversion per trigger 2585 * - continuous mode: after the first trigger, following 2586 * conversions launched successively automatically. 2587 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode 2588 * @param ADCx ADC instance 2589 * @retval Returned value can be one of the following values: 2590 * @arg @ref LL_ADC_REG_CONV_SINGLE 2591 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 2592 */ LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)2593 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) 2594 { 2595 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); 2596 } 2597 2598 /** 2599 * @brief Set ADC group regular conversion data transfer: no transfer or 2600 * transfer by DMA, and DMA requests mode. 2601 * @note If transfer by DMA selected, specifies the DMA requests 2602 * mode: 2603 * - Limited mode (One shot mode): DMA transfer requests are stopped 2604 * when number of DMA data transfers (number of 2605 * ADC conversions) is reached. 2606 * This ADC mode is intended to be used with DMA mode non-circular. 2607 * - Unlimited mode: DMA transfer requests are unlimited, 2608 * whatever number of DMA data transfers (number of 2609 * ADC conversions). 2610 * This ADC mode is intended to be used with DMA mode circular. 2611 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 2612 * mode non-circular: 2613 * when DMA transfers size will be reached, DMA will stop transfers of 2614 * ADC conversions data ADC will raise an overrun error 2615 * (overrun flag and interruption if enabled). 2616 * @note For devices with several ADC instances: ADC multimode DMA 2617 * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). 2618 * @note To configure DMA source address (peripheral address), 2619 * use function @ref LL_ADC_DMA_GetRegAddr(). 2620 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n 2621 * CR2 DDS LL_ADC_REG_SetDMATransfer 2622 * @param ADCx ADC instance 2623 * @param DMATransfer This parameter can be one of the following values: 2624 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 2625 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 2626 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 2627 * @retval None 2628 */ LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)2629 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) 2630 { 2631 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer); 2632 } 2633 2634 /** 2635 * @brief Get ADC group regular conversion data transfer: no transfer or 2636 * transfer by DMA, and DMA requests mode. 2637 * @note If transfer by DMA selected, specifies the DMA requests 2638 * mode: 2639 * - Limited mode (One shot mode): DMA transfer requests are stopped 2640 * when number of DMA data transfers (number of 2641 * ADC conversions) is reached. 2642 * This ADC mode is intended to be used with DMA mode non-circular. 2643 * - Unlimited mode: DMA transfer requests are unlimited, 2644 * whatever number of DMA data transfers (number of 2645 * ADC conversions). 2646 * This ADC mode is intended to be used with DMA mode circular. 2647 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 2648 * mode non-circular: 2649 * when DMA transfers size will be reached, DMA will stop transfers of 2650 * ADC conversions data ADC will raise an overrun error 2651 * (overrun flag and interruption if enabled). 2652 * @note For devices with several ADC instances: ADC multimode DMA 2653 * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). 2654 * @note To configure DMA source address (peripheral address), 2655 * use function @ref LL_ADC_DMA_GetRegAddr(). 2656 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n 2657 * CR2 DDS LL_ADC_REG_GetDMATransfer 2658 * @param ADCx ADC instance 2659 * @retval Returned value can be one of the following values: 2660 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 2661 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 2662 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 2663 */ LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)2664 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) 2665 { 2666 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS)); 2667 } 2668 2669 /** 2670 * @brief Specify which ADC flag between EOC (end of unitary conversion) 2671 * or EOS (end of sequence conversions) is used to indicate 2672 * the end of conversion. 2673 * @note This feature is aimed to be set when using ADC with 2674 * programming model by polling or interruption 2675 * (programming model by DMA usually uses DMA interruptions 2676 * to indicate end of conversion and data transfer). 2677 * @note For ADC group injected, end of conversion (flag&IT) is raised 2678 * only at the end of the sequence. 2679 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion 2680 * @param ADCx ADC instance 2681 * @param EocSelection This parameter can be one of the following values: 2682 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 2683 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV 2684 * @retval None 2685 */ LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef * ADCx,uint32_t EocSelection)2686 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection) 2687 { 2688 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection); 2689 } 2690 2691 /** 2692 * @brief Get which ADC flag between EOC (end of unitary conversion) 2693 * or EOS (end of sequence conversions) is used to indicate 2694 * the end of conversion. 2695 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion 2696 * @param ADCx ADC instance 2697 * @retval Returned value can be one of the following values: 2698 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 2699 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV 2700 */ LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef * ADCx)2701 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) 2702 { 2703 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS)); 2704 } 2705 2706 /** 2707 * @} 2708 */ 2709 2710 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected 2711 * @{ 2712 */ 2713 2714 /** 2715 * @brief Set ADC group injected conversion trigger source: 2716 * internal (SW start) or from external IP (timer event, 2717 * external interrupt line). 2718 * @note On this STM32 serie, setting of external trigger edge is performed 2719 * using function @ref LL_ADC_INJ_StartConversionExtTrig(). 2720 * @note Availability of parameters of trigger sources from timer 2721 * depends on timers availability on the selected device. 2722 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n 2723 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource 2724 * @param ADCx ADC instance 2725 * @param TriggerSource This parameter can be one of the following values: 2726 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 2727 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 2728 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 2729 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 2730 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 2731 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2 2732 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 2733 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 2734 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 2735 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 2736 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 2737 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 2738 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO 2739 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 2740 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3 2741 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 2742 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 2743 * @retval None 2744 */ LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2745 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 2746 { 2747 /* Note: On this STM32 serie, ADC group injected external trigger edge */ 2748 /* is used to perform a ADC conversion start. */ 2749 /* This function does not set external trigger edge. */ 2750 /* This feature is set using function */ 2751 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ 2752 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); 2753 } 2754 2755 /** 2756 * @brief Get ADC group injected conversion trigger source: 2757 * internal (SW start) or from external IP (timer event, 2758 * external interrupt line). 2759 * @note To determine whether group injected trigger source is 2760 * internal (SW start) or external, without detail 2761 * of which peripheral is selected as external trigger, 2762 * (equivalent to 2763 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") 2764 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. 2765 * @note Availability of parameters of trigger sources from timer 2766 * depends on timers availability on the selected device. 2767 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n 2768 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource 2769 * @param ADCx ADC instance 2770 * @retval Returned value can be one of the following values: 2771 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 2772 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 2773 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 2774 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 2775 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 2776 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2 2777 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 2778 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 2779 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 2780 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 2781 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 2782 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 2783 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO 2784 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 2785 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3 2786 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 2787 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 2788 */ LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)2789 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) 2790 { 2791 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); 2792 2793 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 2794 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ 2795 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); 2796 2797 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ 2798 /* to match with triggers literals definition. */ 2799 return ((TriggerSource 2800 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL) 2801 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN) 2802 ); 2803 } 2804 2805 /** 2806 * @brief Get ADC group injected conversion trigger source internal (SW start) 2807 or external 2808 * @note In case of group injected trigger source set to external trigger, 2809 * to determine which peripheral is selected as external trigger, 2810 * use function @ref LL_ADC_INJ_GetTriggerSource. 2811 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart 2812 * @param ADCx ADC instance 2813 * @retval Value "0" if trigger source external trigger 2814 * Value "1" if trigger source SW start. 2815 */ LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2816 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 2817 { 2818 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN)); 2819 } 2820 2821 /** 2822 * @brief Get ADC group injected conversion trigger polarity. 2823 * Applicable only for trigger source set to external trigger. 2824 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge 2825 * @param ADCx ADC instance 2826 * @retval Returned value can be one of the following values: 2827 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 2828 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 2829 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 2830 */ LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)2831 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) 2832 { 2833 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN)); 2834 } 2835 2836 /** 2837 * @brief Set ADC group injected sequencer length and scan direction. 2838 * @note This function performs configuration of: 2839 * - Sequence length: Number of ranks in the scan sequence. 2840 * - Sequence direction: Unless specified in parameters, sequencer 2841 * scan direction is forward (from rank 1 to rank n). 2842 * @note On this STM32 serie, group injected sequencer configuration 2843 * is conditioned to ADC instance sequencer mode. 2844 * If ADC instance sequencer mode is disabled, sequencers of 2845 * all groups (group regular, group injected) can be configured 2846 * but their execution is disabled (limited to rank 1). 2847 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 2848 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 2849 * ADC conversion on only 1 channel. 2850 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength 2851 * @param ADCx ADC instance 2852 * @param SequencerNbRanks This parameter can be one of the following values: 2853 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 2854 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 2855 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 2856 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 2857 * @retval None 2858 */ LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2859 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 2860 { 2861 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); 2862 } 2863 2864 /** 2865 * @brief Get ADC group injected sequencer length and scan direction. 2866 * @note This function retrieves: 2867 * - Sequence length: Number of ranks in the scan sequence. 2868 * - Sequence direction: Unless specified in parameters, sequencer 2869 * scan direction is forward (from rank 1 to rank n). 2870 * @note On this STM32 serie, group injected sequencer configuration 2871 * is conditioned to ADC instance sequencer mode. 2872 * If ADC instance sequencer mode is disabled, sequencers of 2873 * all groups (group regular, group injected) can be configured 2874 * but their execution is disabled (limited to rank 1). 2875 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 2876 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 2877 * ADC conversion on only 1 channel. 2878 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength 2879 * @param ADCx ADC instance 2880 * @retval Returned value can be one of the following values: 2881 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 2882 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 2883 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 2884 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 2885 */ LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)2886 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) 2887 { 2888 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); 2889 } 2890 2891 /** 2892 * @brief Set ADC group injected sequencer discontinuous mode: 2893 * sequence subdivided and scan conversions interrupted every selected 2894 * number of ranks. 2895 * @note It is not possible to enable both ADC group injected 2896 * auto-injected mode and sequencer discontinuous mode. 2897 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont 2898 * @param ADCx ADC instance 2899 * @param SeqDiscont This parameter can be one of the following values: 2900 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 2901 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 2902 * @retval None 2903 */ LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2904 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 2905 { 2906 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); 2907 } 2908 2909 /** 2910 * @brief Get ADC group injected sequencer discontinuous mode: 2911 * sequence subdivided and scan conversions interrupted every selected 2912 * number of ranks. 2913 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont 2914 * @param ADCx ADC instance 2915 * @retval Returned value can be one of the following values: 2916 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 2917 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 2918 */ LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)2919 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) 2920 { 2921 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); 2922 } 2923 2924 /** 2925 * @brief Set ADC group injected sequence: channel on the selected 2926 * sequence rank. 2927 * @note Depending on devices and packages, some channels may not be available. 2928 * Refer to device datasheet for channels availability. 2929 * @note On this STM32 serie, to measure internal channels (VrefInt, 2930 * TempSensor, ...), measurement paths to internal channels must be 2931 * enabled separately. 2932 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 2933 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 2934 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 2935 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 2936 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 2937 * @param ADCx ADC instance 2938 * @param Rank This parameter can be one of the following values: 2939 * @arg @ref LL_ADC_INJ_RANK_1 2940 * @arg @ref LL_ADC_INJ_RANK_2 2941 * @arg @ref LL_ADC_INJ_RANK_3 2942 * @arg @ref LL_ADC_INJ_RANK_4 2943 * @param Channel This parameter can be one of the following values: 2944 * @arg @ref LL_ADC_CHANNEL_0 2945 * @arg @ref LL_ADC_CHANNEL_1 2946 * @arg @ref LL_ADC_CHANNEL_2 2947 * @arg @ref LL_ADC_CHANNEL_3 2948 * @arg @ref LL_ADC_CHANNEL_4 2949 * @arg @ref LL_ADC_CHANNEL_5 2950 * @arg @ref LL_ADC_CHANNEL_6 2951 * @arg @ref LL_ADC_CHANNEL_7 2952 * @arg @ref LL_ADC_CHANNEL_8 2953 * @arg @ref LL_ADC_CHANNEL_9 2954 * @arg @ref LL_ADC_CHANNEL_10 2955 * @arg @ref LL_ADC_CHANNEL_11 2956 * @arg @ref LL_ADC_CHANNEL_12 2957 * @arg @ref LL_ADC_CHANNEL_13 2958 * @arg @ref LL_ADC_CHANNEL_14 2959 * @arg @ref LL_ADC_CHANNEL_15 2960 * @arg @ref LL_ADC_CHANNEL_16 2961 * @arg @ref LL_ADC_CHANNEL_17 2962 * @arg @ref LL_ADC_CHANNEL_18 2963 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2964 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 2965 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 2966 * 2967 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 2968 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 2969 * @retval None 2970 */ LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2971 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 2972 { 2973 /* Set bits with content of parameter "Channel" with bits position */ 2974 /* in register depending on parameter "Rank". */ 2975 /* Parameters "Rank" and "Channel" are used with masks because containing */ 2976 /* other bits reserved for other purpose. */ 2977 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; 2978 2979 MODIFY_REG(ADCx->JSQR, 2980 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), 2981 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); 2982 } 2983 2984 /** 2985 * @brief Get ADC group injected sequence: channel on the selected 2986 * sequence rank. 2987 * @note Depending on devices and packages, some channels may not be available. 2988 * Refer to device datasheet for channels availability. 2989 * @note Usage of the returned channel number: 2990 * - To reinject this channel into another function LL_ADC_xxx: 2991 * the returned channel number is only partly formatted on definition 2992 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 2993 * with parts of literals LL_ADC_CHANNEL_x or using 2994 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 2995 * Then the selected literal LL_ADC_CHANNEL_x can be used 2996 * as parameter for another function. 2997 * - To get the channel number in decimal format: 2998 * process the returned value with the helper macro 2999 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 3000 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 3001 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 3002 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 3003 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 3004 * @param ADCx ADC instance 3005 * @param Rank This parameter can be one of the following values: 3006 * @arg @ref LL_ADC_INJ_RANK_1 3007 * @arg @ref LL_ADC_INJ_RANK_2 3008 * @arg @ref LL_ADC_INJ_RANK_3 3009 * @arg @ref LL_ADC_INJ_RANK_4 3010 * @retval Returned value can be one of the following values: 3011 * @arg @ref LL_ADC_CHANNEL_0 3012 * @arg @ref LL_ADC_CHANNEL_1 3013 * @arg @ref LL_ADC_CHANNEL_2 3014 * @arg @ref LL_ADC_CHANNEL_3 3015 * @arg @ref LL_ADC_CHANNEL_4 3016 * @arg @ref LL_ADC_CHANNEL_5 3017 * @arg @ref LL_ADC_CHANNEL_6 3018 * @arg @ref LL_ADC_CHANNEL_7 3019 * @arg @ref LL_ADC_CHANNEL_8 3020 * @arg @ref LL_ADC_CHANNEL_9 3021 * @arg @ref LL_ADC_CHANNEL_10 3022 * @arg @ref LL_ADC_CHANNEL_11 3023 * @arg @ref LL_ADC_CHANNEL_12 3024 * @arg @ref LL_ADC_CHANNEL_13 3025 * @arg @ref LL_ADC_CHANNEL_14 3026 * @arg @ref LL_ADC_CHANNEL_15 3027 * @arg @ref LL_ADC_CHANNEL_16 3028 * @arg @ref LL_ADC_CHANNEL_17 3029 * @arg @ref LL_ADC_CHANNEL_18 3030 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 3031 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 3032 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 3033 * 3034 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 3035 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 3036 * (1) For ADC channel read back from ADC register, 3037 * comparison with internal channel parameter to be done 3038 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 3039 */ LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3040 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 3041 { 3042 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; 3043 3044 return (uint32_t)(READ_BIT(ADCx->JSQR, 3045 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) 3046 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) 3047 ); 3048 } 3049 3050 /** 3051 * @brief Set ADC group injected conversion trigger: 3052 * independent or from ADC group regular. 3053 * @note This mode can be used to extend number of data registers 3054 * updated after one ADC conversion trigger and with data 3055 * permanently kept (not erased by successive conversions of scan of 3056 * ADC sequencer ranks), up to 5 data registers: 3057 * 1 data register on ADC group regular, 4 data registers 3058 * on ADC group injected. 3059 * @note If ADC group injected injected trigger source is set to an 3060 * external trigger, this feature must be must be set to 3061 * independent trigger. 3062 * ADC group injected automatic trigger is compliant only with 3063 * group injected trigger source set to SW start, without any 3064 * further action on ADC group injected conversion start or stop: 3065 * in this case, ADC group injected is controlled only 3066 * from ADC group regular. 3067 * @note It is not possible to enable both ADC group injected 3068 * auto-injected mode and sequencer discontinuous mode. 3069 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto 3070 * @param ADCx ADC instance 3071 * @param TrigAuto This parameter can be one of the following values: 3072 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 3073 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 3074 * @retval None 3075 */ LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)3076 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) 3077 { 3078 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); 3079 } 3080 3081 /** 3082 * @brief Get ADC group injected conversion trigger: 3083 * independent or from ADC group regular. 3084 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto 3085 * @param ADCx ADC instance 3086 * @retval Returned value can be one of the following values: 3087 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 3088 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 3089 */ LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)3090 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) 3091 { 3092 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); 3093 } 3094 3095 /** 3096 * @brief Set ADC group injected offset. 3097 * @note It sets: 3098 * - ADC group injected rank to which the offset programmed 3099 * will be applied 3100 * - Offset level (offset to be subtracted from the raw 3101 * converted data). 3102 * Caution: Offset format is dependent to ADC resolution: 3103 * offset has to be left-aligned on bit 11, the LSB (right bits) 3104 * are set to 0. 3105 * @note Offset cannot be enabled or disabled. 3106 * To emulate offset disabled, set an offset value equal to 0. 3107 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n 3108 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n 3109 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n 3110 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset 3111 * @param ADCx ADC instance 3112 * @param Rank This parameter can be one of the following values: 3113 * @arg @ref LL_ADC_INJ_RANK_1 3114 * @arg @ref LL_ADC_INJ_RANK_2 3115 * @arg @ref LL_ADC_INJ_RANK_3 3116 * @arg @ref LL_ADC_INJ_RANK_4 3117 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF 3118 * @retval None 3119 */ LL_ADC_INJ_SetOffset(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t OffsetLevel)3120 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) 3121 { 3122 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 3123 3124 MODIFY_REG(*preg, 3125 ADC_JOFR1_JOFFSET1, 3126 OffsetLevel); 3127 } 3128 3129 /** 3130 * @brief Get ADC group injected offset. 3131 * @note It gives offset level (offset to be subtracted from the raw converted data). 3132 * Caution: Offset format is dependent to ADC resolution: 3133 * offset has to be left-aligned on bit 11, the LSB (right bits) 3134 * are set to 0. 3135 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n 3136 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n 3137 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n 3138 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset 3139 * @param ADCx ADC instance 3140 * @param Rank This parameter can be one of the following values: 3141 * @arg @ref LL_ADC_INJ_RANK_1 3142 * @arg @ref LL_ADC_INJ_RANK_2 3143 * @arg @ref LL_ADC_INJ_RANK_3 3144 * @arg @ref LL_ADC_INJ_RANK_4 3145 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 3146 */ LL_ADC_INJ_GetOffset(ADC_TypeDef * ADCx,uint32_t Rank)3147 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) 3148 { 3149 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 3150 3151 return (uint32_t)(READ_BIT(*preg, 3152 ADC_JOFR1_JOFFSET1) 3153 ); 3154 } 3155 3156 /** 3157 * @} 3158 */ 3159 3160 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels 3161 * @{ 3162 */ 3163 3164 /** 3165 * @brief Set sampling time of the selected ADC channel 3166 * Unit: ADC clock cycles. 3167 * @note On this device, sampling time is on channel scope: independently 3168 * of channel mapped on ADC group regular or injected. 3169 * @note In case of internal channel (VrefInt, TempSensor, ...) to be 3170 * converted: 3171 * sampling time constraints must be respected (sampling time can be 3172 * adjusted in function of ADC clock frequency and sampling time 3173 * setting). 3174 * Refer to device datasheet for timings values (parameters TS_vrefint, 3175 * TS_temp, ...). 3176 * @note Conversion time is the addition of sampling time and processing time. 3177 * Refer to reference manual for ADC processing time of 3178 * this STM32 serie. 3179 * @note In case of ADC conversion of internal channel (VrefInt, 3180 * temperature sensor, ...), a sampling time minimum value 3181 * is required. 3182 * Refer to device datasheet. 3183 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n 3184 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n 3185 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n 3186 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n 3187 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n 3188 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n 3189 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n 3190 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n 3191 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n 3192 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n 3193 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n 3194 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n 3195 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n 3196 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n 3197 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n 3198 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n 3199 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n 3200 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n 3201 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime 3202 * @param ADCx ADC instance 3203 * @param Channel This parameter can be one of the following values: 3204 * @arg @ref LL_ADC_CHANNEL_0 3205 * @arg @ref LL_ADC_CHANNEL_1 3206 * @arg @ref LL_ADC_CHANNEL_2 3207 * @arg @ref LL_ADC_CHANNEL_3 3208 * @arg @ref LL_ADC_CHANNEL_4 3209 * @arg @ref LL_ADC_CHANNEL_5 3210 * @arg @ref LL_ADC_CHANNEL_6 3211 * @arg @ref LL_ADC_CHANNEL_7 3212 * @arg @ref LL_ADC_CHANNEL_8 3213 * @arg @ref LL_ADC_CHANNEL_9 3214 * @arg @ref LL_ADC_CHANNEL_10 3215 * @arg @ref LL_ADC_CHANNEL_11 3216 * @arg @ref LL_ADC_CHANNEL_12 3217 * @arg @ref LL_ADC_CHANNEL_13 3218 * @arg @ref LL_ADC_CHANNEL_14 3219 * @arg @ref LL_ADC_CHANNEL_15 3220 * @arg @ref LL_ADC_CHANNEL_16 3221 * @arg @ref LL_ADC_CHANNEL_17 3222 * @arg @ref LL_ADC_CHANNEL_18 3223 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 3224 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 3225 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 3226 * 3227 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 3228 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 3229 * @param SamplingTime This parameter can be one of the following values: 3230 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES 3231 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES 3232 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES 3233 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES 3234 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES 3235 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES 3236 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES 3237 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES 3238 * @retval None 3239 */ LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)3240 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) 3241 { 3242 /* Set bits with content of parameter "SamplingTime" with bits position */ 3243 /* in register and register position depending on parameter "Channel". */ 3244 /* Parameter "Channel" is used with masks because containing */ 3245 /* other bits reserved for other purpose. */ 3246 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 3247 3248 MODIFY_REG(*preg, 3249 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), 3250 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); 3251 } 3252 3253 /** 3254 * @brief Get sampling time of the selected ADC channel 3255 * Unit: ADC clock cycles. 3256 * @note On this device, sampling time is on channel scope: independently 3257 * of channel mapped on ADC group regular or injected. 3258 * @note Conversion time is the addition of sampling time and processing time. 3259 * Refer to reference manual for ADC processing time of 3260 * this STM32 serie. 3261 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n 3262 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n 3263 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n 3264 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n 3265 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n 3266 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n 3267 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n 3268 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n 3269 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n 3270 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n 3271 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n 3272 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n 3273 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n 3274 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n 3275 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n 3276 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n 3277 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n 3278 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n 3279 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime 3280 * @param ADCx ADC instance 3281 * @param Channel This parameter can be one of the following values: 3282 * @arg @ref LL_ADC_CHANNEL_0 3283 * @arg @ref LL_ADC_CHANNEL_1 3284 * @arg @ref LL_ADC_CHANNEL_2 3285 * @arg @ref LL_ADC_CHANNEL_3 3286 * @arg @ref LL_ADC_CHANNEL_4 3287 * @arg @ref LL_ADC_CHANNEL_5 3288 * @arg @ref LL_ADC_CHANNEL_6 3289 * @arg @ref LL_ADC_CHANNEL_7 3290 * @arg @ref LL_ADC_CHANNEL_8 3291 * @arg @ref LL_ADC_CHANNEL_9 3292 * @arg @ref LL_ADC_CHANNEL_10 3293 * @arg @ref LL_ADC_CHANNEL_11 3294 * @arg @ref LL_ADC_CHANNEL_12 3295 * @arg @ref LL_ADC_CHANNEL_13 3296 * @arg @ref LL_ADC_CHANNEL_14 3297 * @arg @ref LL_ADC_CHANNEL_15 3298 * @arg @ref LL_ADC_CHANNEL_16 3299 * @arg @ref LL_ADC_CHANNEL_17 3300 * @arg @ref LL_ADC_CHANNEL_18 3301 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 3302 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 3303 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 3304 * 3305 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 3306 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 3307 * @retval Returned value can be one of the following values: 3308 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES 3309 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES 3310 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES 3311 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES 3312 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES 3313 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES 3314 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES 3315 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES 3316 */ LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)3317 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) 3318 { 3319 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 3320 3321 return (uint32_t)(READ_BIT(*preg, 3322 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) 3323 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) 3324 ); 3325 } 3326 3327 /** 3328 * @} 3329 */ 3330 3331 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog 3332 * @{ 3333 */ 3334 3335 /** 3336 * @brief Set ADC analog watchdog monitored channels: 3337 * a single channel or all channels, 3338 * on ADC groups regular and-or injected. 3339 * @note Once monitored channels are selected, analog watchdog 3340 * is enabled. 3341 * @note In case of need to define a single channel to monitor 3342 * with analog watchdog from sequencer channel definition, 3343 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). 3344 * @note On this STM32 serie, there is only 1 kind of analog watchdog 3345 * instance: 3346 * - AWD standard (instance AWD1): 3347 * - channels monitored: can monitor 1 channel or all channels. 3348 * - groups monitored: ADC groups regular and-or injected. 3349 * - resolution: resolution is not limited (corresponds to 3350 * ADC resolution configured). 3351 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n 3352 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n 3353 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels 3354 * @param ADCx ADC instance 3355 * @param AWDChannelGroup This parameter can be one of the following values: 3356 * @arg @ref LL_ADC_AWD_DISABLE 3357 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 3358 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 3359 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 3360 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 3361 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 3362 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 3363 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 3364 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 3365 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 3366 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 3367 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 3368 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 3369 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 3370 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 3371 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 3372 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 3373 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 3374 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 3375 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 3376 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 3377 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 3378 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 3379 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 3380 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 3381 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 3382 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 3383 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 3384 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 3385 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 3386 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 3387 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 3388 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 3389 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 3390 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 3391 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 3392 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 3393 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 3394 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 3395 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 3396 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 3397 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 3398 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 3399 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 3400 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 3401 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 3402 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 3403 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 3404 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 3405 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 3406 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 3407 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 3408 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 3409 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 3410 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 3411 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 3412 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 3413 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 3414 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 3415 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 3416 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 3417 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 3418 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 3419 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 3420 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) 3421 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) 3422 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) 3423 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) 3424 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) 3425 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) 3426 * 3427 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 3428 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 3429 * @retval None 3430 */ LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)3431 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) 3432 { 3433 MODIFY_REG(ADCx->CR1, 3434 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), 3435 AWDChannelGroup); 3436 } 3437 3438 /** 3439 * @brief Get ADC analog watchdog monitored channel. 3440 * @note Usage of the returned channel number: 3441 * - To reinject this channel into another function LL_ADC_xxx: 3442 * the returned channel number is only partly formatted on definition 3443 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 3444 * with parts of literals LL_ADC_CHANNEL_x or using 3445 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 3446 * Then the selected literal LL_ADC_CHANNEL_x can be used 3447 * as parameter for another function. 3448 * - To get the channel number in decimal format: 3449 * process the returned value with the helper macro 3450 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 3451 * Applicable only when the analog watchdog is set to monitor 3452 * one channel. 3453 * @note On this STM32 serie, there is only 1 kind of analog watchdog 3454 * instance: 3455 * - AWD standard (instance AWD1): 3456 * - channels monitored: can monitor 1 channel or all channels. 3457 * - groups monitored: ADC groups regular and-or injected. 3458 * - resolution: resolution is not limited (corresponds to 3459 * ADC resolution configured). 3460 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n 3461 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n 3462 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels 3463 * @param ADCx ADC instance 3464 * @retval Returned value can be one of the following values: 3465 * @arg @ref LL_ADC_AWD_DISABLE 3466 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 3467 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 3468 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 3469 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 3470 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 3471 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 3472 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 3473 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 3474 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 3475 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 3476 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 3477 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 3478 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 3479 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 3480 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 3481 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 3482 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 3483 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 3484 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 3485 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 3486 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 3487 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 3488 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 3489 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 3490 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 3491 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 3492 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 3493 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 3494 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 3495 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 3496 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 3497 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 3498 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 3499 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 3500 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 3501 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 3502 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 3503 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 3504 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 3505 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 3506 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 3507 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 3508 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 3509 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 3510 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 3511 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 3512 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 3513 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 3514 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 3515 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 3516 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 3517 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 3518 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 3519 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 3520 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 3521 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 3522 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 3523 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 3524 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 3525 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 3526 */ LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx)3527 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) 3528 { 3529 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); 3530 } 3531 3532 /** 3533 * @brief Set ADC analog watchdog threshold value of threshold 3534 * high or low. 3535 * @note In case of ADC resolution different of 12 bits, 3536 * analog watchdog thresholds data require a specific shift. 3537 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). 3538 * @note On this STM32 serie, there is only 1 kind of analog watchdog 3539 * instance: 3540 * - AWD standard (instance AWD1): 3541 * - channels monitored: can monitor 1 channel or all channels. 3542 * - groups monitored: ADC groups regular and-or injected. 3543 * - resolution: resolution is not limited (corresponds to 3544 * ADC resolution configured). 3545 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n 3546 * LTR LT LL_ADC_SetAnalogWDThresholds 3547 * @param ADCx ADC instance 3548 * @param AWDThresholdsHighLow This parameter can be one of the following values: 3549 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 3550 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 3551 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF 3552 * @retval None 3553 */ LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3554 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) 3555 { 3556 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 3557 3558 MODIFY_REG(*preg, 3559 ADC_HTR_HT, 3560 AWDThresholdValue); 3561 } 3562 3563 /** 3564 * @brief Get ADC analog watchdog threshold value of threshold high or 3565 * threshold low. 3566 * @note In case of ADC resolution different of 12 bits, 3567 * analog watchdog thresholds data require a specific shift. 3568 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). 3569 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n 3570 * LTR LT LL_ADC_GetAnalogWDThresholds 3571 * @param ADCx ADC instance 3572 * @param AWDThresholdsHighLow This parameter can be one of the following values: 3573 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 3574 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 3575 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 3576 */ LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)3577 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) 3578 { 3579 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 3580 3581 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); 3582 } 3583 3584 /** 3585 * @} 3586 */ 3587 3588 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode 3589 * @{ 3590 */ 3591 3592 #if defined(ADC_MULTIMODE_SUPPORT) 3593 /** 3594 * @brief Set ADC multimode configuration to operate in independent mode 3595 * or multimode (for devices with several ADC instances). 3596 * @note If multimode configuration: the selected ADC instance is 3597 * either master or slave depending on hardware. 3598 * Refer to reference manual. 3599 * @rmtoll CCR MULTI LL_ADC_SetMultimode 3600 * @param ADCxy_COMMON ADC common instance 3601 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3602 * @param Multimode This parameter can be one of the following values: 3603 * @arg @ref LL_ADC_MULTI_INDEPENDENT 3604 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 3605 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 3606 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 3607 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 3608 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 3609 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 3610 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 3611 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM 3612 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT 3613 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT 3614 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT 3615 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL 3616 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN 3617 * @retval None 3618 */ LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)3619 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) 3620 { 3621 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode); 3622 } 3623 3624 /** 3625 * @brief Get ADC multimode configuration to operate in independent mode 3626 * or multimode (for devices with several ADC instances). 3627 * @note If multimode configuration: the selected ADC instance is 3628 * either master or slave depending on hardware. 3629 * Refer to reference manual. 3630 * @rmtoll CCR MULTI LL_ADC_GetMultimode 3631 * @param ADCxy_COMMON ADC common instance 3632 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3633 * @retval Returned value can be one of the following values: 3634 * @arg @ref LL_ADC_MULTI_INDEPENDENT 3635 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 3636 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 3637 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 3638 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 3639 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 3640 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 3641 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 3642 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM 3643 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT 3644 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT 3645 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT 3646 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL 3647 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN 3648 */ LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)3649 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) 3650 { 3651 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI)); 3652 } 3653 3654 /** 3655 * @brief Set ADC multimode conversion data transfer: no transfer 3656 * or transfer by DMA. 3657 * @note If ADC multimode transfer by DMA is not selected: 3658 * each ADC uses its own DMA channel, with its individual 3659 * DMA transfer settings. 3660 * If ADC multimode transfer by DMA is selected: 3661 * One DMA channel is used for both ADC (DMA of ADC master) 3662 * Specifies the DMA requests mode: 3663 * - Limited mode (One shot mode): DMA transfer requests are stopped 3664 * when number of DMA data transfers (number of 3665 * ADC conversions) is reached. 3666 * This ADC mode is intended to be used with DMA mode non-circular. 3667 * - Unlimited mode: DMA transfer requests are unlimited, 3668 * whatever number of DMA data transfers (number of 3669 * ADC conversions). 3670 * This ADC mode is intended to be used with DMA mode circular. 3671 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 3672 * mode non-circular: 3673 * when DMA transfers size will be reached, DMA will stop transfers of 3674 * ADC conversions data ADC will raise an overrun error 3675 * (overrun flag and interruption if enabled). 3676 * @note How to retrieve multimode conversion data: 3677 * Whatever multimode transfer by DMA setting: using function 3678 * @ref LL_ADC_REG_ReadMultiConversionData32(). 3679 * If ADC multimode transfer by DMA is selected: conversion data 3680 * is a raw data with ADC master and slave concatenated. 3681 * A macro is available to get the conversion data of 3682 * ADC master or ADC slave: see helper macro 3683 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 3684 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n 3685 * CCR DDS LL_ADC_SetMultiDMATransfer 3686 * @param ADCxy_COMMON ADC common instance 3687 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3688 * @param MultiDMATransfer This parameter can be one of the following values: 3689 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 3690 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 3691 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 3692 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 3693 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 3694 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 3695 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 3696 * @retval None 3697 */ LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)3698 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) 3699 { 3700 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer); 3701 } 3702 3703 /** 3704 * @brief Get ADC multimode conversion data transfer: no transfer 3705 * or transfer by DMA. 3706 * @note If ADC multimode transfer by DMA is not selected: 3707 * each ADC uses its own DMA channel, with its individual 3708 * DMA transfer settings. 3709 * If ADC multimode transfer by DMA is selected: 3710 * One DMA channel is used for both ADC (DMA of ADC master) 3711 * Specifies the DMA requests mode: 3712 * - Limited mode (One shot mode): DMA transfer requests are stopped 3713 * when number of DMA data transfers (number of 3714 * ADC conversions) is reached. 3715 * This ADC mode is intended to be used with DMA mode non-circular. 3716 * - Unlimited mode: DMA transfer requests are unlimited, 3717 * whatever number of DMA data transfers (number of 3718 * ADC conversions). 3719 * This ADC mode is intended to be used with DMA mode circular. 3720 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 3721 * mode non-circular: 3722 * when DMA transfers size will be reached, DMA will stop transfers of 3723 * ADC conversions data ADC will raise an overrun error 3724 * (overrun flag and interruption if enabled). 3725 * @note How to retrieve multimode conversion data: 3726 * Whatever multimode transfer by DMA setting: using function 3727 * @ref LL_ADC_REG_ReadMultiConversionData32(). 3728 * If ADC multimode transfer by DMA is selected: conversion data 3729 * is a raw data with ADC master and slave concatenated. 3730 * A macro is available to get the conversion data of 3731 * ADC master or ADC slave: see helper macro 3732 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 3733 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n 3734 * CCR DDS LL_ADC_GetMultiDMATransfer 3735 * @param ADCxy_COMMON ADC common instance 3736 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3737 * @retval Returned value can be one of the following values: 3738 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 3739 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 3740 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 3741 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 3742 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 3743 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 3744 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 3745 */ LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)3746 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) 3747 { 3748 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS)); 3749 } 3750 3751 /** 3752 * @brief Set ADC multimode delay between 2 sampling phases. 3753 * @note The sampling delay range depends on ADC resolution: 3754 * - ADC resolution 12 bits can have maximum delay of 12 cycles. 3755 * - ADC resolution 10 bits can have maximum delay of 10 cycles. 3756 * - ADC resolution 8 bits can have maximum delay of 8 cycles. 3757 * - ADC resolution 6 bits can have maximum delay of 6 cycles. 3758 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay 3759 * @param ADCxy_COMMON ADC common instance 3760 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3761 * @param MultiTwoSamplingDelay This parameter can be one of the following values: 3762 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 3763 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES 3764 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES 3765 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES 3766 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES 3767 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES 3768 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES 3769 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES 3770 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES 3771 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES 3772 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES 3773 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES 3774 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES 3775 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES 3776 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES 3777 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES 3778 * @retval None 3779 */ LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)3780 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) 3781 { 3782 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); 3783 } 3784 3785 /** 3786 * @brief Get ADC multimode delay between 2 sampling phases. 3787 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay 3788 * @param ADCxy_COMMON ADC common instance 3789 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3790 * @retval Returned value can be one of the following values: 3791 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 3792 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES 3793 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES 3794 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES 3795 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES 3796 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES 3797 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES 3798 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES 3799 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES 3800 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES 3801 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES 3802 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES 3803 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES 3804 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES 3805 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES 3806 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES 3807 */ LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)3808 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) 3809 { 3810 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); 3811 } 3812 #endif /* ADC_MULTIMODE_SUPPORT */ 3813 3814 /** 3815 * @} 3816 */ 3817 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance 3818 * @{ 3819 */ 3820 3821 /** 3822 * @brief Enable the selected ADC instance. 3823 * @note On this STM32 serie, after ADC enable, a delay for 3824 * ADC internal analog stabilization is required before performing a 3825 * ADC conversion start. 3826 * Refer to device datasheet, parameter tSTAB. 3827 * @rmtoll CR2 ADON LL_ADC_Enable 3828 * @param ADCx ADC instance 3829 * @retval None 3830 */ LL_ADC_Enable(ADC_TypeDef * ADCx)3831 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) 3832 { 3833 SET_BIT(ADCx->CR2, ADC_CR2_ADON); 3834 } 3835 3836 /** 3837 * @brief Disable the selected ADC instance. 3838 * @rmtoll CR2 ADON LL_ADC_Disable 3839 * @param ADCx ADC instance 3840 * @retval None 3841 */ LL_ADC_Disable(ADC_TypeDef * ADCx)3842 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) 3843 { 3844 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); 3845 } 3846 3847 /** 3848 * @brief Get the selected ADC instance enable state. 3849 * @rmtoll CR2 ADON LL_ADC_IsEnabled 3850 * @param ADCx ADC instance 3851 * @retval 0: ADC is disabled, 1: ADC is enabled. 3852 */ LL_ADC_IsEnabled(ADC_TypeDef * ADCx)3853 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) 3854 { 3855 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); 3856 } 3857 3858 /** 3859 * @} 3860 */ 3861 3862 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular 3863 * @{ 3864 */ 3865 3866 /** 3867 * @brief Start ADC group regular conversion. 3868 * @note On this STM32 serie, this function is relevant only for 3869 * internal trigger (SW start), not for external trigger: 3870 * - If ADC trigger has been set to software start, ADC conversion 3871 * starts immediately. 3872 * - If ADC trigger has been set to external trigger, ADC conversion 3873 * start must be performed using function 3874 * @ref LL_ADC_REG_StartConversionExtTrig(). 3875 * (if external trigger edge would have been set during ADC other 3876 * settings, ADC conversion would start at trigger event 3877 * as soon as ADC is enabled). 3878 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart 3879 * @param ADCx ADC instance 3880 * @retval None 3881 */ LL_ADC_REG_StartConversionSWStart(ADC_TypeDef * ADCx)3882 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) 3883 { 3884 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART); 3885 } 3886 3887 /** 3888 * @brief Start ADC group regular conversion from external trigger. 3889 * @note ADC conversion will start at next trigger event (on the selected 3890 * trigger edge) following the ADC start conversion command. 3891 * @note On this STM32 serie, this function is relevant for 3892 * ADC conversion start from external trigger. 3893 * If internal trigger (SW start) is needed, perform ADC conversion 3894 * start using function @ref LL_ADC_REG_StartConversionSWStart(). 3895 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig 3896 * @param ExternalTriggerEdge This parameter can be one of the following values: 3897 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 3898 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 3899 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 3900 * @param ADCx ADC instance 3901 * @retval None 3902 */ LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3903 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 3904 { 3905 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 3906 } 3907 3908 /** 3909 * @brief Stop ADC group regular conversion from external trigger. 3910 * @note No more ADC conversion will start at next trigger event 3911 * following the ADC stop conversion command. 3912 * If a conversion is on-going, it will be completed. 3913 * @note On this STM32 serie, there is no specific command 3914 * to stop a conversion on-going or to stop ADC converting 3915 * in continuous mode. These actions can be performed 3916 * using function @ref LL_ADC_Disable(). 3917 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig 3918 * @param ADCx ADC instance 3919 * @retval None 3920 */ LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef * ADCx)3921 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) 3922 { 3923 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN); 3924 } 3925 3926 /** 3927 * @brief Get ADC group regular conversion data, range fit for 3928 * all ADC configurations: all ADC resolutions and 3929 * all oversampling increased data width (for devices 3930 * with feature oversampling). 3931 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 3932 * @param ADCx ADC instance 3933 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 3934 */ LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)3935 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) 3936 { 3937 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 3938 } 3939 3940 /** 3941 * @brief Get ADC group regular conversion data, range fit for 3942 * ADC resolution 12 bits. 3943 * @note For devices with feature oversampling: Oversampling 3944 * can increase data width, function for extended range 3945 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 3946 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 3947 * @param ADCx ADC instance 3948 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 3949 */ LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)3950 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) 3951 { 3952 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 3953 } 3954 3955 /** 3956 * @brief Get ADC group regular conversion data, range fit for 3957 * ADC resolution 10 bits. 3958 * @note For devices with feature oversampling: Oversampling 3959 * can increase data width, function for extended range 3960 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 3961 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 3962 * @param ADCx ADC instance 3963 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 3964 */ LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)3965 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) 3966 { 3967 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 3968 } 3969 3970 /** 3971 * @brief Get ADC group regular conversion data, range fit for 3972 * ADC resolution 8 bits. 3973 * @note For devices with feature oversampling: Oversampling 3974 * can increase data width, function for extended range 3975 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 3976 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 3977 * @param ADCx ADC instance 3978 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 3979 */ LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)3980 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) 3981 { 3982 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 3983 } 3984 3985 /** 3986 * @brief Get ADC group regular conversion data, range fit for 3987 * ADC resolution 6 bits. 3988 * @note For devices with feature oversampling: Oversampling 3989 * can increase data width, function for extended range 3990 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 3991 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 3992 * @param ADCx ADC instance 3993 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 3994 */ LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)3995 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) 3996 { 3997 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 3998 } 3999 4000 #if defined(ADC_MULTIMODE_SUPPORT) 4001 /** 4002 * @brief Get ADC multimode conversion data of ADC master, ADC slave 4003 * or raw data with ADC master and slave concatenated. 4004 * @note If raw data with ADC master and slave concatenated is retrieved, 4005 * a macro is available to get the conversion data of 4006 * ADC master or ADC slave: see helper macro 4007 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 4008 * (however this macro is mainly intended for multimode 4009 * transfer by DMA, because this function can do the same 4010 * by getting multimode conversion data of ADC master or ADC slave 4011 * separately). 4012 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n 4013 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32 4014 * @param ADCxy_COMMON ADC common instance 4015 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4016 * @param ConversionData This parameter can be one of the following values: 4017 * @arg @ref LL_ADC_MULTI_MASTER 4018 * @arg @ref LL_ADC_MULTI_SLAVE 4019 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE 4020 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 4021 */ LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)4022 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) 4023 { 4024 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, 4025 ADC_DR_ADC2DATA) 4026 >> POSITION_VAL(ConversionData) 4027 ); 4028 } 4029 #endif /* ADC_MULTIMODE_SUPPORT */ 4030 4031 /** 4032 * @} 4033 */ 4034 4035 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected 4036 * @{ 4037 */ 4038 4039 /** 4040 * @brief Start ADC group injected conversion. 4041 * @note On this STM32 serie, this function is relevant only for 4042 * internal trigger (SW start), not for external trigger: 4043 * - If ADC trigger has been set to software start, ADC conversion 4044 * starts immediately. 4045 * - If ADC trigger has been set to external trigger, ADC conversion 4046 * start must be performed using function 4047 * @ref LL_ADC_INJ_StartConversionExtTrig(). 4048 * (if external trigger edge would have been set during ADC other 4049 * settings, ADC conversion would start at trigger event 4050 * as soon as ADC is enabled). 4051 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart 4052 * @param ADCx ADC instance 4053 * @retval None 4054 */ LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef * ADCx)4055 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) 4056 { 4057 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART); 4058 } 4059 4060 /** 4061 * @brief Start ADC group injected conversion from external trigger. 4062 * @note ADC conversion will start at next trigger event (on the selected 4063 * trigger edge) following the ADC start conversion command. 4064 * @note On this STM32 serie, this function is relevant for 4065 * ADC conversion start from external trigger. 4066 * If internal trigger (SW start) is needed, perform ADC conversion 4067 * start using function @ref LL_ADC_INJ_StartConversionSWStart(). 4068 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig 4069 * @param ExternalTriggerEdge This parameter can be one of the following values: 4070 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 4071 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 4072 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 4073 * @param ADCx ADC instance 4074 * @retval None 4075 */ LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4076 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 4077 { 4078 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 4079 } 4080 4081 /** 4082 * @brief Stop ADC group injected conversion from external trigger. 4083 * @note No more ADC conversion will start at next trigger event 4084 * following the ADC stop conversion command. 4085 * If a conversion is on-going, it will be completed. 4086 * @note On this STM32 serie, there is no specific command 4087 * to stop a conversion on-going or to stop ADC converting 4088 * in continuous mode. These actions can be performed 4089 * using function @ref LL_ADC_Disable(). 4090 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig 4091 * @param ADCx ADC instance 4092 * @retval None 4093 */ LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef * ADCx)4094 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) 4095 { 4096 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN); 4097 } 4098 4099 /** 4100 * @brief Get ADC group regular conversion data, range fit for 4101 * all ADC configurations: all ADC resolutions and 4102 * all oversampling increased data width (for devices 4103 * with feature oversampling). 4104 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n 4105 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n 4106 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n 4107 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 4108 * @param ADCx ADC instance 4109 * @param Rank This parameter can be one of the following values: 4110 * @arg @ref LL_ADC_INJ_RANK_1 4111 * @arg @ref LL_ADC_INJ_RANK_2 4112 * @arg @ref LL_ADC_INJ_RANK_3 4113 * @arg @ref LL_ADC_INJ_RANK_4 4114 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 4115 */ LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)4116 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) 4117 { 4118 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 4119 4120 return (uint32_t)(READ_BIT(*preg, 4121 ADC_JDR1_JDATA) 4122 ); 4123 } 4124 4125 /** 4126 * @brief Get ADC group injected conversion data, range fit for 4127 * ADC resolution 12 bits. 4128 * @note For devices with feature oversampling: Oversampling 4129 * can increase data width, function for extended range 4130 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 4131 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n 4132 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n 4133 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n 4134 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 4135 * @param ADCx ADC instance 4136 * @param Rank This parameter can be one of the following values: 4137 * @arg @ref LL_ADC_INJ_RANK_1 4138 * @arg @ref LL_ADC_INJ_RANK_2 4139 * @arg @ref LL_ADC_INJ_RANK_3 4140 * @arg @ref LL_ADC_INJ_RANK_4 4141 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 4142 */ LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)4143 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) 4144 { 4145 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 4146 4147 return (uint16_t)(READ_BIT(*preg, 4148 ADC_JDR1_JDATA) 4149 ); 4150 } 4151 4152 /** 4153 * @brief Get ADC group injected conversion data, range fit for 4154 * ADC resolution 10 bits. 4155 * @note For devices with feature oversampling: Oversampling 4156 * can increase data width, function for extended range 4157 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 4158 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n 4159 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n 4160 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n 4161 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 4162 * @param ADCx ADC instance 4163 * @param Rank This parameter can be one of the following values: 4164 * @arg @ref LL_ADC_INJ_RANK_1 4165 * @arg @ref LL_ADC_INJ_RANK_2 4166 * @arg @ref LL_ADC_INJ_RANK_3 4167 * @arg @ref LL_ADC_INJ_RANK_4 4168 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 4169 */ LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)4170 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) 4171 { 4172 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 4173 4174 return (uint16_t)(READ_BIT(*preg, 4175 ADC_JDR1_JDATA) 4176 ); 4177 } 4178 4179 /** 4180 * @brief Get ADC group injected conversion data, range fit for 4181 * ADC resolution 8 bits. 4182 * @note For devices with feature oversampling: Oversampling 4183 * can increase data width, function for extended range 4184 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 4185 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n 4186 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n 4187 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n 4188 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 4189 * @param ADCx ADC instance 4190 * @param Rank This parameter can be one of the following values: 4191 * @arg @ref LL_ADC_INJ_RANK_1 4192 * @arg @ref LL_ADC_INJ_RANK_2 4193 * @arg @ref LL_ADC_INJ_RANK_3 4194 * @arg @ref LL_ADC_INJ_RANK_4 4195 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 4196 */ LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)4197 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) 4198 { 4199 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 4200 4201 return (uint8_t)(READ_BIT(*preg, 4202 ADC_JDR1_JDATA) 4203 ); 4204 } 4205 4206 /** 4207 * @brief Get ADC group injected conversion data, range fit for 4208 * ADC resolution 6 bits. 4209 * @note For devices with feature oversampling: Oversampling 4210 * can increase data width, function for extended range 4211 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 4212 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n 4213 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n 4214 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n 4215 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 4216 * @param ADCx ADC instance 4217 * @param Rank This parameter can be one of the following values: 4218 * @arg @ref LL_ADC_INJ_RANK_1 4219 * @arg @ref LL_ADC_INJ_RANK_2 4220 * @arg @ref LL_ADC_INJ_RANK_3 4221 * @arg @ref LL_ADC_INJ_RANK_4 4222 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 4223 */ LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)4224 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) 4225 { 4226 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 4227 4228 return (uint8_t)(READ_BIT(*preg, 4229 ADC_JDR1_JDATA) 4230 ); 4231 } 4232 4233 /** 4234 * @} 4235 */ 4236 4237 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management 4238 * @{ 4239 */ 4240 4241 /** 4242 * @brief Get flag ADC group regular end of unitary conversion 4243 * or end of sequence conversions, depending on 4244 * ADC configuration. 4245 * @note To configure flag of end of conversion, 4246 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 4247 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS 4248 * @param ADCx ADC instance 4249 * @retval State of bit (1 or 0). 4250 */ LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef * ADCx)4251 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx) 4252 { 4253 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); 4254 } 4255 4256 /** 4257 * @brief Get flag ADC group regular overrun. 4258 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR 4259 * @param ADCx ADC instance 4260 * @retval State of bit (1 or 0). 4261 */ LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)4262 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) 4263 { 4264 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); 4265 } 4266 4267 4268 /** 4269 * @brief Get flag ADC group injected end of sequence conversions. 4270 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS 4271 * @param ADCx ADC instance 4272 * @retval State of bit (1 or 0). 4273 */ LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)4274 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) 4275 { 4276 /* Note: on this STM32 serie, there is no flag ADC group injected */ 4277 /* end of unitary conversion. */ 4278 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 4279 /* in other STM32 families). */ 4280 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); 4281 } 4282 4283 /** 4284 * @brief Get flag ADC analog watchdog 1 flag 4285 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 4286 * @param ADCx ADC instance 4287 * @retval State of bit (1 or 0). 4288 */ LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)4289 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) 4290 { 4291 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 4292 } 4293 4294 /** 4295 * @brief Clear flag ADC group regular end of unitary conversion 4296 * or end of sequence conversions, depending on 4297 * ADC configuration. 4298 * @note To configure flag of end of conversion, 4299 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 4300 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS 4301 * @param ADCx ADC instance 4302 * @retval None 4303 */ LL_ADC_ClearFlag_EOCS(ADC_TypeDef * ADCx)4304 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx) 4305 { 4306 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS); 4307 } 4308 4309 /** 4310 * @brief Clear flag ADC group regular overrun. 4311 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR 4312 * @param ADCx ADC instance 4313 * @retval None 4314 */ LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4315 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) 4316 { 4317 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR); 4318 } 4319 4320 4321 /** 4322 * @brief Clear flag ADC group injected end of sequence conversions. 4323 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS 4324 * @param ADCx ADC instance 4325 * @retval None 4326 */ LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)4327 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) 4328 { 4329 /* Note: on this STM32 serie, there is no flag ADC group injected */ 4330 /* end of unitary conversion. */ 4331 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 4332 /* in other STM32 families). */ 4333 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); 4334 } 4335 4336 /** 4337 * @brief Clear flag ADC analog watchdog 1. 4338 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 4339 * @param ADCx ADC instance 4340 * @retval None 4341 */ LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4342 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) 4343 { 4344 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); 4345 } 4346 4347 #if defined(ADC_MULTIMODE_SUPPORT) 4348 /** 4349 * @brief Get flag multimode ADC group regular end of unitary conversion 4350 * or end of sequence conversions, depending on 4351 * ADC configuration, of the ADC master. 4352 * @note To configure flag of end of conversion, 4353 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 4354 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS 4355 * @param ADCxy_COMMON ADC common instance 4356 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4357 * @retval State of bit (1 or 0). 4358 */ LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4359 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 4360 { 4361 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); 4362 } 4363 4364 /** 4365 * @brief Get flag multimode ADC group regular end of unitary conversion 4366 * or end of sequence conversions, depending on 4367 * ADC configuration, of the ADC slave 1. 4368 * @note To configure flag of end of conversion, 4369 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 4370 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS 4371 * @param ADCxy_COMMON ADC common instance 4372 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4373 * @retval State of bit (1 or 0). 4374 */ LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4375 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 4376 { 4377 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1)); 4378 } 4379 4380 /** 4381 * @brief Get flag multimode ADC group regular end of unitary conversion 4382 * or end of sequence conversions, depending on 4383 * ADC configuration, of the ADC slave 2. 4384 * @note To configure flag of end of conversion, 4385 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 4386 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS 4387 * @param ADCxy_COMMON ADC common instance 4388 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4389 * @retval State of bit (1 or 0). 4390 */ LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4391 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 4392 { 4393 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2)); 4394 } 4395 /** 4396 * @brief Get flag multimode ADC group regular overrun of the ADC master. 4397 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR 4398 * @param ADCxy_COMMON ADC common instance 4399 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4400 * @retval State of bit (1 or 0). 4401 */ LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4402 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 4403 { 4404 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); 4405 } 4406 4407 /** 4408 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1. 4409 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR 4410 * @param ADCxy_COMMON ADC common instance 4411 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4412 * @retval State of bit (1 or 0). 4413 */ LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4414 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 4415 { 4416 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1)); 4417 } 4418 4419 /** 4420 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2. 4421 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR 4422 * @param ADCxy_COMMON ADC common instance 4423 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4424 * @retval State of bit (1 or 0). 4425 */ LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4426 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 4427 { 4428 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2)); 4429 } 4430 4431 4432 /** 4433 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. 4434 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS 4435 * @param ADCxy_COMMON ADC common instance 4436 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4437 * @retval State of bit (1 or 0). 4438 */ LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4439 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 4440 { 4441 /* Note: on this STM32 serie, there is no flag ADC group injected */ 4442 /* end of unitary conversion. */ 4443 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 4444 /* in other STM32 families). */ 4445 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1)); 4446 } 4447 4448 /** 4449 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1. 4450 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS 4451 * @param ADCxy_COMMON ADC common instance 4452 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4453 * @retval State of bit (1 or 0). 4454 */ LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4455 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 4456 { 4457 /* Note: on this STM32 serie, there is no flag ADC group injected */ 4458 /* end of unitary conversion. */ 4459 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 4460 /* in other STM32 families). */ 4461 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2)); 4462 } 4463 4464 /** 4465 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2. 4466 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS 4467 * @param ADCxy_COMMON ADC common instance 4468 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4469 * @retval State of bit (1 or 0). 4470 */ LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4471 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 4472 { 4473 /* Note: on this STM32 serie, there is no flag ADC group injected */ 4474 /* end of unitary conversion. */ 4475 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 4476 /* in other STM32 families). */ 4477 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3)); 4478 } 4479 4480 /** 4481 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. 4482 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1 4483 * @param ADCxy_COMMON ADC common instance 4484 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4485 * @retval State of bit (1 or 0). 4486 */ LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4487 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 4488 { 4489 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); 4490 } 4491 4492 /** 4493 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1. 4494 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1 4495 * @param ADCxy_COMMON ADC common instance 4496 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4497 * @retval State of bit (1 or 0). 4498 */ LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4499 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 4500 { 4501 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1)); 4502 } 4503 4504 /** 4505 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2. 4506 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1 4507 * @param ADCxy_COMMON ADC common instance 4508 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 4509 * @retval State of bit (1 or 0). 4510 */ LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4511 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 4512 { 4513 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); 4514 } 4515 4516 #endif /* ADC_MULTIMODE_SUPPORT */ 4517 4518 /** 4519 * @} 4520 */ 4521 4522 /** @defgroup ADC_LL_EF_IT_Management ADC IT management 4523 * @{ 4524 */ 4525 4526 /** 4527 * @brief Enable interruption ADC group regular end of unitary conversion 4528 * or end of sequence conversions, depending on 4529 * ADC configuration. 4530 * @note To configure flag of end of conversion, 4531 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 4532 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS 4533 * @param ADCx ADC instance 4534 * @retval None 4535 */ LL_ADC_EnableIT_EOCS(ADC_TypeDef * ADCx)4536 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx) 4537 { 4538 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS); 4539 } 4540 4541 /** 4542 * @brief Enable ADC group regular interruption overrun. 4543 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR 4544 * @param ADCx ADC instance 4545 * @retval None 4546 */ LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4547 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) 4548 { 4549 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR); 4550 } 4551 4552 4553 /** 4554 * @brief Enable interruption ADC group injected end of sequence conversions. 4555 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 4556 * @param ADCx ADC instance 4557 * @retval None 4558 */ LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)4559 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) 4560 { 4561 /* Note: on this STM32 serie, there is no flag ADC group injected */ 4562 /* end of unitary conversion. */ 4563 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 4564 /* in other STM32 families). */ 4565 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 4566 } 4567 4568 /** 4569 * @brief Enable interruption ADC analog watchdog 1. 4570 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 4571 * @param ADCx ADC instance 4572 * @retval None 4573 */ LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4574 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) 4575 { 4576 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 4577 } 4578 4579 /** 4580 * @brief Disable interruption ADC group regular end of unitary conversion 4581 * or end of sequence conversions, depending on 4582 * ADC configuration. 4583 * @note To configure flag of end of conversion, 4584 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 4585 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS 4586 * @param ADCx ADC instance 4587 * @retval None 4588 */ LL_ADC_DisableIT_EOCS(ADC_TypeDef * ADCx)4589 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx) 4590 { 4591 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS); 4592 } 4593 4594 /** 4595 * @brief Disable interruption ADC group regular overrun. 4596 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR 4597 * @param ADCx ADC instance 4598 * @retval None 4599 */ LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4600 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) 4601 { 4602 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR); 4603 } 4604 4605 4606 /** 4607 * @brief Disable interruption ADC group injected end of sequence conversions. 4608 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 4609 * @param ADCx ADC instance 4610 * @retval None 4611 */ LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)4612 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) 4613 { 4614 /* Note: on this STM32 serie, there is no flag ADC group injected */ 4615 /* end of unitary conversion. */ 4616 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 4617 /* in other STM32 families). */ 4618 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 4619 } 4620 4621 /** 4622 * @brief Disable interruption ADC analog watchdog 1. 4623 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 4624 * @param ADCx ADC instance 4625 * @retval None 4626 */ LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4627 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) 4628 { 4629 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 4630 } 4631 4632 /** 4633 * @brief Get state of interruption ADC group regular end of unitary conversion 4634 * or end of sequence conversions, depending on 4635 * ADC configuration. 4636 * @note To configure flag of end of conversion, 4637 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 4638 * (0: interrupt disabled, 1: interrupt enabled) 4639 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS 4640 * @param ADCx ADC instance 4641 * @retval State of bit (1 or 0). 4642 */ LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef * ADCx)4643 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx) 4644 { 4645 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS)); 4646 } 4647 4648 /** 4649 * @brief Get state of interruption ADC group regular overrun 4650 * (0: interrupt disabled, 1: interrupt enabled). 4651 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR 4652 * @param ADCx ADC instance 4653 * @retval State of bit (1 or 0). 4654 */ LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)4655 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) 4656 { 4657 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); 4658 } 4659 4660 4661 /** 4662 * @brief Get state of interruption ADC group injected end of sequence conversions 4663 * (0: interrupt disabled, 1: interrupt enabled). 4664 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 4665 * @param ADCx ADC instance 4666 * @retval State of bit (1 or 0). 4667 */ LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)4668 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) 4669 { 4670 /* Note: on this STM32 serie, there is no flag ADC group injected */ 4671 /* end of unitary conversion. */ 4672 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 4673 /* in other STM32 families). */ 4674 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); 4675 } 4676 4677 /** 4678 * @brief Get state of interruption ADC analog watchdog 1 4679 * (0: interrupt disabled, 1: interrupt enabled). 4680 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 4681 * @param ADCx ADC instance 4682 * @retval State of bit (1 or 0). 4683 */ LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)4684 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) 4685 { 4686 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); 4687 } 4688 4689 /** 4690 * @} 4691 */ 4692 4693 #if defined(USE_FULL_LL_DRIVER) 4694 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions 4695 * @{ 4696 */ 4697 4698 /* Initialization of some features of ADC common parameters and multimode */ 4699 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); 4700 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 4701 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 4702 4703 /* De-initialization of ADC instance, ADC group regular and ADC group injected */ 4704 /* (availability of ADC group injected depends on STM32 families) */ 4705 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); 4706 4707 /* Initialization of some features of ADC instance */ 4708 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); 4709 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); 4710 4711 /* Initialization of some features of ADC instance and ADC group regular */ 4712 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 4713 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 4714 4715 /* Initialization of some features of ADC instance and ADC group injected */ 4716 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 4717 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 4718 4719 /** 4720 * @} 4721 */ 4722 #endif /* USE_FULL_LL_DRIVER */ 4723 4724 /** 4725 * @} 4726 */ 4727 4728 /** 4729 * @} 4730 */ 4731 4732 #endif /* ADC1 || ADC2 || ADC3 */ 4733 4734 /** 4735 * @} 4736 */ 4737 4738 #ifdef __cplusplus 4739 } 4740 #endif 4741 4742 #endif /* __STM32F4xx_LL_ADC_H */ 4743 4744 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4745