xref: /btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h (revision a8f7f3fcbcd51f8d2e92aca076b6a9f812db358c) 
1  /**
2    ******************************************************************************
3    * @file    stm32f446xx.h
4    * @author  MCD Application Team
5    * @brief   CMSIS STM32F446xx Device Peripheral Access Layer Header File.
6    *
7    *          This file contains:
8    *           - Data structures and the address mapping for all peripherals
9    *           - peripherals registers declarations and bits definition
10    *           - Macros to access peripheral’s registers hardware
11    *
12    ******************************************************************************
13    * @attention
14    *
15    * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16    * All rights reserved.</center></h2>
17    *
18    * This software component is licensed by ST under BSD 3-Clause license,
19    * the "License"; You may not use this file except in compliance with the
20    * License. You may obtain a copy of the License at:
21    *                        opensource.org/licenses/BSD-3-Clause
22    *
23    ******************************************************************************
24    */
25  
26  /** @addtogroup CMSIS_Device
27    * @{
28    */
29  
30  /** @addtogroup stm32f446xx
31    * @{
32    */
33  
34  #ifndef __STM32F446xx_H
35  #define __STM32F446xx_H
36  
37  #ifdef __cplusplus
38   extern "C" {
39  #endif /* __cplusplus */
40  
41  /** @addtogroup Configuration_section_for_CMSIS
42    * @{
43    */
44  
45  /**
46    * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47    */
48  #define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
49  #define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
50  #define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
51  #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
52  #define __FPU_PRESENT             1U       /*!< FPU present                                   */
53  
54  /**
55    * @}
56    */
57  
58  /** @addtogroup Peripheral_interrupt_number_definition
59    * @{
60    */
61  
62  /**
63   * @brief STM32F4XX Interrupt Number Definition, according to the selected device
64   *        in @ref Library_configuration_section
65   */
66  typedef enum
67  {
68  /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69    NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
70    MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
71    BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
72    UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
73    SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
74    DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
75    PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
76    SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
77  /******  STM32 specific Interrupt Numbers **********************************************************************/
78    WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79    PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
80    TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
81    RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
82    FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
83    RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
84    EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
85    EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
86    EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
87    EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
88    EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
89    DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
90    DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
91    DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
92    DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
93    DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
94    DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
95    DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
96    ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
97    CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
98    CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
99    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
100    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
101    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
102    TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
103    TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
104    TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
105    TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
106    TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
107    TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
108    TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
109    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
110    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
111    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
112    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
113    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
114    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
115    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
116    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
117    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
118    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
119    RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
120    OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
121    TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
122    TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
123    TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
124    TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
125    DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
126    FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
127    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
128    TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
129    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
130    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
131    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
132    TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
133    TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
134    DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
135    DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
136    DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
137    DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
138    DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
139    CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
140    CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
141    CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
142    CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
143    OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
144    DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
145    DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
146    DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
147    USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
148    I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
149    I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
150    OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
151    OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
152    OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
153    OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
154    DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
155    FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
156    SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
157    SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
158    SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
159    QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */
160    CEC_IRQn                    = 93,     /*!< CEC global Interrupt                                              */
161    SPDIF_RX_IRQn               = 94,     /*!< SPDIF-RX global Interrupt                                          */
162    FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
163    FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */
164  } IRQn_Type;
165  
166  /**
167    * @}
168    */
169  
170  #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
171  #include "system_stm32f4xx.h"
172  #include <stdint.h>
173  
174  /** @addtogroup Peripheral_registers_structures
175    * @{
176    */
177  
178  /**
179    * @brief Analog to Digital Converter
180    */
181  
182  typedef struct
183  {
184    __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
185    __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
186    __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
187    __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
188    __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
189    __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
190    __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
191    __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
192    __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
193    __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
194    __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
195    __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
196    __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
197    __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
198    __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
199    __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
200    __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
201    __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
202    __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
203    __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
204  } ADC_TypeDef;
205  
206  typedef struct
207  {
208    __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
209    __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
210    __IO uint32_t CDR;    /*!< ADC common regular data register for dual
211                               AND triple modes,                            Address offset: ADC1 base address + 0x308 */
212  } ADC_Common_TypeDef;
213  
214  
215  /**
216    * @brief Controller Area Network TxMailBox
217    */
218  
219  typedef struct
220  {
221    __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
222    __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
223    __IO uint32_t TDLR; /*!< CAN mailbox data low register */
224    __IO uint32_t TDHR; /*!< CAN mailbox data high register */
225  } CAN_TxMailBox_TypeDef;
226  
227  /**
228    * @brief Controller Area Network FIFOMailBox
229    */
230  
231  typedef struct
232  {
233    __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
234    __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
235    __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
236    __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
237  } CAN_FIFOMailBox_TypeDef;
238  
239  /**
240    * @brief Controller Area Network FilterRegister
241    */
242  
243  typedef struct
244  {
245    __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
246    __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
247  } CAN_FilterRegister_TypeDef;
248  
249  /**
250    * @brief Controller Area Network
251    */
252  
253  typedef struct
254  {
255    __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
256    __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
257    __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
258    __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
259    __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
260    __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
261    __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
262    __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
263    uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
264    CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
265    CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
266    uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
267    __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
268    __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
269    uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
270    __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
271    uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
272    __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
273    uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
274    __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
275    uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
276    CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
277  } CAN_TypeDef;
278  
279  
280  /**
281    * @brief Consumer Electronics Control
282    */
283  
284  typedef struct
285  {
286    __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
287    __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
288    __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
289    __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
290    __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
291    __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
292  }CEC_TypeDef;
293  /**
294    * @brief CRC calculation unit
295    */
296  
297  typedef struct
298  {
299    __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
300    __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
301    uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
302    uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
303    __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
304  } CRC_TypeDef;
305  
306  /**
307    * @brief Digital to Analog Converter
308    */
309  
310  typedef struct
311  {
312    __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
313    __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
314    __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
315    __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
316    __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
317    __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
318    __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
319    __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
320    __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
321    __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
322    __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
323    __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
324    __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
325    __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
326  } DAC_TypeDef;
327  
328  /**
329    * @brief Debug MCU
330    */
331  
332  typedef struct
333  {
334    __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
335    __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
336    __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
337    __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
338  }DBGMCU_TypeDef;
339  
340  /**
341    * @brief DCMI
342    */
343  
344  typedef struct
345  {
346    __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
347    __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
348    __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
349    __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
350    __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
351    __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
352    __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
353    __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
354    __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
355    __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
356    __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
357  } DCMI_TypeDef;
358  
359  /**
360    * @brief DMA Controller
361    */
362  
363  typedef struct
364  {
365    __IO uint32_t CR;     /*!< DMA stream x configuration register      */
366    __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
367    __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
368    __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
369    __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
370    __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
371  } DMA_Stream_TypeDef;
372  
373  typedef struct
374  {
375    __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
376    __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
377    __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
378    __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
379  } DMA_TypeDef;
380  
381  /**
382    * @brief External Interrupt/Event Controller
383    */
384  
385  typedef struct
386  {
387    __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
388    __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
389    __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
390    __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
391    __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
392    __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
393  } EXTI_TypeDef;
394  
395  /**
396    * @brief FLASH Registers
397    */
398  
399  typedef struct
400  {
401    __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
402    __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
403    __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
404    __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
405    __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
406    __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
407    __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
408  } FLASH_TypeDef;
409  
410  /**
411    * @brief Flexible Memory Controller
412    */
413  
414  typedef struct
415  {
416    __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
417  } FMC_Bank1_TypeDef;
418  
419  /**
420    * @brief Flexible Memory Controller Bank1E
421    */
422  
423  typedef struct
424  {
425    __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
426  } FMC_Bank1E_TypeDef;
427  
428  /**
429    * @brief Flexible Memory Controller Bank3
430    */
431  
432  typedef struct
433  {
434    __IO uint32_t PCR;       /*!< NAND Flash control register,                       Address offset: 0x80 */
435    __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
436    __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
437    __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
438    uint32_t      RESERVED;  /*!< Reserved, 0x90                                                          */
439    __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
440  } FMC_Bank3_TypeDef;
441  
442  /**
443    * @brief Flexible Memory Controller Bank5_6
444    */
445  
446  typedef struct
447  {
448    __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
449    __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
450    __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */
451    __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */
452    __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */
453  } FMC_Bank5_6_TypeDef;
454  
455  /**
456    * @brief General Purpose I/O
457    */
458  
459  typedef struct
460  {
461    __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
462    __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
463    __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
464    __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
465    __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
466    __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
467    __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
468    __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
469    __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
470  } GPIO_TypeDef;
471  
472  /**
473    * @brief System configuration controller
474    */
475  
476  typedef struct
477  {
478    __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
479    __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
480    __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
481    uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
482    __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
483    uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */
484    __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */
485  } SYSCFG_TypeDef;
486  
487  /**
488    * @brief Inter-integrated Circuit Interface
489    */
490  
491  typedef struct
492  {
493    __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
494    __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
495    __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
496    __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
497    __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
498    __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
499    __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
500    __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
501    __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
502    __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
503  } I2C_TypeDef;
504  
505  /**
506    * @brief Inter-integrated Circuit Interface
507    */
508  
509  typedef struct
510  {
511    __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
512    __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
513    __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
514    __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
515    __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
516    __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
517    __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
518    __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
519    __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
520    __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
521    __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
522  } FMPI2C_TypeDef;
523  
524  /**
525    * @brief Independent WATCHDOG
526    */
527  
528  typedef struct
529  {
530    __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
531    __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
532    __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
533    __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
534  } IWDG_TypeDef;
535  
536  
537  /**
538    * @brief Power Control
539    */
540  
541  typedef struct
542  {
543    __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
544    __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
545  } PWR_TypeDef;
546  
547  /**
548    * @brief Reset and Clock Control
549    */
550  
551  typedef struct
552  {
553    __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
554    __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
555    __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
556    __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
557    __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
558    __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
559    __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
560    uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
561    __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
562    __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
563    uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
564    __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
565    __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
566    __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
567    uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
568    __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
569    __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
570    uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
571    __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
572    __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
573    __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
574    uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
575    __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
576    __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
577    uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
578    __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
579    __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
580    uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
581    __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
582    __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
583    __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
584    __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
585    __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated ENable Register,                            Address offset: 0x90 */
586    __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
587  } RCC_TypeDef;
588  
589  /**
590    * @brief Real-Time Clock
591    */
592  
593  typedef struct
594  {
595    __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
596    __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
597    __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
598    __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
599    __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
600    __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
601    __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
602    __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
603    __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
604    __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
605    __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
606    __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
607    __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
608    __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
609    __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
610    __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
611    __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
612    __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
613    __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
614    uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
615    __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
616    __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
617    __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
618    __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
619    __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
620    __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
621    __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
622    __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
623    __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
624    __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
625    __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
626    __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
627    __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
628    __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
629    __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
630    __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
631    __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
632    __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
633    __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
634    __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
635  } RTC_TypeDef;
636  
637  /**
638    * @brief Serial Audio Interface
639    */
640  
641  typedef struct
642  {
643    __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
644  } SAI_TypeDef;
645  
646  typedef struct
647  {
648    __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
649    __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
650    __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
651    __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
652    __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
653    __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
654    __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
655    __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
656  } SAI_Block_TypeDef;
657  
658  /**
659    * @brief SD host Interface
660    */
661  
662  typedef struct
663  {
664    __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
665    __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
666    __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
667    __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
668    __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
669    __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
670    __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
671    __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
672    __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
673    __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
674    __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
675    __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
676    __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
677    __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
678    __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
679    __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
680    uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
681    __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
682    uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
683    __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
684  } SDIO_TypeDef;
685  
686  /**
687    * @brief Serial Peripheral Interface
688    */
689  
690  typedef struct
691  {
692    __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
693    __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
694    __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
695    __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
696    __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
697    __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
698    __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
699    __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
700    __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
701  } SPI_TypeDef;
702  
703  /**
704    * @brief QUAD Serial Peripheral Interface
705    */
706  
707  typedef struct
708  {
709    __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
710    __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
711    __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
712    __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
713    __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
714    __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
715    __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
716    __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
717    __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
718    __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
719    __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
720    __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
721    __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
722  } QUADSPI_TypeDef;
723  
724  /**
725    * @brief SPDIFRX Interface
726    */
727  
728  typedef struct
729  {
730    __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
731    __IO uint16_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
732    uint16_t        RESERVED0;    /*!< Reserved,  0x06                                          */
733    __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
734    __IO uint16_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
735    uint16_t        RESERVED1;    /*!< Reserved,  0x0E                                          */
736    __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
737    __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
738     __IO uint32_t  DIR;          /*!< Debug Information register,         Address offset: 0x18 */
739    uint16_t        RESERVED2;    /*!< Reserved,  0x1A                                          */
740  } SPDIFRX_TypeDef;
741  
742  /**
743    * @brief TIM
744    */
745  
746  typedef struct
747  {
748    __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
749    __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
750    __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
751    __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
752    __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
753    __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
754    __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
755    __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
756    __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
757    __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
758    __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
759    __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
760    __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
761    __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
762    __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
763    __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
764    __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
765    __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
766    __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
767    __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
768    __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
769  } TIM_TypeDef;
770  
771  /**
772    * @brief Universal Synchronous Asynchronous Receiver Transmitter
773    */
774  
775  typedef struct
776  {
777    __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
778    __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
779    __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
780    __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
781    __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
782    __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
783    __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
784  } USART_TypeDef;
785  
786  /**
787    * @brief Window WATCHDOG
788    */
789  
790  typedef struct
791  {
792    __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
793    __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
794    __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
795  } WWDG_TypeDef;
796  /**
797    * @brief USB_OTG_Core_Registers
798    */
799  typedef struct
800  {
801    __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
802    __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
803    __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
804    __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
805    __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
806    __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
807    __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
808    __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
809    __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
810    __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
811    __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
812    __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
813    uint32_t Reserved30[2];             /*!< Reserved                                     030h */
814    __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
815    __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
816    uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
817    __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
818    uint32_t  Reserved6;                /*!< Reserved                                     050h */
819    __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
820    uint32_t  Reserved;                 /*!< Reserved                                     058h */
821    __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
822    uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */
823    __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
824    __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
825  } USB_OTG_GlobalTypeDef;
826  
827  /**
828    * @brief USB_OTG_device_Registers
829    */
830  typedef struct
831  {
832    __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
833    __IO uint32_t DCTL;            /*!< dev Control Register         804h */
834    __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
835    uint32_t Reserved0C;           /*!< Reserved                     80Ch */
836    __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
837    __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
838    __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
839    __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
840    uint32_t  Reserved20;          /*!< Reserved                     820h */
841    uint32_t Reserved9;            /*!< Reserved                     824h */
842    __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
843    __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
844    __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
845    __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
846    __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
847    __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
848    uint32_t Reserved40;           /*!< dedicated EP mask            840h */
849    __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
850    uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
851    __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
852  } USB_OTG_DeviceTypeDef;
853  
854  /**
855    * @brief USB_OTG_IN_Endpoint-Specific_Register
856    */
857  typedef struct
858  {
859    __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
860    uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
861    __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
862    uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
863    __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
864    __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
865    __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
866    uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
867  } USB_OTG_INEndpointTypeDef;
868  
869  /**
870    * @brief USB_OTG_OUT_Endpoint-Specific_Registers
871    */
872  typedef struct
873  {
874    __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
875    uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
876    __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
877    uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
878    __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
879    __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
880    uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
881  } USB_OTG_OUTEndpointTypeDef;
882  
883  /**
884    * @brief USB_OTG_Host_Mode_Register_Structures
885    */
886  typedef struct
887  {
888    __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
889    __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
890    __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
891    uint32_t Reserved40C;           /*!< Reserved                             40Ch */
892    __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
893    __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
894    __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
895  } USB_OTG_HostTypeDef;
896  
897  /**
898    * @brief USB_OTG_Host_Channel_Specific_Registers
899    */
900  typedef struct
901  {
902    __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
903    __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
904    __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
905    __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
906    __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
907    __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
908    uint32_t Reserved[2];           /*!< Reserved                                      */
909  } USB_OTG_HostChannelTypeDef;
910  
911  /**
912    * @}
913    */
914  
915  /** @addtogroup Peripheral_memory_map
916    * @{
917    */
918  #define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
919  #define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                              */
920  #define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
921  #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
922  #define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
923  #define FMC_R_BASE            0xA0000000UL /*!< FMC registers base address                                                 */
924  #define QSPI_R_BASE           0xA0001000UL /*!< QuadSPI registers base address                                             */
925  #define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
926  #define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
927  #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
928  #define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
929  #define FLASH_END             0x0807FFFFUL /*!< FLASH end address                                                          */
930  #define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
931  #define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
932  
933  /* Legacy defines */
934  #define SRAM_BASE             SRAM1_BASE
935  #define SRAM_BB_BASE          SRAM1_BB_BASE
936  
937  /*!< Peripheral memory map */
938  #define APB1PERIPH_BASE       PERIPH_BASE
939  #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
940  #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
941  #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
942  
943  /*!< APB1 peripherals */
944  #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
945  #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
946  #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
947  #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
948  #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
949  #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
950  #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
951  #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
952  #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
953  #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
954  #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
955  #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
956  #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
957  #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
958  #define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000UL)
959  #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
960  #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
961  #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
962  #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
963  #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
964  #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
965  #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
966  #define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000UL)
967  #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
968  #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
969  #define CEC_BASE              (APB1PERIPH_BASE + 0x6C00UL)
970  #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
971  #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
972  
973  /*!< APB2 peripherals */
974  #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
975  #define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
976  #define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
977  #define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
978  #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
979  #define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
980  #define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
981  #define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
982  /* Legacy define */
983  #define ADC_BASE               ADC123_COMMON_BASE
984  #define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
985  #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
986  #define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)
987  #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
988  #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
989  #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
990  #define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
991  #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
992  #define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)
993  #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
994  #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
995  #define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00UL)
996  #define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
997  #define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
998  
999  /*!< AHB1 peripherals */
1000  #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
1001  #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
1002  #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
1003  #define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
1004  #define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
1005  #define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
1006  #define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
1007  #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
1008  #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1009  #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
1010  #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
1011  #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
1012  #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
1013  #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
1014  #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
1015  #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
1016  #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
1017  #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
1018  #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
1019  #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
1020  #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
1021  #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
1022  #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
1023  #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
1024  #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
1025  #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
1026  #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
1027  #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
1028  #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
1029  
1030  /*!< AHB2 peripherals */
1031  #define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
1032  
1033  /*!< FMC Bankx registers base address */
1034  #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
1035  #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
1036  #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
1037  #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
1038  
1039  
1040  /*!< Debug MCU registers base address */
1041  #define DBGMCU_BASE           0xE0042000UL
1042  /*!< USB registers base address */
1043  #define USB_OTG_HS_PERIPH_BASE               0x40040000UL
1044  #define USB_OTG_FS_PERIPH_BASE               0x50000000UL
1045  
1046  #define USB_OTG_GLOBAL_BASE                  0x000UL
1047  #define USB_OTG_DEVICE_BASE                  0x800UL
1048  #define USB_OTG_IN_ENDPOINT_BASE             0x900UL
1049  #define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
1050  #define USB_OTG_EP_REG_SIZE                  0x20UL
1051  #define USB_OTG_HOST_BASE                    0x400UL
1052  #define USB_OTG_HOST_PORT_BASE               0x440UL
1053  #define USB_OTG_HOST_CHANNEL_BASE            0x500UL
1054  #define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
1055  #define USB_OTG_PCGCCTL_BASE                 0xE00UL
1056  #define USB_OTG_FIFO_BASE                    0x1000UL
1057  #define USB_OTG_FIFO_SIZE                    0x1000UL
1058  
1059  #define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
1060  #define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
1061  #define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
1062  /**
1063    * @}
1064    */
1065  
1066  /** @addtogroup Peripheral_declaration
1067    * @{
1068    */
1069  #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1070  #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1071  #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1072  #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1073  #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1074  #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1075  #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
1076  #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
1077  #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
1078  #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1079  #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1080  #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1081  #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1082  #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1083  #define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1084  #define USART2              ((USART_TypeDef *) USART2_BASE)
1085  #define USART3              ((USART_TypeDef *) USART3_BASE)
1086  #define UART4               ((USART_TypeDef *) UART4_BASE)
1087  #define UART5               ((USART_TypeDef *) UART5_BASE)
1088  #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1089  #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1090  #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1091  #define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1092  #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1093  #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1094  #define CEC                 ((CEC_TypeDef *) CEC_BASE)
1095  #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1096  #define DAC1                ((DAC_TypeDef *) DAC_BASE)
1097  #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1098  #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1099  #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1100  #define USART1              ((USART_TypeDef *) USART1_BASE)
1101  #define USART6              ((USART_TypeDef *) USART6_BASE)
1102  #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1103  #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1104  #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1105  #define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1106  /* Legacy define */
1107  #define ADC                  ADC123_COMMON
1108  #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
1109  #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1110  #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1111  #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1112  #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1113  #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
1114  #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
1115  #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
1116  #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1117  #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1118  #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1119  #define SAI2                ((SAI_TypeDef *) SAI2_BASE)
1120  #define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1121  #define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1122  #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1123  #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1124  #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1125  #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1126  #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1127  #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1128  #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1129  #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1130  #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1131  #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1132  #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1133  #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1134  #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1135  #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1136  #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1137  #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1138  #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1139  #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1140  #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1141  #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1142  #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1143  #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1144  #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1145  #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1146  #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1147  #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1148  #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1149  #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1150  #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1151  #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
1152  #define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1153  #define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1154  #define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1155  #define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1156  #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1157  #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1158  #define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1159  #define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1160  
1161  /**
1162    * @}
1163    */
1164  
1165  /** @addtogroup Exported_constants
1166    * @{
1167    */
1168  
1169    /** @addtogroup Peripheral_Registers_Bits_Definition
1170    * @{
1171    */
1172  
1173  /******************************************************************************/
1174  /*                         Peripheral Registers_Bits_Definition               */
1175  /******************************************************************************/
1176  
1177  /******************************************************************************/
1178  /*                                                                            */
1179  /*                        Analog to Digital Converter                         */
1180  /*                                                                            */
1181  /******************************************************************************/
1182  /*
1183   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1184   */
1185  #define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */
1186  
1187  /********************  Bit definition for ADC_SR register  ********************/
1188  #define ADC_SR_AWD_Pos            (0U)
1189  #define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
1190  #define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
1191  #define ADC_SR_EOC_Pos            (1U)
1192  #define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
1193  #define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
1194  #define ADC_SR_JEOC_Pos           (2U)
1195  #define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
1196  #define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
1197  #define ADC_SR_JSTRT_Pos          (3U)
1198  #define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
1199  #define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
1200  #define ADC_SR_STRT_Pos           (4U)
1201  #define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
1202  #define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
1203  #define ADC_SR_OVR_Pos            (5U)
1204  #define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
1205  #define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
1206  
1207  /*******************  Bit definition for ADC_CR1 register  ********************/
1208  #define ADC_CR1_AWDCH_Pos         (0U)
1209  #define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
1210  #define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1211  #define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
1212  #define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
1213  #define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
1214  #define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
1215  #define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
1216  #define ADC_CR1_EOCIE_Pos         (5U)
1217  #define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
1218  #define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
1219  #define ADC_CR1_AWDIE_Pos         (6U)
1220  #define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
1221  #define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
1222  #define ADC_CR1_JEOCIE_Pos        (7U)
1223  #define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
1224  #define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
1225  #define ADC_CR1_SCAN_Pos          (8U)
1226  #define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
1227  #define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
1228  #define ADC_CR1_AWDSGL_Pos        (9U)
1229  #define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
1230  #define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
1231  #define ADC_CR1_JAUTO_Pos         (10U)
1232  #define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
1233  #define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
1234  #define ADC_CR1_DISCEN_Pos        (11U)
1235  #define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
1236  #define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
1237  #define ADC_CR1_JDISCEN_Pos       (12U)
1238  #define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
1239  #define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
1240  #define ADC_CR1_DISCNUM_Pos       (13U)
1241  #define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
1242  #define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1243  #define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
1244  #define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
1245  #define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
1246  #define ADC_CR1_JAWDEN_Pos        (22U)
1247  #define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
1248  #define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
1249  #define ADC_CR1_AWDEN_Pos         (23U)
1250  #define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
1251  #define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
1252  #define ADC_CR1_RES_Pos           (24U)
1253  #define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
1254  #define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
1255  #define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
1256  #define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
1257  #define ADC_CR1_OVRIE_Pos         (26U)
1258  #define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
1259  #define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
1260  
1261  /*******************  Bit definition for ADC_CR2 register  ********************/
1262  #define ADC_CR2_ADON_Pos          (0U)
1263  #define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
1264  #define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
1265  #define ADC_CR2_CONT_Pos          (1U)
1266  #define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
1267  #define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
1268  #define ADC_CR2_DMA_Pos           (8U)
1269  #define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
1270  #define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
1271  #define ADC_CR2_DDS_Pos           (9U)
1272  #define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
1273  #define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
1274  #define ADC_CR2_EOCS_Pos          (10U)
1275  #define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
1276  #define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
1277  #define ADC_CR2_ALIGN_Pos         (11U)
1278  #define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
1279  #define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
1280  #define ADC_CR2_JEXTSEL_Pos       (16U)
1281  #define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
1282  #define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1283  #define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
1284  #define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
1285  #define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
1286  #define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
1287  #define ADC_CR2_JEXTEN_Pos        (20U)
1288  #define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
1289  #define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1290  #define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
1291  #define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
1292  #define ADC_CR2_JSWSTART_Pos      (22U)
1293  #define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
1294  #define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
1295  #define ADC_CR2_EXTSEL_Pos        (24U)
1296  #define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
1297  #define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1298  #define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
1299  #define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
1300  #define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
1301  #define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
1302  #define ADC_CR2_EXTEN_Pos         (28U)
1303  #define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
1304  #define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1305  #define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
1306  #define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
1307  #define ADC_CR2_SWSTART_Pos       (30U)
1308  #define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
1309  #define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
1310  
1311  /******************  Bit definition for ADC_SMPR1 register  *******************/
1312  #define ADC_SMPR1_SMP10_Pos       (0U)
1313  #define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
1314  #define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1315  #define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
1316  #define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
1317  #define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
1318  #define ADC_SMPR1_SMP11_Pos       (3U)
1319  #define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
1320  #define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1321  #define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
1322  #define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
1323  #define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
1324  #define ADC_SMPR1_SMP12_Pos       (6U)
1325  #define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
1326  #define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1327  #define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
1328  #define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
1329  #define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
1330  #define ADC_SMPR1_SMP13_Pos       (9U)
1331  #define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
1332  #define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1333  #define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
1334  #define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
1335  #define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
1336  #define ADC_SMPR1_SMP14_Pos       (12U)
1337  #define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
1338  #define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1339  #define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
1340  #define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
1341  #define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
1342  #define ADC_SMPR1_SMP15_Pos       (15U)
1343  #define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
1344  #define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1345  #define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
1346  #define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
1347  #define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
1348  #define ADC_SMPR1_SMP16_Pos       (18U)
1349  #define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
1350  #define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1351  #define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
1352  #define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
1353  #define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
1354  #define ADC_SMPR1_SMP17_Pos       (21U)
1355  #define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
1356  #define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1357  #define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
1358  #define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
1359  #define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
1360  #define ADC_SMPR1_SMP18_Pos       (24U)
1361  #define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
1362  #define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1363  #define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
1364  #define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
1365  #define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
1366  
1367  /******************  Bit definition for ADC_SMPR2 register  *******************/
1368  #define ADC_SMPR2_SMP0_Pos        (0U)
1369  #define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
1370  #define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1371  #define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
1372  #define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
1373  #define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
1374  #define ADC_SMPR2_SMP1_Pos        (3U)
1375  #define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
1376  #define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1377  #define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
1378  #define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
1379  #define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
1380  #define ADC_SMPR2_SMP2_Pos        (6U)
1381  #define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
1382  #define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1383  #define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
1384  #define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
1385  #define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
1386  #define ADC_SMPR2_SMP3_Pos        (9U)
1387  #define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
1388  #define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1389  #define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
1390  #define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
1391  #define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
1392  #define ADC_SMPR2_SMP4_Pos        (12U)
1393  #define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
1394  #define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1395  #define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
1396  #define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
1397  #define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
1398  #define ADC_SMPR2_SMP5_Pos        (15U)
1399  #define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
1400  #define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1401  #define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
1402  #define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
1403  #define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
1404  #define ADC_SMPR2_SMP6_Pos        (18U)
1405  #define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
1406  #define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1407  #define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
1408  #define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
1409  #define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
1410  #define ADC_SMPR2_SMP7_Pos        (21U)
1411  #define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
1412  #define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1413  #define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
1414  #define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
1415  #define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
1416  #define ADC_SMPR2_SMP8_Pos        (24U)
1417  #define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
1418  #define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1419  #define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
1420  #define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
1421  #define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
1422  #define ADC_SMPR2_SMP9_Pos        (27U)
1423  #define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
1424  #define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1425  #define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
1426  #define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
1427  #define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
1428  
1429  /******************  Bit definition for ADC_JOFR1 register  *******************/
1430  #define ADC_JOFR1_JOFFSET1_Pos    (0U)
1431  #define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
1432  #define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
1433  
1434  /******************  Bit definition for ADC_JOFR2 register  *******************/
1435  #define ADC_JOFR2_JOFFSET2_Pos    (0U)
1436  #define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
1437  #define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
1438  
1439  /******************  Bit definition for ADC_JOFR3 register  *******************/
1440  #define ADC_JOFR3_JOFFSET3_Pos    (0U)
1441  #define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
1442  #define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
1443  
1444  /******************  Bit definition for ADC_JOFR4 register  *******************/
1445  #define ADC_JOFR4_JOFFSET4_Pos    (0U)
1446  #define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
1447  #define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
1448  
1449  /*******************  Bit definition for ADC_HTR register  ********************/
1450  #define ADC_HTR_HT_Pos            (0U)
1451  #define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
1452  #define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
1453  
1454  /*******************  Bit definition for ADC_LTR register  ********************/
1455  #define ADC_LTR_LT_Pos            (0U)
1456  #define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
1457  #define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
1458  
1459  /*******************  Bit definition for ADC_SQR1 register  *******************/
1460  #define ADC_SQR1_SQ13_Pos         (0U)
1461  #define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
1462  #define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1463  #define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
1464  #define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
1465  #define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
1466  #define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
1467  #define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
1468  #define ADC_SQR1_SQ14_Pos         (5U)
1469  #define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
1470  #define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1471  #define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
1472  #define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
1473  #define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
1474  #define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
1475  #define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
1476  #define ADC_SQR1_SQ15_Pos         (10U)
1477  #define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
1478  #define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1479  #define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
1480  #define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
1481  #define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
1482  #define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
1483  #define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
1484  #define ADC_SQR1_SQ16_Pos         (15U)
1485  #define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
1486  #define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1487  #define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
1488  #define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
1489  #define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
1490  #define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
1491  #define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
1492  #define ADC_SQR1_L_Pos            (20U)
1493  #define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
1494  #define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
1495  #define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
1496  #define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
1497  #define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
1498  #define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
1499  
1500  /*******************  Bit definition for ADC_SQR2 register  *******************/
1501  #define ADC_SQR2_SQ7_Pos          (0U)
1502  #define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
1503  #define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1504  #define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
1505  #define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
1506  #define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
1507  #define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
1508  #define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
1509  #define ADC_SQR2_SQ8_Pos          (5U)
1510  #define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
1511  #define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1512  #define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
1513  #define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
1514  #define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
1515  #define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
1516  #define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
1517  #define ADC_SQR2_SQ9_Pos          (10U)
1518  #define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
1519  #define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1520  #define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
1521  #define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
1522  #define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
1523  #define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
1524  #define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
1525  #define ADC_SQR2_SQ10_Pos         (15U)
1526  #define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
1527  #define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1528  #define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
1529  #define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
1530  #define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
1531  #define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
1532  #define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
1533  #define ADC_SQR2_SQ11_Pos         (20U)
1534  #define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
1535  #define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1536  #define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
1537  #define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
1538  #define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
1539  #define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
1540  #define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
1541  #define ADC_SQR2_SQ12_Pos         (25U)
1542  #define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
1543  #define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1544  #define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
1545  #define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
1546  #define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
1547  #define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
1548  #define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
1549  
1550  /*******************  Bit definition for ADC_SQR3 register  *******************/
1551  #define ADC_SQR3_SQ1_Pos          (0U)
1552  #define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
1553  #define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1554  #define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
1555  #define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
1556  #define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
1557  #define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
1558  #define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
1559  #define ADC_SQR3_SQ2_Pos          (5U)
1560  #define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
1561  #define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1562  #define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
1563  #define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
1564  #define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
1565  #define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
1566  #define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
1567  #define ADC_SQR3_SQ3_Pos          (10U)
1568  #define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
1569  #define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1570  #define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
1571  #define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
1572  #define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
1573  #define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
1574  #define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
1575  #define ADC_SQR3_SQ4_Pos          (15U)
1576  #define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
1577  #define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1578  #define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
1579  #define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
1580  #define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
1581  #define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
1582  #define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
1583  #define ADC_SQR3_SQ5_Pos          (20U)
1584  #define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
1585  #define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1586  #define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
1587  #define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
1588  #define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
1589  #define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
1590  #define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
1591  #define ADC_SQR3_SQ6_Pos          (25U)
1592  #define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
1593  #define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1594  #define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
1595  #define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
1596  #define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
1597  #define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
1598  #define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
1599  
1600  /*******************  Bit definition for ADC_JSQR register  *******************/
1601  #define ADC_JSQR_JSQ1_Pos         (0U)
1602  #define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
1603  #define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1604  #define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
1605  #define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
1606  #define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
1607  #define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
1608  #define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
1609  #define ADC_JSQR_JSQ2_Pos         (5U)
1610  #define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
1611  #define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1612  #define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
1613  #define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
1614  #define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
1615  #define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
1616  #define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
1617  #define ADC_JSQR_JSQ3_Pos         (10U)
1618  #define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
1619  #define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1620  #define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
1621  #define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
1622  #define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
1623  #define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
1624  #define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
1625  #define ADC_JSQR_JSQ4_Pos         (15U)
1626  #define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
1627  #define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1628  #define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
1629  #define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
1630  #define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
1631  #define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
1632  #define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
1633  #define ADC_JSQR_JL_Pos           (20U)
1634  #define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
1635  #define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
1636  #define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
1637  #define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
1638  
1639  /*******************  Bit definition for ADC_JDR1 register  *******************/
1640  #define ADC_JDR1_JDATA_Pos        (0U)
1641  #define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
1642  #define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
1643  
1644  /*******************  Bit definition for ADC_JDR2 register  *******************/
1645  #define ADC_JDR2_JDATA_Pos        (0U)
1646  #define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
1647  #define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
1648  
1649  /*******************  Bit definition for ADC_JDR3 register  *******************/
1650  #define ADC_JDR3_JDATA_Pos        (0U)
1651  #define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
1652  #define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
1653  
1654  /*******************  Bit definition for ADC_JDR4 register  *******************/
1655  #define ADC_JDR4_JDATA_Pos        (0U)
1656  #define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
1657  #define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
1658  
1659  /********************  Bit definition for ADC_DR register  ********************/
1660  #define ADC_DR_DATA_Pos           (0U)
1661  #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1662  #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
1663  #define ADC_DR_ADC2DATA_Pos       (16U)
1664  #define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
1665  #define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
1666  
1667  /*******************  Bit definition for ADC_CSR register  ********************/
1668  #define ADC_CSR_AWD1_Pos          (0U)
1669  #define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
1670  #define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
1671  #define ADC_CSR_EOC1_Pos          (1U)
1672  #define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
1673  #define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
1674  #define ADC_CSR_JEOC1_Pos         (2U)
1675  #define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
1676  #define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
1677  #define ADC_CSR_JSTRT1_Pos        (3U)
1678  #define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
1679  #define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
1680  #define ADC_CSR_STRT1_Pos         (4U)
1681  #define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
1682  #define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
1683  #define ADC_CSR_OVR1_Pos          (5U)
1684  #define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
1685  #define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
1686  #define ADC_CSR_AWD2_Pos          (8U)
1687  #define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
1688  #define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
1689  #define ADC_CSR_EOC2_Pos          (9U)
1690  #define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
1691  #define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
1692  #define ADC_CSR_JEOC2_Pos         (10U)
1693  #define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
1694  #define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
1695  #define ADC_CSR_JSTRT2_Pos        (11U)
1696  #define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
1697  #define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
1698  #define ADC_CSR_STRT2_Pos         (12U)
1699  #define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
1700  #define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
1701  #define ADC_CSR_OVR2_Pos          (13U)
1702  #define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
1703  #define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
1704  #define ADC_CSR_AWD3_Pos          (16U)
1705  #define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
1706  #define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
1707  #define ADC_CSR_EOC3_Pos          (17U)
1708  #define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
1709  #define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
1710  #define ADC_CSR_JEOC3_Pos         (18U)
1711  #define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
1712  #define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
1713  #define ADC_CSR_JSTRT3_Pos        (19U)
1714  #define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
1715  #define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
1716  #define ADC_CSR_STRT3_Pos         (20U)
1717  #define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
1718  #define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
1719  #define ADC_CSR_OVR3_Pos          (21U)
1720  #define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
1721  #define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
1722  
1723  /* Legacy defines */
1724  #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
1725  #define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
1726  #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
1727  
1728  /*******************  Bit definition for ADC_CCR register  ********************/
1729  #define ADC_CCR_MULTI_Pos         (0U)
1730  #define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
1731  #define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1732  #define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
1733  #define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
1734  #define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
1735  #define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
1736  #define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
1737  #define ADC_CCR_DELAY_Pos         (8U)
1738  #define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
1739  #define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1740  #define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
1741  #define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
1742  #define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
1743  #define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
1744  #define ADC_CCR_DDS_Pos           (13U)
1745  #define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
1746  #define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
1747  #define ADC_CCR_DMA_Pos           (14U)
1748  #define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
1749  #define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1750  #define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
1751  #define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
1752  #define ADC_CCR_ADCPRE_Pos        (16U)
1753  #define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
1754  #define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
1755  #define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
1756  #define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
1757  #define ADC_CCR_VBATE_Pos         (22U)
1758  #define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
1759  #define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
1760  #define ADC_CCR_TSVREFE_Pos       (23U)
1761  #define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
1762  #define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
1763  
1764  /*******************  Bit definition for ADC_CDR register  ********************/
1765  #define ADC_CDR_DATA1_Pos         (0U)
1766  #define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
1767  #define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
1768  #define ADC_CDR_DATA2_Pos         (16U)
1769  #define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
1770  #define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
1771  
1772  /* Legacy defines */
1773  #define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
1774  #define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
1775  
1776  /******************************************************************************/
1777  /*                                                                            */
1778  /*                         Controller Area Network                            */
1779  /*                                                                            */
1780  /******************************************************************************/
1781  /*!<CAN control and status registers */
1782  /*******************  Bit definition for CAN_MCR register  ********************/
1783  #define CAN_MCR_INRQ_Pos       (0U)
1784  #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
1785  #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
1786  #define CAN_MCR_SLEEP_Pos      (1U)
1787  #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
1788  #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
1789  #define CAN_MCR_TXFP_Pos       (2U)
1790  #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
1791  #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
1792  #define CAN_MCR_RFLM_Pos       (3U)
1793  #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
1794  #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
1795  #define CAN_MCR_NART_Pos       (4U)
1796  #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
1797  #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
1798  #define CAN_MCR_AWUM_Pos       (5U)
1799  #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
1800  #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
1801  #define CAN_MCR_ABOM_Pos       (6U)
1802  #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
1803  #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
1804  #define CAN_MCR_TTCM_Pos       (7U)
1805  #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
1806  #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
1807  #define CAN_MCR_RESET_Pos      (15U)
1808  #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
1809  #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
1810  #define CAN_MCR_DBF_Pos        (16U)
1811  #define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
1812  #define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
1813  /*******************  Bit definition for CAN_MSR register  ********************/
1814  #define CAN_MSR_INAK_Pos       (0U)
1815  #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
1816  #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
1817  #define CAN_MSR_SLAK_Pos       (1U)
1818  #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
1819  #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
1820  #define CAN_MSR_ERRI_Pos       (2U)
1821  #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
1822  #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
1823  #define CAN_MSR_WKUI_Pos       (3U)
1824  #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
1825  #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
1826  #define CAN_MSR_SLAKI_Pos      (4U)
1827  #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
1828  #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
1829  #define CAN_MSR_TXM_Pos        (8U)
1830  #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
1831  #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
1832  #define CAN_MSR_RXM_Pos        (9U)
1833  #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
1834  #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
1835  #define CAN_MSR_SAMP_Pos       (10U)
1836  #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
1837  #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
1838  #define CAN_MSR_RX_Pos         (11U)
1839  #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
1840  #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
1841  
1842  /*******************  Bit definition for CAN_TSR register  ********************/
1843  #define CAN_TSR_RQCP0_Pos      (0U)
1844  #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
1845  #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
1846  #define CAN_TSR_TXOK0_Pos      (1U)
1847  #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
1848  #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
1849  #define CAN_TSR_ALST0_Pos      (2U)
1850  #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
1851  #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
1852  #define CAN_TSR_TERR0_Pos      (3U)
1853  #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
1854  #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
1855  #define CAN_TSR_ABRQ0_Pos      (7U)
1856  #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
1857  #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
1858  #define CAN_TSR_RQCP1_Pos      (8U)
1859  #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
1860  #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
1861  #define CAN_TSR_TXOK1_Pos      (9U)
1862  #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
1863  #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
1864  #define CAN_TSR_ALST1_Pos      (10U)
1865  #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
1866  #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
1867  #define CAN_TSR_TERR1_Pos      (11U)
1868  #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
1869  #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
1870  #define CAN_TSR_ABRQ1_Pos      (15U)
1871  #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
1872  #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
1873  #define CAN_TSR_RQCP2_Pos      (16U)
1874  #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
1875  #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
1876  #define CAN_TSR_TXOK2_Pos      (17U)
1877  #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
1878  #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
1879  #define CAN_TSR_ALST2_Pos      (18U)
1880  #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
1881  #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
1882  #define CAN_TSR_TERR2_Pos      (19U)
1883  #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
1884  #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
1885  #define CAN_TSR_ABRQ2_Pos      (23U)
1886  #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
1887  #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
1888  #define CAN_TSR_CODE_Pos       (24U)
1889  #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
1890  #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
1891  
1892  #define CAN_TSR_TME_Pos        (26U)
1893  #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
1894  #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
1895  #define CAN_TSR_TME0_Pos       (26U)
1896  #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
1897  #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
1898  #define CAN_TSR_TME1_Pos       (27U)
1899  #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
1900  #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
1901  #define CAN_TSR_TME2_Pos       (28U)
1902  #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
1903  #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
1904  
1905  #define CAN_TSR_LOW_Pos        (29U)
1906  #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
1907  #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
1908  #define CAN_TSR_LOW0_Pos       (29U)
1909  #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
1910  #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
1911  #define CAN_TSR_LOW1_Pos       (30U)
1912  #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
1913  #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
1914  #define CAN_TSR_LOW2_Pos       (31U)
1915  #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
1916  #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
1917  
1918  /*******************  Bit definition for CAN_RF0R register  *******************/
1919  #define CAN_RF0R_FMP0_Pos      (0U)
1920  #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
1921  #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
1922  #define CAN_RF0R_FULL0_Pos     (3U)
1923  #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
1924  #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
1925  #define CAN_RF0R_FOVR0_Pos     (4U)
1926  #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
1927  #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
1928  #define CAN_RF0R_RFOM0_Pos     (5U)
1929  #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
1930  #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
1931  
1932  /*******************  Bit definition for CAN_RF1R register  *******************/
1933  #define CAN_RF1R_FMP1_Pos      (0U)
1934  #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
1935  #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
1936  #define CAN_RF1R_FULL1_Pos     (3U)
1937  #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
1938  #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
1939  #define CAN_RF1R_FOVR1_Pos     (4U)
1940  #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
1941  #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
1942  #define CAN_RF1R_RFOM1_Pos     (5U)
1943  #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
1944  #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
1945  
1946  /********************  Bit definition for CAN_IER register  *******************/
1947  #define CAN_IER_TMEIE_Pos      (0U)
1948  #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
1949  #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
1950  #define CAN_IER_FMPIE0_Pos     (1U)
1951  #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
1952  #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1953  #define CAN_IER_FFIE0_Pos      (2U)
1954  #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
1955  #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
1956  #define CAN_IER_FOVIE0_Pos     (3U)
1957  #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
1958  #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
1959  #define CAN_IER_FMPIE1_Pos     (4U)
1960  #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
1961  #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1962  #define CAN_IER_FFIE1_Pos      (5U)
1963  #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
1964  #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
1965  #define CAN_IER_FOVIE1_Pos     (6U)
1966  #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
1967  #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
1968  #define CAN_IER_EWGIE_Pos      (8U)
1969  #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
1970  #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
1971  #define CAN_IER_EPVIE_Pos      (9U)
1972  #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
1973  #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
1974  #define CAN_IER_BOFIE_Pos      (10U)
1975  #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
1976  #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
1977  #define CAN_IER_LECIE_Pos      (11U)
1978  #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
1979  #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
1980  #define CAN_IER_ERRIE_Pos      (15U)
1981  #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
1982  #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
1983  #define CAN_IER_WKUIE_Pos      (16U)
1984  #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
1985  #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
1986  #define CAN_IER_SLKIE_Pos      (17U)
1987  #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
1988  #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
1989  #define CAN_IER_EWGIE_Pos      (8U)
1990  
1991  /********************  Bit definition for CAN_ESR register  *******************/
1992  #define CAN_ESR_EWGF_Pos       (0U)
1993  #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
1994  #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
1995  #define CAN_ESR_EPVF_Pos       (1U)
1996  #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
1997  #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
1998  #define CAN_ESR_BOFF_Pos       (2U)
1999  #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
2000  #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
2001  
2002  #define CAN_ESR_LEC_Pos        (4U)
2003  #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
2004  #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
2005  #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
2006  #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
2007  #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
2008  
2009  #define CAN_ESR_TEC_Pos        (16U)
2010  #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
2011  #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2012  #define CAN_ESR_REC_Pos        (24U)
2013  #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
2014  #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2015  
2016  /*******************  Bit definition for CAN_BTR register  ********************/
2017  #define CAN_BTR_BRP_Pos        (0U)
2018  #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
2019  #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
2020  #define CAN_BTR_TS1_Pos        (16U)
2021  #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
2022  #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
2023  #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
2024  #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
2025  #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
2026  #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
2027  #define CAN_BTR_TS2_Pos        (20U)
2028  #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
2029  #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
2030  #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
2031  #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
2032  #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
2033  #define CAN_BTR_SJW_Pos        (24U)
2034  #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
2035  #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
2036  #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
2037  #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
2038  #define CAN_BTR_LBKM_Pos       (30U)
2039  #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
2040  #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
2041  #define CAN_BTR_SILM_Pos       (31U)
2042  #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
2043  #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
2044  
2045  
2046  /*!<Mailbox registers */
2047  /******************  Bit definition for CAN_TI0R register  ********************/
2048  #define CAN_TI0R_TXRQ_Pos      (0U)
2049  #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
2050  #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2051  #define CAN_TI0R_RTR_Pos       (1U)
2052  #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
2053  #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
2054  #define CAN_TI0R_IDE_Pos       (2U)
2055  #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
2056  #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
2057  #define CAN_TI0R_EXID_Pos      (3U)
2058  #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2059  #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
2060  #define CAN_TI0R_STID_Pos      (21U)
2061  #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
2062  #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2063  
2064  /******************  Bit definition for CAN_TDT0R register  *******************/
2065  #define CAN_TDT0R_DLC_Pos      (0U)
2066  #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
2067  #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
2068  #define CAN_TDT0R_TGT_Pos      (8U)
2069  #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
2070  #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2071  #define CAN_TDT0R_TIME_Pos     (16U)
2072  #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2073  #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
2074  
2075  /******************  Bit definition for CAN_TDL0R register  *******************/
2076  #define CAN_TDL0R_DATA0_Pos    (0U)
2077  #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2078  #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2079  #define CAN_TDL0R_DATA1_Pos    (8U)
2080  #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2081  #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2082  #define CAN_TDL0R_DATA2_Pos    (16U)
2083  #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2084  #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2085  #define CAN_TDL0R_DATA3_Pos    (24U)
2086  #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2087  #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2088  
2089  /******************  Bit definition for CAN_TDH0R register  *******************/
2090  #define CAN_TDH0R_DATA4_Pos    (0U)
2091  #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2092  #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2093  #define CAN_TDH0R_DATA5_Pos    (8U)
2094  #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2095  #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2096  #define CAN_TDH0R_DATA6_Pos    (16U)
2097  #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2098  #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2099  #define CAN_TDH0R_DATA7_Pos    (24U)
2100  #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2101  #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2102  
2103  /*******************  Bit definition for CAN_TI1R register  *******************/
2104  #define CAN_TI1R_TXRQ_Pos      (0U)
2105  #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
2106  #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2107  #define CAN_TI1R_RTR_Pos       (1U)
2108  #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
2109  #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
2110  #define CAN_TI1R_IDE_Pos       (2U)
2111  #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
2112  #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
2113  #define CAN_TI1R_EXID_Pos      (3U)
2114  #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2115  #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
2116  #define CAN_TI1R_STID_Pos      (21U)
2117  #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
2118  #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2119  
2120  /*******************  Bit definition for CAN_TDT1R register  ******************/
2121  #define CAN_TDT1R_DLC_Pos      (0U)
2122  #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
2123  #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
2124  #define CAN_TDT1R_TGT_Pos      (8U)
2125  #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
2126  #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2127  #define CAN_TDT1R_TIME_Pos     (16U)
2128  #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2129  #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
2130  
2131  /*******************  Bit definition for CAN_TDL1R register  ******************/
2132  #define CAN_TDL1R_DATA0_Pos    (0U)
2133  #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2134  #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2135  #define CAN_TDL1R_DATA1_Pos    (8U)
2136  #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2137  #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2138  #define CAN_TDL1R_DATA2_Pos    (16U)
2139  #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2140  #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2141  #define CAN_TDL1R_DATA3_Pos    (24U)
2142  #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2143  #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2144  
2145  /*******************  Bit definition for CAN_TDH1R register  ******************/
2146  #define CAN_TDH1R_DATA4_Pos    (0U)
2147  #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2148  #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2149  #define CAN_TDH1R_DATA5_Pos    (8U)
2150  #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2151  #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2152  #define CAN_TDH1R_DATA6_Pos    (16U)
2153  #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2154  #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2155  #define CAN_TDH1R_DATA7_Pos    (24U)
2156  #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2157  #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2158  
2159  /*******************  Bit definition for CAN_TI2R register  *******************/
2160  #define CAN_TI2R_TXRQ_Pos      (0U)
2161  #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
2162  #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2163  #define CAN_TI2R_RTR_Pos       (1U)
2164  #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
2165  #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
2166  #define CAN_TI2R_IDE_Pos       (2U)
2167  #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
2168  #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
2169  #define CAN_TI2R_EXID_Pos      (3U)
2170  #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
2171  #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
2172  #define CAN_TI2R_STID_Pos      (21U)
2173  #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
2174  #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2175  
2176  /*******************  Bit definition for CAN_TDT2R register  ******************/
2177  #define CAN_TDT2R_DLC_Pos      (0U)
2178  #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
2179  #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
2180  #define CAN_TDT2R_TGT_Pos      (8U)
2181  #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
2182  #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
2183  #define CAN_TDT2R_TIME_Pos     (16U)
2184  #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
2185  #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
2186  
2187  /*******************  Bit definition for CAN_TDL2R register  ******************/
2188  #define CAN_TDL2R_DATA0_Pos    (0U)
2189  #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
2190  #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2191  #define CAN_TDL2R_DATA1_Pos    (8U)
2192  #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
2193  #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2194  #define CAN_TDL2R_DATA2_Pos    (16U)
2195  #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
2196  #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2197  #define CAN_TDL2R_DATA3_Pos    (24U)
2198  #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
2199  #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2200  
2201  /*******************  Bit definition for CAN_TDH2R register  ******************/
2202  #define CAN_TDH2R_DATA4_Pos    (0U)
2203  #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
2204  #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2205  #define CAN_TDH2R_DATA5_Pos    (8U)
2206  #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
2207  #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2208  #define CAN_TDH2R_DATA6_Pos    (16U)
2209  #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
2210  #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2211  #define CAN_TDH2R_DATA7_Pos    (24U)
2212  #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
2213  #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2214  
2215  /*******************  Bit definition for CAN_RI0R register  *******************/
2216  #define CAN_RI0R_RTR_Pos       (1U)
2217  #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
2218  #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
2219  #define CAN_RI0R_IDE_Pos       (2U)
2220  #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
2221  #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
2222  #define CAN_RI0R_EXID_Pos      (3U)
2223  #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2224  #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
2225  #define CAN_RI0R_STID_Pos      (21U)
2226  #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
2227  #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2228  
2229  /*******************  Bit definition for CAN_RDT0R register  ******************/
2230  #define CAN_RDT0R_DLC_Pos      (0U)
2231  #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
2232  #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
2233  #define CAN_RDT0R_FMI_Pos      (8U)
2234  #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
2235  #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
2236  #define CAN_RDT0R_TIME_Pos     (16U)
2237  #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2238  #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
2239  
2240  /*******************  Bit definition for CAN_RDL0R register  ******************/
2241  #define CAN_RDL0R_DATA0_Pos    (0U)
2242  #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2243  #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
2244  #define CAN_RDL0R_DATA1_Pos    (8U)
2245  #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2246  #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
2247  #define CAN_RDL0R_DATA2_Pos    (16U)
2248  #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2249  #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
2250  #define CAN_RDL0R_DATA3_Pos    (24U)
2251  #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2252  #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
2253  
2254  /*******************  Bit definition for CAN_RDH0R register  ******************/
2255  #define CAN_RDH0R_DATA4_Pos    (0U)
2256  #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2257  #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
2258  #define CAN_RDH0R_DATA5_Pos    (8U)
2259  #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2260  #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
2261  #define CAN_RDH0R_DATA6_Pos    (16U)
2262  #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2263  #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
2264  #define CAN_RDH0R_DATA7_Pos    (24U)
2265  #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2266  #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
2267  
2268  /*******************  Bit definition for CAN_RI1R register  *******************/
2269  #define CAN_RI1R_RTR_Pos       (1U)
2270  #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
2271  #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
2272  #define CAN_RI1R_IDE_Pos       (2U)
2273  #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
2274  #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
2275  #define CAN_RI1R_EXID_Pos      (3U)
2276  #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2277  #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
2278  #define CAN_RI1R_STID_Pos      (21U)
2279  #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
2280  #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2281  
2282  /*******************  Bit definition for CAN_RDT1R register  ******************/
2283  #define CAN_RDT1R_DLC_Pos      (0U)
2284  #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
2285  #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
2286  #define CAN_RDT1R_FMI_Pos      (8U)
2287  #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
2288  #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
2289  #define CAN_RDT1R_TIME_Pos     (16U)
2290  #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2291  #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
2292  
2293  /*******************  Bit definition for CAN_RDL1R register  ******************/
2294  #define CAN_RDL1R_DATA0_Pos    (0U)
2295  #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2296  #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
2297  #define CAN_RDL1R_DATA1_Pos    (8U)
2298  #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2299  #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
2300  #define CAN_RDL1R_DATA2_Pos    (16U)
2301  #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2302  #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
2303  #define CAN_RDL1R_DATA3_Pos    (24U)
2304  #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2305  #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
2306  
2307  /*******************  Bit definition for CAN_RDH1R register  ******************/
2308  #define CAN_RDH1R_DATA4_Pos    (0U)
2309  #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2310  #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
2311  #define CAN_RDH1R_DATA5_Pos    (8U)
2312  #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2313  #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
2314  #define CAN_RDH1R_DATA6_Pos    (16U)
2315  #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2316  #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
2317  #define CAN_RDH1R_DATA7_Pos    (24U)
2318  #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2319  #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
2320  
2321  /*!<CAN filter registers */
2322  /*******************  Bit definition for CAN_FMR register  ********************/
2323  #define CAN_FMR_FINIT_Pos      (0U)
2324  #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
2325  #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
2326  #define CAN_FMR_CAN2SB_Pos     (8U)
2327  #define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
2328  #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
2329  
2330  /*******************  Bit definition for CAN_FM1R register  *******************/
2331  #define CAN_FM1R_FBM_Pos       (0U)
2332  #define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
2333  #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
2334  #define CAN_FM1R_FBM0_Pos      (0U)
2335  #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
2336  #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
2337  #define CAN_FM1R_FBM1_Pos      (1U)
2338  #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
2339  #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
2340  #define CAN_FM1R_FBM2_Pos      (2U)
2341  #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
2342  #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
2343  #define CAN_FM1R_FBM3_Pos      (3U)
2344  #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
2345  #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
2346  #define CAN_FM1R_FBM4_Pos      (4U)
2347  #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
2348  #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
2349  #define CAN_FM1R_FBM5_Pos      (5U)
2350  #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
2351  #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
2352  #define CAN_FM1R_FBM6_Pos      (6U)
2353  #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
2354  #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
2355  #define CAN_FM1R_FBM7_Pos      (7U)
2356  #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
2357  #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
2358  #define CAN_FM1R_FBM8_Pos      (8U)
2359  #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
2360  #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
2361  #define CAN_FM1R_FBM9_Pos      (9U)
2362  #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
2363  #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
2364  #define CAN_FM1R_FBM10_Pos     (10U)
2365  #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
2366  #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
2367  #define CAN_FM1R_FBM11_Pos     (11U)
2368  #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
2369  #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
2370  #define CAN_FM1R_FBM12_Pos     (12U)
2371  #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
2372  #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
2373  #define CAN_FM1R_FBM13_Pos     (13U)
2374  #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
2375  #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
2376  #define CAN_FM1R_FBM14_Pos     (14U)
2377  #define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
2378  #define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
2379  #define CAN_FM1R_FBM15_Pos     (15U)
2380  #define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
2381  #define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
2382  #define CAN_FM1R_FBM16_Pos     (16U)
2383  #define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
2384  #define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
2385  #define CAN_FM1R_FBM17_Pos     (17U)
2386  #define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
2387  #define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
2388  #define CAN_FM1R_FBM18_Pos     (18U)
2389  #define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
2390  #define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
2391  #define CAN_FM1R_FBM19_Pos     (19U)
2392  #define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
2393  #define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
2394  #define CAN_FM1R_FBM20_Pos     (20U)
2395  #define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
2396  #define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
2397  #define CAN_FM1R_FBM21_Pos     (21U)
2398  #define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
2399  #define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
2400  #define CAN_FM1R_FBM22_Pos     (22U)
2401  #define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
2402  #define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
2403  #define CAN_FM1R_FBM23_Pos     (23U)
2404  #define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
2405  #define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
2406  #define CAN_FM1R_FBM24_Pos     (24U)
2407  #define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
2408  #define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
2409  #define CAN_FM1R_FBM25_Pos     (25U)
2410  #define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
2411  #define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
2412  #define CAN_FM1R_FBM26_Pos     (26U)
2413  #define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
2414  #define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
2415  #define CAN_FM1R_FBM27_Pos     (27U)
2416  #define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
2417  #define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
2418  
2419  /*******************  Bit definition for CAN_FS1R register  *******************/
2420  #define CAN_FS1R_FSC_Pos       (0U)
2421  #define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
2422  #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
2423  #define CAN_FS1R_FSC0_Pos      (0U)
2424  #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
2425  #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
2426  #define CAN_FS1R_FSC1_Pos      (1U)
2427  #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
2428  #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
2429  #define CAN_FS1R_FSC2_Pos      (2U)
2430  #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
2431  #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
2432  #define CAN_FS1R_FSC3_Pos      (3U)
2433  #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
2434  #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
2435  #define CAN_FS1R_FSC4_Pos      (4U)
2436  #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
2437  #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
2438  #define CAN_FS1R_FSC5_Pos      (5U)
2439  #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
2440  #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
2441  #define CAN_FS1R_FSC6_Pos      (6U)
2442  #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
2443  #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
2444  #define CAN_FS1R_FSC7_Pos      (7U)
2445  #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
2446  #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
2447  #define CAN_FS1R_FSC8_Pos      (8U)
2448  #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
2449  #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
2450  #define CAN_FS1R_FSC9_Pos      (9U)
2451  #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
2452  #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
2453  #define CAN_FS1R_FSC10_Pos     (10U)
2454  #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
2455  #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
2456  #define CAN_FS1R_FSC11_Pos     (11U)
2457  #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
2458  #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
2459  #define CAN_FS1R_FSC12_Pos     (12U)
2460  #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
2461  #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
2462  #define CAN_FS1R_FSC13_Pos     (13U)
2463  #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
2464  #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
2465  #define CAN_FS1R_FSC14_Pos     (14U)
2466  #define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
2467  #define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
2468  #define CAN_FS1R_FSC15_Pos     (15U)
2469  #define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
2470  #define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
2471  #define CAN_FS1R_FSC16_Pos     (16U)
2472  #define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
2473  #define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
2474  #define CAN_FS1R_FSC17_Pos     (17U)
2475  #define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
2476  #define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
2477  #define CAN_FS1R_FSC18_Pos     (18U)
2478  #define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
2479  #define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
2480  #define CAN_FS1R_FSC19_Pos     (19U)
2481  #define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
2482  #define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
2483  #define CAN_FS1R_FSC20_Pos     (20U)
2484  #define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
2485  #define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
2486  #define CAN_FS1R_FSC21_Pos     (21U)
2487  #define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
2488  #define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
2489  #define CAN_FS1R_FSC22_Pos     (22U)
2490  #define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
2491  #define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
2492  #define CAN_FS1R_FSC23_Pos     (23U)
2493  #define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
2494  #define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
2495  #define CAN_FS1R_FSC24_Pos     (24U)
2496  #define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
2497  #define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
2498  #define CAN_FS1R_FSC25_Pos     (25U)
2499  #define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
2500  #define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
2501  #define CAN_FS1R_FSC26_Pos     (26U)
2502  #define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
2503  #define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
2504  #define CAN_FS1R_FSC27_Pos     (27U)
2505  #define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
2506  #define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
2507  
2508  /******************  Bit definition for CAN_FFA1R register  *******************/
2509  #define CAN_FFA1R_FFA_Pos      (0U)
2510  #define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
2511  #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
2512  #define CAN_FFA1R_FFA0_Pos     (0U)
2513  #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
2514  #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
2515  #define CAN_FFA1R_FFA1_Pos     (1U)
2516  #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
2517  #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
2518  #define CAN_FFA1R_FFA2_Pos     (2U)
2519  #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
2520  #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
2521  #define CAN_FFA1R_FFA3_Pos     (3U)
2522  #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
2523  #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
2524  #define CAN_FFA1R_FFA4_Pos     (4U)
2525  #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
2526  #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
2527  #define CAN_FFA1R_FFA5_Pos     (5U)
2528  #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
2529  #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
2530  #define CAN_FFA1R_FFA6_Pos     (6U)
2531  #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
2532  #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
2533  #define CAN_FFA1R_FFA7_Pos     (7U)
2534  #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
2535  #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
2536  #define CAN_FFA1R_FFA8_Pos     (8U)
2537  #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
2538  #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
2539  #define CAN_FFA1R_FFA9_Pos     (9U)
2540  #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
2541  #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
2542  #define CAN_FFA1R_FFA10_Pos    (10U)
2543  #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
2544  #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
2545  #define CAN_FFA1R_FFA11_Pos    (11U)
2546  #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
2547  #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
2548  #define CAN_FFA1R_FFA12_Pos    (12U)
2549  #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
2550  #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
2551  #define CAN_FFA1R_FFA13_Pos    (13U)
2552  #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
2553  #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
2554  #define CAN_FFA1R_FFA14_Pos    (14U)
2555  #define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
2556  #define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
2557  #define CAN_FFA1R_FFA15_Pos    (15U)
2558  #define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
2559  #define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
2560  #define CAN_FFA1R_FFA16_Pos    (16U)
2561  #define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
2562  #define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
2563  #define CAN_FFA1R_FFA17_Pos    (17U)
2564  #define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
2565  #define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
2566  #define CAN_FFA1R_FFA18_Pos    (18U)
2567  #define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
2568  #define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
2569  #define CAN_FFA1R_FFA19_Pos    (19U)
2570  #define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
2571  #define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
2572  #define CAN_FFA1R_FFA20_Pos    (20U)
2573  #define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
2574  #define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
2575  #define CAN_FFA1R_FFA21_Pos    (21U)
2576  #define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
2577  #define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
2578  #define CAN_FFA1R_FFA22_Pos    (22U)
2579  #define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
2580  #define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
2581  #define CAN_FFA1R_FFA23_Pos    (23U)
2582  #define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
2583  #define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
2584  #define CAN_FFA1R_FFA24_Pos    (24U)
2585  #define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
2586  #define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
2587  #define CAN_FFA1R_FFA25_Pos    (25U)
2588  #define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
2589  #define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
2590  #define CAN_FFA1R_FFA26_Pos    (26U)
2591  #define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
2592  #define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
2593  #define CAN_FFA1R_FFA27_Pos    (27U)
2594  #define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
2595  #define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
2596  
2597  /*******************  Bit definition for CAN_FA1R register  *******************/
2598  #define CAN_FA1R_FACT_Pos      (0U)
2599  #define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
2600  #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
2601  #define CAN_FA1R_FACT0_Pos     (0U)
2602  #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
2603  #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
2604  #define CAN_FA1R_FACT1_Pos     (1U)
2605  #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
2606  #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
2607  #define CAN_FA1R_FACT2_Pos     (2U)
2608  #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
2609  #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
2610  #define CAN_FA1R_FACT3_Pos     (3U)
2611  #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
2612  #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
2613  #define CAN_FA1R_FACT4_Pos     (4U)
2614  #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
2615  #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
2616  #define CAN_FA1R_FACT5_Pos     (5U)
2617  #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
2618  #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
2619  #define CAN_FA1R_FACT6_Pos     (6U)
2620  #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
2621  #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
2622  #define CAN_FA1R_FACT7_Pos     (7U)
2623  #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
2624  #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
2625  #define CAN_FA1R_FACT8_Pos     (8U)
2626  #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
2627  #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
2628  #define CAN_FA1R_FACT9_Pos     (9U)
2629  #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
2630  #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
2631  #define CAN_FA1R_FACT10_Pos    (10U)
2632  #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
2633  #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
2634  #define CAN_FA1R_FACT11_Pos    (11U)
2635  #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
2636  #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
2637  #define CAN_FA1R_FACT12_Pos    (12U)
2638  #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
2639  #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
2640  #define CAN_FA1R_FACT13_Pos    (13U)
2641  #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
2642  #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
2643  #define CAN_FA1R_FACT14_Pos    (14U)
2644  #define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
2645  #define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
2646  #define CAN_FA1R_FACT15_Pos    (15U)
2647  #define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
2648  #define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
2649  #define CAN_FA1R_FACT16_Pos    (16U)
2650  #define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
2651  #define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
2652  #define CAN_FA1R_FACT17_Pos    (17U)
2653  #define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
2654  #define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
2655  #define CAN_FA1R_FACT18_Pos    (18U)
2656  #define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
2657  #define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
2658  #define CAN_FA1R_FACT19_Pos    (19U)
2659  #define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
2660  #define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
2661  #define CAN_FA1R_FACT20_Pos    (20U)
2662  #define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
2663  #define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
2664  #define CAN_FA1R_FACT21_Pos    (21U)
2665  #define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
2666  #define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
2667  #define CAN_FA1R_FACT22_Pos    (22U)
2668  #define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
2669  #define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
2670  #define CAN_FA1R_FACT23_Pos    (23U)
2671  #define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
2672  #define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
2673  #define CAN_FA1R_FACT24_Pos    (24U)
2674  #define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
2675  #define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
2676  #define CAN_FA1R_FACT25_Pos    (25U)
2677  #define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
2678  #define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
2679  #define CAN_FA1R_FACT26_Pos    (26U)
2680  #define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
2681  #define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
2682  #define CAN_FA1R_FACT27_Pos    (27U)
2683  #define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
2684  #define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
2685  
2686  
2687  /*******************  Bit definition for CAN_F0R1 register  *******************/
2688  #define CAN_F0R1_FB0_Pos       (0U)
2689  #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
2690  #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
2691  #define CAN_F0R1_FB1_Pos       (1U)
2692  #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
2693  #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
2694  #define CAN_F0R1_FB2_Pos       (2U)
2695  #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
2696  #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
2697  #define CAN_F0R1_FB3_Pos       (3U)
2698  #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
2699  #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
2700  #define CAN_F0R1_FB4_Pos       (4U)
2701  #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
2702  #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
2703  #define CAN_F0R1_FB5_Pos       (5U)
2704  #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
2705  #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
2706  #define CAN_F0R1_FB6_Pos       (6U)
2707  #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
2708  #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
2709  #define CAN_F0R1_FB7_Pos       (7U)
2710  #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
2711  #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
2712  #define CAN_F0R1_FB8_Pos       (8U)
2713  #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
2714  #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
2715  #define CAN_F0R1_FB9_Pos       (9U)
2716  #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
2717  #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
2718  #define CAN_F0R1_FB10_Pos      (10U)
2719  #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
2720  #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
2721  #define CAN_F0R1_FB11_Pos      (11U)
2722  #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
2723  #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
2724  #define CAN_F0R1_FB12_Pos      (12U)
2725  #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
2726  #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
2727  #define CAN_F0R1_FB13_Pos      (13U)
2728  #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
2729  #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
2730  #define CAN_F0R1_FB14_Pos      (14U)
2731  #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
2732  #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
2733  #define CAN_F0R1_FB15_Pos      (15U)
2734  #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
2735  #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
2736  #define CAN_F0R1_FB16_Pos      (16U)
2737  #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
2738  #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2739  #define CAN_F0R1_FB17_Pos      (17U)
2740  #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
2741  #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2742  #define CAN_F0R1_FB18_Pos      (18U)
2743  #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
2744  #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2745  #define CAN_F0R1_FB19_Pos      (19U)
2746  #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
2747  #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2748  #define CAN_F0R1_FB20_Pos      (20U)
2749  #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
2750  #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2751  #define CAN_F0R1_FB21_Pos      (21U)
2752  #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
2753  #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2754  #define CAN_F0R1_FB22_Pos      (22U)
2755  #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
2756  #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2757  #define CAN_F0R1_FB23_Pos      (23U)
2758  #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
2759  #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2760  #define CAN_F0R1_FB24_Pos      (24U)
2761  #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
2762  #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2763  #define CAN_F0R1_FB25_Pos      (25U)
2764  #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
2765  #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2766  #define CAN_F0R1_FB26_Pos      (26U)
2767  #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
2768  #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2769  #define CAN_F0R1_FB27_Pos      (27U)
2770  #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
2771  #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2772  #define CAN_F0R1_FB28_Pos      (28U)
2773  #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
2774  #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2775  #define CAN_F0R1_FB29_Pos      (29U)
2776  #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
2777  #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
2778  #define CAN_F0R1_FB30_Pos      (30U)
2779  #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
2780  #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
2781  #define CAN_F0R1_FB31_Pos      (31U)
2782  #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
2783  #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
2784  
2785  /*******************  Bit definition for CAN_F1R1 register  *******************/
2786  #define CAN_F1R1_FB0_Pos       (0U)
2787  #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
2788  #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
2789  #define CAN_F1R1_FB1_Pos       (1U)
2790  #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
2791  #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
2792  #define CAN_F1R1_FB2_Pos       (2U)
2793  #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
2794  #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
2795  #define CAN_F1R1_FB3_Pos       (3U)
2796  #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
2797  #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
2798  #define CAN_F1R1_FB4_Pos       (4U)
2799  #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
2800  #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
2801  #define CAN_F1R1_FB5_Pos       (5U)
2802  #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
2803  #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
2804  #define CAN_F1R1_FB6_Pos       (6U)
2805  #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
2806  #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
2807  #define CAN_F1R1_FB7_Pos       (7U)
2808  #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
2809  #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
2810  #define CAN_F1R1_FB8_Pos       (8U)
2811  #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
2812  #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
2813  #define CAN_F1R1_FB9_Pos       (9U)
2814  #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
2815  #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
2816  #define CAN_F1R1_FB10_Pos      (10U)
2817  #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
2818  #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
2819  #define CAN_F1R1_FB11_Pos      (11U)
2820  #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
2821  #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
2822  #define CAN_F1R1_FB12_Pos      (12U)
2823  #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
2824  #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
2825  #define CAN_F1R1_FB13_Pos      (13U)
2826  #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
2827  #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
2828  #define CAN_F1R1_FB14_Pos      (14U)
2829  #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
2830  #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
2831  #define CAN_F1R1_FB15_Pos      (15U)
2832  #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
2833  #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
2834  #define CAN_F1R1_FB16_Pos      (16U)
2835  #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
2836  #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
2837  #define CAN_F1R1_FB17_Pos      (17U)
2838  #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
2839  #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
2840  #define CAN_F1R1_FB18_Pos      (18U)
2841  #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
2842  #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
2843  #define CAN_F1R1_FB19_Pos      (19U)
2844  #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
2845  #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
2846  #define CAN_F1R1_FB20_Pos      (20U)
2847  #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
2848  #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
2849  #define CAN_F1R1_FB21_Pos      (21U)
2850  #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
2851  #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
2852  #define CAN_F1R1_FB22_Pos      (22U)
2853  #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
2854  #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
2855  #define CAN_F1R1_FB23_Pos      (23U)
2856  #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
2857  #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
2858  #define CAN_F1R1_FB24_Pos      (24U)
2859  #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
2860  #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
2861  #define CAN_F1R1_FB25_Pos      (25U)
2862  #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
2863  #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
2864  #define CAN_F1R1_FB26_Pos      (26U)
2865  #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
2866  #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
2867  #define CAN_F1R1_FB27_Pos      (27U)
2868  #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
2869  #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
2870  #define CAN_F1R1_FB28_Pos      (28U)
2871  #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
2872  #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
2873  #define CAN_F1R1_FB29_Pos      (29U)
2874  #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
2875  #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
2876  #define CAN_F1R1_FB30_Pos      (30U)
2877  #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
2878  #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
2879  #define CAN_F1R1_FB31_Pos      (31U)
2880  #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
2881  #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
2882  
2883  /*******************  Bit definition for CAN_F2R1 register  *******************/
2884  #define CAN_F2R1_FB0_Pos       (0U)
2885  #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
2886  #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
2887  #define CAN_F2R1_FB1_Pos       (1U)
2888  #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
2889  #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
2890  #define CAN_F2R1_FB2_Pos       (2U)
2891  #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
2892  #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
2893  #define CAN_F2R1_FB3_Pos       (3U)
2894  #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
2895  #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
2896  #define CAN_F2R1_FB4_Pos       (4U)
2897  #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
2898  #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
2899  #define CAN_F2R1_FB5_Pos       (5U)
2900  #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
2901  #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
2902  #define CAN_F2R1_FB6_Pos       (6U)
2903  #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
2904  #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
2905  #define CAN_F2R1_FB7_Pos       (7U)
2906  #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
2907  #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
2908  #define CAN_F2R1_FB8_Pos       (8U)
2909  #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
2910  #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
2911  #define CAN_F2R1_FB9_Pos       (9U)
2912  #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
2913  #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
2914  #define CAN_F2R1_FB10_Pos      (10U)
2915  #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
2916  #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
2917  #define CAN_F2R1_FB11_Pos      (11U)
2918  #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
2919  #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
2920  #define CAN_F2R1_FB12_Pos      (12U)
2921  #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
2922  #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
2923  #define CAN_F2R1_FB13_Pos      (13U)
2924  #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
2925  #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
2926  #define CAN_F2R1_FB14_Pos      (14U)
2927  #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
2928  #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
2929  #define CAN_F2R1_FB15_Pos      (15U)
2930  #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
2931  #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
2932  #define CAN_F2R1_FB16_Pos      (16U)
2933  #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
2934  #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
2935  #define CAN_F2R1_FB17_Pos      (17U)
2936  #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
2937  #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
2938  #define CAN_F2R1_FB18_Pos      (18U)
2939  #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
2940  #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
2941  #define CAN_F2R1_FB19_Pos      (19U)
2942  #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
2943  #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
2944  #define CAN_F2R1_FB20_Pos      (20U)
2945  #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
2946  #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
2947  #define CAN_F2R1_FB21_Pos      (21U)
2948  #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
2949  #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
2950  #define CAN_F2R1_FB22_Pos      (22U)
2951  #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
2952  #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
2953  #define CAN_F2R1_FB23_Pos      (23U)
2954  #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
2955  #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
2956  #define CAN_F2R1_FB24_Pos      (24U)
2957  #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
2958  #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
2959  #define CAN_F2R1_FB25_Pos      (25U)
2960  #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
2961  #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
2962  #define CAN_F2R1_FB26_Pos      (26U)
2963  #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
2964  #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
2965  #define CAN_F2R1_FB27_Pos      (27U)
2966  #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
2967  #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
2968  #define CAN_F2R1_FB28_Pos      (28U)
2969  #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
2970  #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
2971  #define CAN_F2R1_FB29_Pos      (29U)
2972  #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
2973  #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
2974  #define CAN_F2R1_FB30_Pos      (30U)
2975  #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
2976  #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
2977  #define CAN_F2R1_FB31_Pos      (31U)
2978  #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
2979  #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
2980  
2981  /*******************  Bit definition for CAN_F3R1 register  *******************/
2982  #define CAN_F3R1_FB0_Pos       (0U)
2983  #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
2984  #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
2985  #define CAN_F3R1_FB1_Pos       (1U)
2986  #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
2987  #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
2988  #define CAN_F3R1_FB2_Pos       (2U)
2989  #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
2990  #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
2991  #define CAN_F3R1_FB3_Pos       (3U)
2992  #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
2993  #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
2994  #define CAN_F3R1_FB4_Pos       (4U)
2995  #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
2996  #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
2997  #define CAN_F3R1_FB5_Pos       (5U)
2998  #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
2999  #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3000  #define CAN_F3R1_FB6_Pos       (6U)
3001  #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
3002  #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3003  #define CAN_F3R1_FB7_Pos       (7U)
3004  #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
3005  #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3006  #define CAN_F3R1_FB8_Pos       (8U)
3007  #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
3008  #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3009  #define CAN_F3R1_FB9_Pos       (9U)
3010  #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3011  #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3012  #define CAN_F3R1_FB10_Pos      (10U)
3013  #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3014  #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3015  #define CAN_F3R1_FB11_Pos      (11U)
3016  #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3017  #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3018  #define CAN_F3R1_FB12_Pos      (12U)
3019  #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3020  #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3021  #define CAN_F3R1_FB13_Pos      (13U)
3022  #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3023  #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3024  #define CAN_F3R1_FB14_Pos      (14U)
3025  #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3026  #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3027  #define CAN_F3R1_FB15_Pos      (15U)
3028  #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3029  #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3030  #define CAN_F3R1_FB16_Pos      (16U)
3031  #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3032  #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3033  #define CAN_F3R1_FB17_Pos      (17U)
3034  #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3035  #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3036  #define CAN_F3R1_FB18_Pos      (18U)
3037  #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3038  #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3039  #define CAN_F3R1_FB19_Pos      (19U)
3040  #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3041  #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3042  #define CAN_F3R1_FB20_Pos      (20U)
3043  #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3044  #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3045  #define CAN_F3R1_FB21_Pos      (21U)
3046  #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3047  #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3048  #define CAN_F3R1_FB22_Pos      (22U)
3049  #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3050  #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3051  #define CAN_F3R1_FB23_Pos      (23U)
3052  #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3053  #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3054  #define CAN_F3R1_FB24_Pos      (24U)
3055  #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3056  #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3057  #define CAN_F3R1_FB25_Pos      (25U)
3058  #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3059  #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3060  #define CAN_F3R1_FB26_Pos      (26U)
3061  #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3062  #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3063  #define CAN_F3R1_FB27_Pos      (27U)
3064  #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3065  #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3066  #define CAN_F3R1_FB28_Pos      (28U)
3067  #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3068  #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3069  #define CAN_F3R1_FB29_Pos      (29U)
3070  #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3071  #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3072  #define CAN_F3R1_FB30_Pos      (30U)
3073  #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3074  #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3075  #define CAN_F3R1_FB31_Pos      (31U)
3076  #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3077  #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3078  
3079  /*******************  Bit definition for CAN_F4R1 register  *******************/
3080  #define CAN_F4R1_FB0_Pos       (0U)
3081  #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3082  #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3083  #define CAN_F4R1_FB1_Pos       (1U)
3084  #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3085  #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3086  #define CAN_F4R1_FB2_Pos       (2U)
3087  #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3088  #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3089  #define CAN_F4R1_FB3_Pos       (3U)
3090  #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3091  #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3092  #define CAN_F4R1_FB4_Pos       (4U)
3093  #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3094  #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3095  #define CAN_F4R1_FB5_Pos       (5U)
3096  #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3097  #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3098  #define CAN_F4R1_FB6_Pos       (6U)
3099  #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3100  #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3101  #define CAN_F4R1_FB7_Pos       (7U)
3102  #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3103  #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3104  #define CAN_F4R1_FB8_Pos       (8U)
3105  #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3106  #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3107  #define CAN_F4R1_FB9_Pos       (9U)
3108  #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3109  #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3110  #define CAN_F4R1_FB10_Pos      (10U)
3111  #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3112  #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3113  #define CAN_F4R1_FB11_Pos      (11U)
3114  #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3115  #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3116  #define CAN_F4R1_FB12_Pos      (12U)
3117  #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3118  #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3119  #define CAN_F4R1_FB13_Pos      (13U)
3120  #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3121  #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3122  #define CAN_F4R1_FB14_Pos      (14U)
3123  #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3124  #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3125  #define CAN_F4R1_FB15_Pos      (15U)
3126  #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3127  #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3128  #define CAN_F4R1_FB16_Pos      (16U)
3129  #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3130  #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3131  #define CAN_F4R1_FB17_Pos      (17U)
3132  #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3133  #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3134  #define CAN_F4R1_FB18_Pos      (18U)
3135  #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3136  #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3137  #define CAN_F4R1_FB19_Pos      (19U)
3138  #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3139  #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3140  #define CAN_F4R1_FB20_Pos      (20U)
3141  #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3142  #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3143  #define CAN_F4R1_FB21_Pos      (21U)
3144  #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3145  #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3146  #define CAN_F4R1_FB22_Pos      (22U)
3147  #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3148  #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3149  #define CAN_F4R1_FB23_Pos      (23U)
3150  #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3151  #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3152  #define CAN_F4R1_FB24_Pos      (24U)
3153  #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3154  #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3155  #define CAN_F4R1_FB25_Pos      (25U)
3156  #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3157  #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3158  #define CAN_F4R1_FB26_Pos      (26U)
3159  #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3160  #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3161  #define CAN_F4R1_FB27_Pos      (27U)
3162  #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
3163  #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3164  #define CAN_F4R1_FB28_Pos      (28U)
3165  #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
3166  #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3167  #define CAN_F4R1_FB29_Pos      (29U)
3168  #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
3169  #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3170  #define CAN_F4R1_FB30_Pos      (30U)
3171  #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
3172  #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3173  #define CAN_F4R1_FB31_Pos      (31U)
3174  #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
3175  #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3176  
3177  /*******************  Bit definition for CAN_F5R1 register  *******************/
3178  #define CAN_F5R1_FB0_Pos       (0U)
3179  #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
3180  #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3181  #define CAN_F5R1_FB1_Pos       (1U)
3182  #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
3183  #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3184  #define CAN_F5R1_FB2_Pos       (2U)
3185  #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
3186  #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3187  #define CAN_F5R1_FB3_Pos       (3U)
3188  #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
3189  #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3190  #define CAN_F5R1_FB4_Pos       (4U)
3191  #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
3192  #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3193  #define CAN_F5R1_FB5_Pos       (5U)
3194  #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
3195  #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3196  #define CAN_F5R1_FB6_Pos       (6U)
3197  #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
3198  #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3199  #define CAN_F5R1_FB7_Pos       (7U)
3200  #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
3201  #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3202  #define CAN_F5R1_FB8_Pos       (8U)
3203  #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
3204  #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3205  #define CAN_F5R1_FB9_Pos       (9U)
3206  #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
3207  #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3208  #define CAN_F5R1_FB10_Pos      (10U)
3209  #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
3210  #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3211  #define CAN_F5R1_FB11_Pos      (11U)
3212  #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
3213  #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3214  #define CAN_F5R1_FB12_Pos      (12U)
3215  #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
3216  #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3217  #define CAN_F5R1_FB13_Pos      (13U)
3218  #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
3219  #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3220  #define CAN_F5R1_FB14_Pos      (14U)
3221  #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
3222  #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3223  #define CAN_F5R1_FB15_Pos      (15U)
3224  #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
3225  #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3226  #define CAN_F5R1_FB16_Pos      (16U)
3227  #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
3228  #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3229  #define CAN_F5R1_FB17_Pos      (17U)
3230  #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
3231  #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3232  #define CAN_F5R1_FB18_Pos      (18U)
3233  #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
3234  #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3235  #define CAN_F5R1_FB19_Pos      (19U)
3236  #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
3237  #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3238  #define CAN_F5R1_FB20_Pos      (20U)
3239  #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
3240  #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3241  #define CAN_F5R1_FB21_Pos      (21U)
3242  #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
3243  #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3244  #define CAN_F5R1_FB22_Pos      (22U)
3245  #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
3246  #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3247  #define CAN_F5R1_FB23_Pos      (23U)
3248  #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
3249  #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3250  #define CAN_F5R1_FB24_Pos      (24U)
3251  #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
3252  #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3253  #define CAN_F5R1_FB25_Pos      (25U)
3254  #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
3255  #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3256  #define CAN_F5R1_FB26_Pos      (26U)
3257  #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
3258  #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3259  #define CAN_F5R1_FB27_Pos      (27U)
3260  #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
3261  #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3262  #define CAN_F5R1_FB28_Pos      (28U)
3263  #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
3264  #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3265  #define CAN_F5R1_FB29_Pos      (29U)
3266  #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
3267  #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3268  #define CAN_F5R1_FB30_Pos      (30U)
3269  #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
3270  #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3271  #define CAN_F5R1_FB31_Pos      (31U)
3272  #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
3273  #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3274  
3275  /*******************  Bit definition for CAN_F6R1 register  *******************/
3276  #define CAN_F6R1_FB0_Pos       (0U)
3277  #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
3278  #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3279  #define CAN_F6R1_FB1_Pos       (1U)
3280  #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
3281  #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3282  #define CAN_F6R1_FB2_Pos       (2U)
3283  #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
3284  #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3285  #define CAN_F6R1_FB3_Pos       (3U)
3286  #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
3287  #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3288  #define CAN_F6R1_FB4_Pos       (4U)
3289  #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
3290  #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3291  #define CAN_F6R1_FB5_Pos       (5U)
3292  #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
3293  #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3294  #define CAN_F6R1_FB6_Pos       (6U)
3295  #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
3296  #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3297  #define CAN_F6R1_FB7_Pos       (7U)
3298  #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
3299  #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3300  #define CAN_F6R1_FB8_Pos       (8U)
3301  #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
3302  #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3303  #define CAN_F6R1_FB9_Pos       (9U)
3304  #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
3305  #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3306  #define CAN_F6R1_FB10_Pos      (10U)
3307  #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
3308  #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3309  #define CAN_F6R1_FB11_Pos      (11U)
3310  #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
3311  #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3312  #define CAN_F6R1_FB12_Pos      (12U)
3313  #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
3314  #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3315  #define CAN_F6R1_FB13_Pos      (13U)
3316  #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
3317  #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3318  #define CAN_F6R1_FB14_Pos      (14U)
3319  #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
3320  #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3321  #define CAN_F6R1_FB15_Pos      (15U)
3322  #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
3323  #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3324  #define CAN_F6R1_FB16_Pos      (16U)
3325  #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
3326  #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3327  #define CAN_F6R1_FB17_Pos      (17U)
3328  #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
3329  #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3330  #define CAN_F6R1_FB18_Pos      (18U)
3331  #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
3332  #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3333  #define CAN_F6R1_FB19_Pos      (19U)
3334  #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
3335  #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3336  #define CAN_F6R1_FB20_Pos      (20U)
3337  #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
3338  #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3339  #define CAN_F6R1_FB21_Pos      (21U)
3340  #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
3341  #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3342  #define CAN_F6R1_FB22_Pos      (22U)
3343  #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
3344  #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3345  #define CAN_F6R1_FB23_Pos      (23U)
3346  #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
3347  #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3348  #define CAN_F6R1_FB24_Pos      (24U)
3349  #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
3350  #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3351  #define CAN_F6R1_FB25_Pos      (25U)
3352  #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
3353  #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3354  #define CAN_F6R1_FB26_Pos      (26U)
3355  #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
3356  #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3357  #define CAN_F6R1_FB27_Pos      (27U)
3358  #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
3359  #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3360  #define CAN_F6R1_FB28_Pos      (28U)
3361  #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
3362  #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3363  #define CAN_F6R1_FB29_Pos      (29U)
3364  #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
3365  #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3366  #define CAN_F6R1_FB30_Pos      (30U)
3367  #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
3368  #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3369  #define CAN_F6R1_FB31_Pos      (31U)
3370  #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
3371  #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3372  
3373  /*******************  Bit definition for CAN_F7R1 register  *******************/
3374  #define CAN_F7R1_FB0_Pos       (0U)
3375  #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
3376  #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3377  #define CAN_F7R1_FB1_Pos       (1U)
3378  #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
3379  #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3380  #define CAN_F7R1_FB2_Pos       (2U)
3381  #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
3382  #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3383  #define CAN_F7R1_FB3_Pos       (3U)
3384  #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
3385  #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3386  #define CAN_F7R1_FB4_Pos       (4U)
3387  #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
3388  #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3389  #define CAN_F7R1_FB5_Pos       (5U)
3390  #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
3391  #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3392  #define CAN_F7R1_FB6_Pos       (6U)
3393  #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
3394  #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3395  #define CAN_F7R1_FB7_Pos       (7U)
3396  #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
3397  #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3398  #define CAN_F7R1_FB8_Pos       (8U)
3399  #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
3400  #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3401  #define CAN_F7R1_FB9_Pos       (9U)
3402  #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
3403  #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
3404  #define CAN_F7R1_FB10_Pos      (10U)
3405  #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
3406  #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
3407  #define CAN_F7R1_FB11_Pos      (11U)
3408  #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
3409  #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
3410  #define CAN_F7R1_FB12_Pos      (12U)
3411  #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
3412  #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
3413  #define CAN_F7R1_FB13_Pos      (13U)
3414  #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
3415  #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
3416  #define CAN_F7R1_FB14_Pos      (14U)
3417  #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
3418  #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
3419  #define CAN_F7R1_FB15_Pos      (15U)
3420  #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
3421  #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
3422  #define CAN_F7R1_FB16_Pos      (16U)
3423  #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
3424  #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
3425  #define CAN_F7R1_FB17_Pos      (17U)
3426  #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
3427  #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
3428  #define CAN_F7R1_FB18_Pos      (18U)
3429  #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
3430  #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
3431  #define CAN_F7R1_FB19_Pos      (19U)
3432  #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
3433  #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
3434  #define CAN_F7R1_FB20_Pos      (20U)
3435  #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
3436  #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
3437  #define CAN_F7R1_FB21_Pos      (21U)
3438  #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
3439  #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
3440  #define CAN_F7R1_FB22_Pos      (22U)
3441  #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
3442  #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
3443  #define CAN_F7R1_FB23_Pos      (23U)
3444  #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
3445  #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
3446  #define CAN_F7R1_FB24_Pos      (24U)
3447  #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
3448  #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
3449  #define CAN_F7R1_FB25_Pos      (25U)
3450  #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
3451  #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
3452  #define CAN_F7R1_FB26_Pos      (26U)
3453  #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
3454  #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
3455  #define CAN_F7R1_FB27_Pos      (27U)
3456  #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
3457  #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
3458  #define CAN_F7R1_FB28_Pos      (28U)
3459  #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
3460  #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
3461  #define CAN_F7R1_FB29_Pos      (29U)
3462  #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
3463  #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
3464  #define CAN_F7R1_FB30_Pos      (30U)
3465  #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
3466  #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
3467  #define CAN_F7R1_FB31_Pos      (31U)
3468  #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
3469  #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
3470  
3471  /*******************  Bit definition for CAN_F8R1 register  *******************/
3472  #define CAN_F8R1_FB0_Pos       (0U)
3473  #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
3474  #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
3475  #define CAN_F8R1_FB1_Pos       (1U)
3476  #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
3477  #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
3478  #define CAN_F8R1_FB2_Pos       (2U)
3479  #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
3480  #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
3481  #define CAN_F8R1_FB3_Pos       (3U)
3482  #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
3483  #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
3484  #define CAN_F8R1_FB4_Pos       (4U)
3485  #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
3486  #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
3487  #define CAN_F8R1_FB5_Pos       (5U)
3488  #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
3489  #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
3490  #define CAN_F8R1_FB6_Pos       (6U)
3491  #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
3492  #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
3493  #define CAN_F8R1_FB7_Pos       (7U)
3494  #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
3495  #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
3496  #define CAN_F8R1_FB8_Pos       (8U)
3497  #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
3498  #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
3499  #define CAN_F8R1_FB9_Pos       (9U)
3500  #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
3501  #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
3502  #define CAN_F8R1_FB10_Pos      (10U)
3503  #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
3504  #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
3505  #define CAN_F8R1_FB11_Pos      (11U)
3506  #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
3507  #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
3508  #define CAN_F8R1_FB12_Pos      (12U)
3509  #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
3510  #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
3511  #define CAN_F8R1_FB13_Pos      (13U)
3512  #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
3513  #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
3514  #define CAN_F8R1_FB14_Pos      (14U)
3515  #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
3516  #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
3517  #define CAN_F8R1_FB15_Pos      (15U)
3518  #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
3519  #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
3520  #define CAN_F8R1_FB16_Pos      (16U)
3521  #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
3522  #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
3523  #define CAN_F8R1_FB17_Pos      (17U)
3524  #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
3525  #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
3526  #define CAN_F8R1_FB18_Pos      (18U)
3527  #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
3528  #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
3529  #define CAN_F8R1_FB19_Pos      (19U)
3530  #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
3531  #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
3532  #define CAN_F8R1_FB20_Pos      (20U)
3533  #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
3534  #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
3535  #define CAN_F8R1_FB21_Pos      (21U)
3536  #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
3537  #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
3538  #define CAN_F8R1_FB22_Pos      (22U)
3539  #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
3540  #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
3541  #define CAN_F8R1_FB23_Pos      (23U)
3542  #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
3543  #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
3544  #define CAN_F8R1_FB24_Pos      (24U)
3545  #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
3546  #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
3547  #define CAN_F8R1_FB25_Pos      (25U)
3548  #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
3549  #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
3550  #define CAN_F8R1_FB26_Pos      (26U)
3551  #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
3552  #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
3553  #define CAN_F8R1_FB27_Pos      (27U)
3554  #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
3555  #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
3556  #define CAN_F8R1_FB28_Pos      (28U)
3557  #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
3558  #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
3559  #define CAN_F8R1_FB29_Pos      (29U)
3560  #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
3561  #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
3562  #define CAN_F8R1_FB30_Pos      (30U)
3563  #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
3564  #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
3565  #define CAN_F8R1_FB31_Pos      (31U)
3566  #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
3567  #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
3568  
3569  /*******************  Bit definition for CAN_F9R1 register  *******************/
3570  #define CAN_F9R1_FB0_Pos       (0U)
3571  #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
3572  #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
3573  #define CAN_F9R1_FB1_Pos       (1U)
3574  #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
3575  #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
3576  #define CAN_F9R1_FB2_Pos       (2U)
3577  #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
3578  #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
3579  #define CAN_F9R1_FB3_Pos       (3U)
3580  #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
3581  #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
3582  #define CAN_F9R1_FB4_Pos       (4U)
3583  #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
3584  #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
3585  #define CAN_F9R1_FB5_Pos       (5U)
3586  #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
3587  #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
3588  #define CAN_F9R1_FB6_Pos       (6U)
3589  #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
3590  #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
3591  #define CAN_F9R1_FB7_Pos       (7U)
3592  #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
3593  #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
3594  #define CAN_F9R1_FB8_Pos       (8U)
3595  #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
3596  #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
3597  #define CAN_F9R1_FB9_Pos       (9U)
3598  #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
3599  #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
3600  #define CAN_F9R1_FB10_Pos      (10U)
3601  #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
3602  #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
3603  #define CAN_F9R1_FB11_Pos      (11U)
3604  #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
3605  #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
3606  #define CAN_F9R1_FB12_Pos      (12U)
3607  #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
3608  #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
3609  #define CAN_F9R1_FB13_Pos      (13U)
3610  #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
3611  #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
3612  #define CAN_F9R1_FB14_Pos      (14U)
3613  #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
3614  #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
3615  #define CAN_F9R1_FB15_Pos      (15U)
3616  #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
3617  #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
3618  #define CAN_F9R1_FB16_Pos      (16U)
3619  #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
3620  #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
3621  #define CAN_F9R1_FB17_Pos      (17U)
3622  #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
3623  #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
3624  #define CAN_F9R1_FB18_Pos      (18U)
3625  #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
3626  #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
3627  #define CAN_F9R1_FB19_Pos      (19U)
3628  #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
3629  #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
3630  #define CAN_F9R1_FB20_Pos      (20U)
3631  #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
3632  #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
3633  #define CAN_F9R1_FB21_Pos      (21U)
3634  #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
3635  #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
3636  #define CAN_F9R1_FB22_Pos      (22U)
3637  #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
3638  #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
3639  #define CAN_F9R1_FB23_Pos      (23U)
3640  #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
3641  #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
3642  #define CAN_F9R1_FB24_Pos      (24U)
3643  #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
3644  #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
3645  #define CAN_F9R1_FB25_Pos      (25U)
3646  #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
3647  #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
3648  #define CAN_F9R1_FB26_Pos      (26U)
3649  #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
3650  #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
3651  #define CAN_F9R1_FB27_Pos      (27U)
3652  #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
3653  #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
3654  #define CAN_F9R1_FB28_Pos      (28U)
3655  #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
3656  #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
3657  #define CAN_F9R1_FB29_Pos      (29U)
3658  #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
3659  #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
3660  #define CAN_F9R1_FB30_Pos      (30U)
3661  #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
3662  #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
3663  #define CAN_F9R1_FB31_Pos      (31U)
3664  #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
3665  #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
3666  
3667  /*******************  Bit definition for CAN_F10R1 register  ******************/
3668  #define CAN_F10R1_FB0_Pos      (0U)
3669  #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
3670  #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
3671  #define CAN_F10R1_FB1_Pos      (1U)
3672  #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
3673  #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
3674  #define CAN_F10R1_FB2_Pos      (2U)
3675  #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
3676  #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
3677  #define CAN_F10R1_FB3_Pos      (3U)
3678  #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
3679  #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
3680  #define CAN_F10R1_FB4_Pos      (4U)
3681  #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
3682  #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
3683  #define CAN_F10R1_FB5_Pos      (5U)
3684  #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
3685  #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
3686  #define CAN_F10R1_FB6_Pos      (6U)
3687  #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
3688  #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
3689  #define CAN_F10R1_FB7_Pos      (7U)
3690  #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
3691  #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
3692  #define CAN_F10R1_FB8_Pos      (8U)
3693  #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
3694  #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
3695  #define CAN_F10R1_FB9_Pos      (9U)
3696  #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
3697  #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
3698  #define CAN_F10R1_FB10_Pos     (10U)
3699  #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
3700  #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
3701  #define CAN_F10R1_FB11_Pos     (11U)
3702  #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
3703  #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
3704  #define CAN_F10R1_FB12_Pos     (12U)
3705  #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
3706  #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
3707  #define CAN_F10R1_FB13_Pos     (13U)
3708  #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
3709  #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
3710  #define CAN_F10R1_FB14_Pos     (14U)
3711  #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
3712  #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
3713  #define CAN_F10R1_FB15_Pos     (15U)
3714  #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
3715  #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
3716  #define CAN_F10R1_FB16_Pos     (16U)
3717  #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
3718  #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
3719  #define CAN_F10R1_FB17_Pos     (17U)
3720  #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
3721  #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
3722  #define CAN_F10R1_FB18_Pos     (18U)
3723  #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
3724  #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
3725  #define CAN_F10R1_FB19_Pos     (19U)
3726  #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
3727  #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
3728  #define CAN_F10R1_FB20_Pos     (20U)
3729  #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
3730  #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
3731  #define CAN_F10R1_FB21_Pos     (21U)
3732  #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
3733  #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
3734  #define CAN_F10R1_FB22_Pos     (22U)
3735  #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
3736  #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3737  #define CAN_F10R1_FB23_Pos     (23U)
3738  #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
3739  #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3740  #define CAN_F10R1_FB24_Pos     (24U)
3741  #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
3742  #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3743  #define CAN_F10R1_FB25_Pos     (25U)
3744  #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
3745  #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3746  #define CAN_F10R1_FB26_Pos     (26U)
3747  #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
3748  #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3749  #define CAN_F10R1_FB27_Pos     (27U)
3750  #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
3751  #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3752  #define CAN_F10R1_FB28_Pos     (28U)
3753  #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
3754  #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3755  #define CAN_F10R1_FB29_Pos     (29U)
3756  #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
3757  #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3758  #define CAN_F10R1_FB30_Pos     (30U)
3759  #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
3760  #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3761  #define CAN_F10R1_FB31_Pos     (31U)
3762  #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
3763  #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3764  
3765  /*******************  Bit definition for CAN_F11R1 register  ******************/
3766  #define CAN_F11R1_FB0_Pos      (0U)
3767  #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
3768  #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3769  #define CAN_F11R1_FB1_Pos      (1U)
3770  #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
3771  #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3772  #define CAN_F11R1_FB2_Pos      (2U)
3773  #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
3774  #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3775  #define CAN_F11R1_FB3_Pos      (3U)
3776  #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
3777  #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
3778  #define CAN_F11R1_FB4_Pos      (4U)
3779  #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
3780  #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
3781  #define CAN_F11R1_FB5_Pos      (5U)
3782  #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
3783  #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
3784  #define CAN_F11R1_FB6_Pos      (6U)
3785  #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
3786  #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
3787  #define CAN_F11R1_FB7_Pos      (7U)
3788  #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
3789  #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
3790  #define CAN_F11R1_FB8_Pos      (8U)
3791  #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
3792  #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
3793  #define CAN_F11R1_FB9_Pos      (9U)
3794  #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
3795  #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
3796  #define CAN_F11R1_FB10_Pos     (10U)
3797  #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
3798  #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
3799  #define CAN_F11R1_FB11_Pos     (11U)
3800  #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
3801  #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
3802  #define CAN_F11R1_FB12_Pos     (12U)
3803  #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
3804  #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
3805  #define CAN_F11R1_FB13_Pos     (13U)
3806  #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
3807  #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
3808  #define CAN_F11R1_FB14_Pos     (14U)
3809  #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
3810  #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
3811  #define CAN_F11R1_FB15_Pos     (15U)
3812  #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
3813  #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
3814  #define CAN_F11R1_FB16_Pos     (16U)
3815  #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
3816  #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
3817  #define CAN_F11R1_FB17_Pos     (17U)
3818  #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
3819  #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
3820  #define CAN_F11R1_FB18_Pos     (18U)
3821  #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
3822  #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
3823  #define CAN_F11R1_FB19_Pos     (19U)
3824  #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
3825  #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
3826  #define CAN_F11R1_FB20_Pos     (20U)
3827  #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
3828  #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
3829  #define CAN_F11R1_FB21_Pos     (21U)
3830  #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
3831  #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
3832  #define CAN_F11R1_FB22_Pos     (22U)
3833  #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
3834  #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
3835  #define CAN_F11R1_FB23_Pos     (23U)
3836  #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
3837  #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
3838  #define CAN_F11R1_FB24_Pos     (24U)
3839  #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
3840  #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
3841  #define CAN_F11R1_FB25_Pos     (25U)
3842  #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
3843  #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
3844  #define CAN_F11R1_FB26_Pos     (26U)
3845  #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
3846  #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
3847  #define CAN_F11R1_FB27_Pos     (27U)
3848  #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
3849  #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
3850  #define CAN_F11R1_FB28_Pos     (28U)
3851  #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
3852  #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
3853  #define CAN_F11R1_FB29_Pos     (29U)
3854  #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
3855  #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
3856  #define CAN_F11R1_FB30_Pos     (30U)
3857  #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
3858  #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
3859  #define CAN_F11R1_FB31_Pos     (31U)
3860  #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
3861  #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
3862  
3863  /*******************  Bit definition for CAN_F12R1 register  ******************/
3864  #define CAN_F12R1_FB0_Pos      (0U)
3865  #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
3866  #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
3867  #define CAN_F12R1_FB1_Pos      (1U)
3868  #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
3869  #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
3870  #define CAN_F12R1_FB2_Pos      (2U)
3871  #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
3872  #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
3873  #define CAN_F12R1_FB3_Pos      (3U)
3874  #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
3875  #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
3876  #define CAN_F12R1_FB4_Pos      (4U)
3877  #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
3878  #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
3879  #define CAN_F12R1_FB5_Pos      (5U)
3880  #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
3881  #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
3882  #define CAN_F12R1_FB6_Pos      (6U)
3883  #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
3884  #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
3885  #define CAN_F12R1_FB7_Pos      (7U)
3886  #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
3887  #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
3888  #define CAN_F12R1_FB8_Pos      (8U)
3889  #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
3890  #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
3891  #define CAN_F12R1_FB9_Pos      (9U)
3892  #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
3893  #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
3894  #define CAN_F12R1_FB10_Pos     (10U)
3895  #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
3896  #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
3897  #define CAN_F12R1_FB11_Pos     (11U)
3898  #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
3899  #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
3900  #define CAN_F12R1_FB12_Pos     (12U)
3901  #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
3902  #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
3903  #define CAN_F12R1_FB13_Pos     (13U)
3904  #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
3905  #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
3906  #define CAN_F12R1_FB14_Pos     (14U)
3907  #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
3908  #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
3909  #define CAN_F12R1_FB15_Pos     (15U)
3910  #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
3911  #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
3912  #define CAN_F12R1_FB16_Pos     (16U)
3913  #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
3914  #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
3915  #define CAN_F12R1_FB17_Pos     (17U)
3916  #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
3917  #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
3918  #define CAN_F12R1_FB18_Pos     (18U)
3919  #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
3920  #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
3921  #define CAN_F12R1_FB19_Pos     (19U)
3922  #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
3923  #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
3924  #define CAN_F12R1_FB20_Pos     (20U)
3925  #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
3926  #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
3927  #define CAN_F12R1_FB21_Pos     (21U)
3928  #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
3929  #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
3930  #define CAN_F12R1_FB22_Pos     (22U)
3931  #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
3932  #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
3933  #define CAN_F12R1_FB23_Pos     (23U)
3934  #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
3935  #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
3936  #define CAN_F12R1_FB24_Pos     (24U)
3937  #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
3938  #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
3939  #define CAN_F12R1_FB25_Pos     (25U)
3940  #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
3941  #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
3942  #define CAN_F12R1_FB26_Pos     (26U)
3943  #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
3944  #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
3945  #define CAN_F12R1_FB27_Pos     (27U)
3946  #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
3947  #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
3948  #define CAN_F12R1_FB28_Pos     (28U)
3949  #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
3950  #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
3951  #define CAN_F12R1_FB29_Pos     (29U)
3952  #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
3953  #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
3954  #define CAN_F12R1_FB30_Pos     (30U)
3955  #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
3956  #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
3957  #define CAN_F12R1_FB31_Pos     (31U)
3958  #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
3959  #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
3960  
3961  /*******************  Bit definition for CAN_F13R1 register  ******************/
3962  #define CAN_F13R1_FB0_Pos      (0U)
3963  #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
3964  #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
3965  #define CAN_F13R1_FB1_Pos      (1U)
3966  #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
3967  #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
3968  #define CAN_F13R1_FB2_Pos      (2U)
3969  #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
3970  #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
3971  #define CAN_F13R1_FB3_Pos      (3U)
3972  #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
3973  #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
3974  #define CAN_F13R1_FB4_Pos      (4U)
3975  #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
3976  #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
3977  #define CAN_F13R1_FB5_Pos      (5U)
3978  #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
3979  #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
3980  #define CAN_F13R1_FB6_Pos      (6U)
3981  #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
3982  #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
3983  #define CAN_F13R1_FB7_Pos      (7U)
3984  #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
3985  #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
3986  #define CAN_F13R1_FB8_Pos      (8U)
3987  #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
3988  #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
3989  #define CAN_F13R1_FB9_Pos      (9U)
3990  #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
3991  #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
3992  #define CAN_F13R1_FB10_Pos     (10U)
3993  #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
3994  #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
3995  #define CAN_F13R1_FB11_Pos     (11U)
3996  #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
3997  #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
3998  #define CAN_F13R1_FB12_Pos     (12U)
3999  #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
4000  #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4001  #define CAN_F13R1_FB13_Pos     (13U)
4002  #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
4003  #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4004  #define CAN_F13R1_FB14_Pos     (14U)
4005  #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
4006  #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4007  #define CAN_F13R1_FB15_Pos     (15U)
4008  #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
4009  #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4010  #define CAN_F13R1_FB16_Pos     (16U)
4011  #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4012  #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4013  #define CAN_F13R1_FB17_Pos     (17U)
4014  #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4015  #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4016  #define CAN_F13R1_FB18_Pos     (18U)
4017  #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4018  #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4019  #define CAN_F13R1_FB19_Pos     (19U)
4020  #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4021  #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4022  #define CAN_F13R1_FB20_Pos     (20U)
4023  #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4024  #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4025  #define CAN_F13R1_FB21_Pos     (21U)
4026  #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4027  #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4028  #define CAN_F13R1_FB22_Pos     (22U)
4029  #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4030  #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4031  #define CAN_F13R1_FB23_Pos     (23U)
4032  #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4033  #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4034  #define CAN_F13R1_FB24_Pos     (24U)
4035  #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4036  #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4037  #define CAN_F13R1_FB25_Pos     (25U)
4038  #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4039  #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4040  #define CAN_F13R1_FB26_Pos     (26U)
4041  #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4042  #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4043  #define CAN_F13R1_FB27_Pos     (27U)
4044  #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4045  #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4046  #define CAN_F13R1_FB28_Pos     (28U)
4047  #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4048  #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4049  #define CAN_F13R1_FB29_Pos     (29U)
4050  #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4051  #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4052  #define CAN_F13R1_FB30_Pos     (30U)
4053  #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4054  #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4055  #define CAN_F13R1_FB31_Pos     (31U)
4056  #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4057  #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4058  
4059  /*******************  Bit definition for CAN_F0R2 register  *******************/
4060  #define CAN_F0R2_FB0_Pos       (0U)
4061  #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4062  #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4063  #define CAN_F0R2_FB1_Pos       (1U)
4064  #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4065  #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4066  #define CAN_F0R2_FB2_Pos       (2U)
4067  #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4068  #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4069  #define CAN_F0R2_FB3_Pos       (3U)
4070  #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4071  #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4072  #define CAN_F0R2_FB4_Pos       (4U)
4073  #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4074  #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4075  #define CAN_F0R2_FB5_Pos       (5U)
4076  #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4077  #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4078  #define CAN_F0R2_FB6_Pos       (6U)
4079  #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4080  #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4081  #define CAN_F0R2_FB7_Pos       (7U)
4082  #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4083  #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4084  #define CAN_F0R2_FB8_Pos       (8U)
4085  #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4086  #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4087  #define CAN_F0R2_FB9_Pos       (9U)
4088  #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4089  #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4090  #define CAN_F0R2_FB10_Pos      (10U)
4091  #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4092  #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4093  #define CAN_F0R2_FB11_Pos      (11U)
4094  #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4095  #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4096  #define CAN_F0R2_FB12_Pos      (12U)
4097  #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4098  #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4099  #define CAN_F0R2_FB13_Pos      (13U)
4100  #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4101  #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4102  #define CAN_F0R2_FB14_Pos      (14U)
4103  #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4104  #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4105  #define CAN_F0R2_FB15_Pos      (15U)
4106  #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4107  #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4108  #define CAN_F0R2_FB16_Pos      (16U)
4109  #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4110  #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4111  #define CAN_F0R2_FB17_Pos      (17U)
4112  #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4113  #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4114  #define CAN_F0R2_FB18_Pos      (18U)
4115  #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4116  #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4117  #define CAN_F0R2_FB19_Pos      (19U)
4118  #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4119  #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4120  #define CAN_F0R2_FB20_Pos      (20U)
4121  #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4122  #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4123  #define CAN_F0R2_FB21_Pos      (21U)
4124  #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4125  #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4126  #define CAN_F0R2_FB22_Pos      (22U)
4127  #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4128  #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4129  #define CAN_F0R2_FB23_Pos      (23U)
4130  #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4131  #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4132  #define CAN_F0R2_FB24_Pos      (24U)
4133  #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4134  #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4135  #define CAN_F0R2_FB25_Pos      (25U)
4136  #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4137  #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4138  #define CAN_F0R2_FB26_Pos      (26U)
4139  #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4140  #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4141  #define CAN_F0R2_FB27_Pos      (27U)
4142  #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4143  #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4144  #define CAN_F0R2_FB28_Pos      (28U)
4145  #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4146  #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4147  #define CAN_F0R2_FB29_Pos      (29U)
4148  #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4149  #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4150  #define CAN_F0R2_FB30_Pos      (30U)
4151  #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4152  #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4153  #define CAN_F0R2_FB31_Pos      (31U)
4154  #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4155  #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4156  
4157  /*******************  Bit definition for CAN_F1R2 register  *******************/
4158  #define CAN_F1R2_FB0_Pos       (0U)
4159  #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4160  #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4161  #define CAN_F1R2_FB1_Pos       (1U)
4162  #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
4163  #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4164  #define CAN_F1R2_FB2_Pos       (2U)
4165  #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
4166  #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4167  #define CAN_F1R2_FB3_Pos       (3U)
4168  #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
4169  #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4170  #define CAN_F1R2_FB4_Pos       (4U)
4171  #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
4172  #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4173  #define CAN_F1R2_FB5_Pos       (5U)
4174  #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
4175  #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4176  #define CAN_F1R2_FB6_Pos       (6U)
4177  #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
4178  #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4179  #define CAN_F1R2_FB7_Pos       (7U)
4180  #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
4181  #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4182  #define CAN_F1R2_FB8_Pos       (8U)
4183  #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
4184  #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4185  #define CAN_F1R2_FB9_Pos       (9U)
4186  #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
4187  #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4188  #define CAN_F1R2_FB10_Pos      (10U)
4189  #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
4190  #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4191  #define CAN_F1R2_FB11_Pos      (11U)
4192  #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
4193  #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4194  #define CAN_F1R2_FB12_Pos      (12U)
4195  #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
4196  #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4197  #define CAN_F1R2_FB13_Pos      (13U)
4198  #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
4199  #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4200  #define CAN_F1R2_FB14_Pos      (14U)
4201  #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
4202  #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4203  #define CAN_F1R2_FB15_Pos      (15U)
4204  #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
4205  #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4206  #define CAN_F1R2_FB16_Pos      (16U)
4207  #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
4208  #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4209  #define CAN_F1R2_FB17_Pos      (17U)
4210  #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
4211  #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4212  #define CAN_F1R2_FB18_Pos      (18U)
4213  #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
4214  #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4215  #define CAN_F1R2_FB19_Pos      (19U)
4216  #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
4217  #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4218  #define CAN_F1R2_FB20_Pos      (20U)
4219  #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
4220  #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4221  #define CAN_F1R2_FB21_Pos      (21U)
4222  #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
4223  #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4224  #define CAN_F1R2_FB22_Pos      (22U)
4225  #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
4226  #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4227  #define CAN_F1R2_FB23_Pos      (23U)
4228  #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
4229  #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4230  #define CAN_F1R2_FB24_Pos      (24U)
4231  #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
4232  #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4233  #define CAN_F1R2_FB25_Pos      (25U)
4234  #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
4235  #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4236  #define CAN_F1R2_FB26_Pos      (26U)
4237  #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
4238  #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4239  #define CAN_F1R2_FB27_Pos      (27U)
4240  #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
4241  #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4242  #define CAN_F1R2_FB28_Pos      (28U)
4243  #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
4244  #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4245  #define CAN_F1R2_FB29_Pos      (29U)
4246  #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
4247  #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4248  #define CAN_F1R2_FB30_Pos      (30U)
4249  #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
4250  #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4251  #define CAN_F1R2_FB31_Pos      (31U)
4252  #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
4253  #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4254  
4255  /*******************  Bit definition for CAN_F2R2 register  *******************/
4256  #define CAN_F2R2_FB0_Pos       (0U)
4257  #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
4258  #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4259  #define CAN_F2R2_FB1_Pos       (1U)
4260  #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
4261  #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4262  #define CAN_F2R2_FB2_Pos       (2U)
4263  #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
4264  #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4265  #define CAN_F2R2_FB3_Pos       (3U)
4266  #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
4267  #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4268  #define CAN_F2R2_FB4_Pos       (4U)
4269  #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
4270  #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4271  #define CAN_F2R2_FB5_Pos       (5U)
4272  #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
4273  #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4274  #define CAN_F2R2_FB6_Pos       (6U)
4275  #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
4276  #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4277  #define CAN_F2R2_FB7_Pos       (7U)
4278  #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
4279  #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4280  #define CAN_F2R2_FB8_Pos       (8U)
4281  #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
4282  #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4283  #define CAN_F2R2_FB9_Pos       (9U)
4284  #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
4285  #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4286  #define CAN_F2R2_FB10_Pos      (10U)
4287  #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
4288  #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4289  #define CAN_F2R2_FB11_Pos      (11U)
4290  #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
4291  #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4292  #define CAN_F2R2_FB12_Pos      (12U)
4293  #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
4294  #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4295  #define CAN_F2R2_FB13_Pos      (13U)
4296  #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
4297  #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4298  #define CAN_F2R2_FB14_Pos      (14U)
4299  #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
4300  #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4301  #define CAN_F2R2_FB15_Pos      (15U)
4302  #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
4303  #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4304  #define CAN_F2R2_FB16_Pos      (16U)
4305  #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
4306  #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4307  #define CAN_F2R2_FB17_Pos      (17U)
4308  #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
4309  #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4310  #define CAN_F2R2_FB18_Pos      (18U)
4311  #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
4312  #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4313  #define CAN_F2R2_FB19_Pos      (19U)
4314  #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
4315  #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4316  #define CAN_F2R2_FB20_Pos      (20U)
4317  #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
4318  #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4319  #define CAN_F2R2_FB21_Pos      (21U)
4320  #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
4321  #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4322  #define CAN_F2R2_FB22_Pos      (22U)
4323  #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
4324  #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4325  #define CAN_F2R2_FB23_Pos      (23U)
4326  #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
4327  #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4328  #define CAN_F2R2_FB24_Pos      (24U)
4329  #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
4330  #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4331  #define CAN_F2R2_FB25_Pos      (25U)
4332  #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
4333  #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4334  #define CAN_F2R2_FB26_Pos      (26U)
4335  #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
4336  #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4337  #define CAN_F2R2_FB27_Pos      (27U)
4338  #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
4339  #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4340  #define CAN_F2R2_FB28_Pos      (28U)
4341  #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
4342  #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4343  #define CAN_F2R2_FB29_Pos      (29U)
4344  #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
4345  #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4346  #define CAN_F2R2_FB30_Pos      (30U)
4347  #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
4348  #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4349  #define CAN_F2R2_FB31_Pos      (31U)
4350  #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
4351  #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4352  
4353  /*******************  Bit definition for CAN_F3R2 register  *******************/
4354  #define CAN_F3R2_FB0_Pos       (0U)
4355  #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
4356  #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4357  #define CAN_F3R2_FB1_Pos       (1U)
4358  #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
4359  #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4360  #define CAN_F3R2_FB2_Pos       (2U)
4361  #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
4362  #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4363  #define CAN_F3R2_FB3_Pos       (3U)
4364  #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
4365  #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4366  #define CAN_F3R2_FB4_Pos       (4U)
4367  #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
4368  #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4369  #define CAN_F3R2_FB5_Pos       (5U)
4370  #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
4371  #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4372  #define CAN_F3R2_FB6_Pos       (6U)
4373  #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
4374  #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4375  #define CAN_F3R2_FB7_Pos       (7U)
4376  #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
4377  #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4378  #define CAN_F3R2_FB8_Pos       (8U)
4379  #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
4380  #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4381  #define CAN_F3R2_FB9_Pos       (9U)
4382  #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
4383  #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4384  #define CAN_F3R2_FB10_Pos      (10U)
4385  #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
4386  #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4387  #define CAN_F3R2_FB11_Pos      (11U)
4388  #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
4389  #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4390  #define CAN_F3R2_FB12_Pos      (12U)
4391  #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
4392  #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4393  #define CAN_F3R2_FB13_Pos      (13U)
4394  #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
4395  #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4396  #define CAN_F3R2_FB14_Pos      (14U)
4397  #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
4398  #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4399  #define CAN_F3R2_FB15_Pos      (15U)
4400  #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
4401  #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4402  #define CAN_F3R2_FB16_Pos      (16U)
4403  #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
4404  #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
4405  #define CAN_F3R2_FB17_Pos      (17U)
4406  #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
4407  #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
4408  #define CAN_F3R2_FB18_Pos      (18U)
4409  #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
4410  #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
4411  #define CAN_F3R2_FB19_Pos      (19U)
4412  #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
4413  #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
4414  #define CAN_F3R2_FB20_Pos      (20U)
4415  #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
4416  #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
4417  #define CAN_F3R2_FB21_Pos      (21U)
4418  #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
4419  #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
4420  #define CAN_F3R2_FB22_Pos      (22U)
4421  #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
4422  #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
4423  #define CAN_F3R2_FB23_Pos      (23U)
4424  #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
4425  #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
4426  #define CAN_F3R2_FB24_Pos      (24U)
4427  #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
4428  #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
4429  #define CAN_F3R2_FB25_Pos      (25U)
4430  #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
4431  #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
4432  #define CAN_F3R2_FB26_Pos      (26U)
4433  #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
4434  #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
4435  #define CAN_F3R2_FB27_Pos      (27U)
4436  #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
4437  #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
4438  #define CAN_F3R2_FB28_Pos      (28U)
4439  #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
4440  #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
4441  #define CAN_F3R2_FB29_Pos      (29U)
4442  #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
4443  #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
4444  #define CAN_F3R2_FB30_Pos      (30U)
4445  #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
4446  #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
4447  #define CAN_F3R2_FB31_Pos      (31U)
4448  #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
4449  #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
4450  
4451  /*******************  Bit definition for CAN_F4R2 register  *******************/
4452  #define CAN_F4R2_FB0_Pos       (0U)
4453  #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
4454  #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
4455  #define CAN_F4R2_FB1_Pos       (1U)
4456  #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
4457  #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
4458  #define CAN_F4R2_FB2_Pos       (2U)
4459  #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
4460  #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
4461  #define CAN_F4R2_FB3_Pos       (3U)
4462  #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
4463  #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
4464  #define CAN_F4R2_FB4_Pos       (4U)
4465  #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
4466  #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
4467  #define CAN_F4R2_FB5_Pos       (5U)
4468  #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
4469  #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
4470  #define CAN_F4R2_FB6_Pos       (6U)
4471  #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
4472  #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
4473  #define CAN_F4R2_FB7_Pos       (7U)
4474  #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
4475  #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
4476  #define CAN_F4R2_FB8_Pos       (8U)
4477  #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
4478  #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
4479  #define CAN_F4R2_FB9_Pos       (9U)
4480  #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
4481  #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
4482  #define CAN_F4R2_FB10_Pos      (10U)
4483  #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
4484  #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
4485  #define CAN_F4R2_FB11_Pos      (11U)
4486  #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
4487  #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
4488  #define CAN_F4R2_FB12_Pos      (12U)
4489  #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
4490  #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
4491  #define CAN_F4R2_FB13_Pos      (13U)
4492  #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
4493  #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
4494  #define CAN_F4R2_FB14_Pos      (14U)
4495  #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
4496  #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
4497  #define CAN_F4R2_FB15_Pos      (15U)
4498  #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
4499  #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
4500  #define CAN_F4R2_FB16_Pos      (16U)
4501  #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
4502  #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
4503  #define CAN_F4R2_FB17_Pos      (17U)
4504  #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
4505  #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
4506  #define CAN_F4R2_FB18_Pos      (18U)
4507  #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
4508  #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
4509  #define CAN_F4R2_FB19_Pos      (19U)
4510  #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
4511  #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
4512  #define CAN_F4R2_FB20_Pos      (20U)
4513  #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
4514  #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
4515  #define CAN_F4R2_FB21_Pos      (21U)
4516  #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
4517  #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
4518  #define CAN_F4R2_FB22_Pos      (22U)
4519  #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
4520  #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
4521  #define CAN_F4R2_FB23_Pos      (23U)
4522  #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
4523  #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
4524  #define CAN_F4R2_FB24_Pos      (24U)
4525  #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
4526  #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
4527  #define CAN_F4R2_FB25_Pos      (25U)
4528  #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
4529  #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
4530  #define CAN_F4R2_FB26_Pos      (26U)
4531  #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
4532  #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
4533  #define CAN_F4R2_FB27_Pos      (27U)
4534  #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
4535  #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
4536  #define CAN_F4R2_FB28_Pos      (28U)
4537  #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
4538  #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
4539  #define CAN_F4R2_FB29_Pos      (29U)
4540  #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
4541  #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
4542  #define CAN_F4R2_FB30_Pos      (30U)
4543  #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
4544  #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
4545  #define CAN_F4R2_FB31_Pos      (31U)
4546  #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
4547  #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
4548  
4549  /*******************  Bit definition for CAN_F5R2 register  *******************/
4550  #define CAN_F5R2_FB0_Pos       (0U)
4551  #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
4552  #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
4553  #define CAN_F5R2_FB1_Pos       (1U)
4554  #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
4555  #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
4556  #define CAN_F5R2_FB2_Pos       (2U)
4557  #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
4558  #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
4559  #define CAN_F5R2_FB3_Pos       (3U)
4560  #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
4561  #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
4562  #define CAN_F5R2_FB4_Pos       (4U)
4563  #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
4564  #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
4565  #define CAN_F5R2_FB5_Pos       (5U)
4566  #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
4567  #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
4568  #define CAN_F5R2_FB6_Pos       (6U)
4569  #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
4570  #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
4571  #define CAN_F5R2_FB7_Pos       (7U)
4572  #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
4573  #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
4574  #define CAN_F5R2_FB8_Pos       (8U)
4575  #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
4576  #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
4577  #define CAN_F5R2_FB9_Pos       (9U)
4578  #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
4579  #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
4580  #define CAN_F5R2_FB10_Pos      (10U)
4581  #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
4582  #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
4583  #define CAN_F5R2_FB11_Pos      (11U)
4584  #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
4585  #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
4586  #define CAN_F5R2_FB12_Pos      (12U)
4587  #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
4588  #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
4589  #define CAN_F5R2_FB13_Pos      (13U)
4590  #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
4591  #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
4592  #define CAN_F5R2_FB14_Pos      (14U)
4593  #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
4594  #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
4595  #define CAN_F5R2_FB15_Pos      (15U)
4596  #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
4597  #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
4598  #define CAN_F5R2_FB16_Pos      (16U)
4599  #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
4600  #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
4601  #define CAN_F5R2_FB17_Pos      (17U)
4602  #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
4603  #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
4604  #define CAN_F5R2_FB18_Pos      (18U)
4605  #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
4606  #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
4607  #define CAN_F5R2_FB19_Pos      (19U)
4608  #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
4609  #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
4610  #define CAN_F5R2_FB20_Pos      (20U)
4611  #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
4612  #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
4613  #define CAN_F5R2_FB21_Pos      (21U)
4614  #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
4615  #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
4616  #define CAN_F5R2_FB22_Pos      (22U)
4617  #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
4618  #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
4619  #define CAN_F5R2_FB23_Pos      (23U)
4620  #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
4621  #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
4622  #define CAN_F5R2_FB24_Pos      (24U)
4623  #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
4624  #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
4625  #define CAN_F5R2_FB25_Pos      (25U)
4626  #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
4627  #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
4628  #define CAN_F5R2_FB26_Pos      (26U)
4629  #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
4630  #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
4631  #define CAN_F5R2_FB27_Pos      (27U)
4632  #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
4633  #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
4634  #define CAN_F5R2_FB28_Pos      (28U)
4635  #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
4636  #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
4637  #define CAN_F5R2_FB29_Pos      (29U)
4638  #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
4639  #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
4640  #define CAN_F5R2_FB30_Pos      (30U)
4641  #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
4642  #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
4643  #define CAN_F5R2_FB31_Pos      (31U)
4644  #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
4645  #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
4646  
4647  /*******************  Bit definition for CAN_F6R2 register  *******************/
4648  #define CAN_F6R2_FB0_Pos       (0U)
4649  #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
4650  #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
4651  #define CAN_F6R2_FB1_Pos       (1U)
4652  #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
4653  #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
4654  #define CAN_F6R2_FB2_Pos       (2U)
4655  #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
4656  #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
4657  #define CAN_F6R2_FB3_Pos       (3U)
4658  #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
4659  #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
4660  #define CAN_F6R2_FB4_Pos       (4U)
4661  #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
4662  #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
4663  #define CAN_F6R2_FB5_Pos       (5U)
4664  #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
4665  #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
4666  #define CAN_F6R2_FB6_Pos       (6U)
4667  #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
4668  #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
4669  #define CAN_F6R2_FB7_Pos       (7U)
4670  #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
4671  #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
4672  #define CAN_F6R2_FB8_Pos       (8U)
4673  #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
4674  #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
4675  #define CAN_F6R2_FB9_Pos       (9U)
4676  #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
4677  #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
4678  #define CAN_F6R2_FB10_Pos      (10U)
4679  #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
4680  #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
4681  #define CAN_F6R2_FB11_Pos      (11U)
4682  #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
4683  #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
4684  #define CAN_F6R2_FB12_Pos      (12U)
4685  #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
4686  #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
4687  #define CAN_F6R2_FB13_Pos      (13U)
4688  #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
4689  #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
4690  #define CAN_F6R2_FB14_Pos      (14U)
4691  #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
4692  #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
4693  #define CAN_F6R2_FB15_Pos      (15U)
4694  #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
4695  #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
4696  #define CAN_F6R2_FB16_Pos      (16U)
4697  #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
4698  #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
4699  #define CAN_F6R2_FB17_Pos      (17U)
4700  #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
4701  #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
4702  #define CAN_F6R2_FB18_Pos      (18U)
4703  #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
4704  #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
4705  #define CAN_F6R2_FB19_Pos      (19U)
4706  #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
4707  #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
4708  #define CAN_F6R2_FB20_Pos      (20U)
4709  #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
4710  #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
4711  #define CAN_F6R2_FB21_Pos      (21U)
4712  #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
4713  #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
4714  #define CAN_F6R2_FB22_Pos      (22U)
4715  #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
4716  #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
4717  #define CAN_F6R2_FB23_Pos      (23U)
4718  #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
4719  #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
4720  #define CAN_F6R2_FB24_Pos      (24U)
4721  #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
4722  #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
4723  #define CAN_F6R2_FB25_Pos      (25U)
4724  #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
4725  #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
4726  #define CAN_F6R2_FB26_Pos      (26U)
4727  #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
4728  #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
4729  #define CAN_F6R2_FB27_Pos      (27U)
4730  #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
4731  #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
4732  #define CAN_F6R2_FB28_Pos      (28U)
4733  #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
4734  #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
4735  #define CAN_F6R2_FB29_Pos      (29U)
4736  #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
4737  #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4738  #define CAN_F6R2_FB30_Pos      (30U)
4739  #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
4740  #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4741  #define CAN_F6R2_FB31_Pos      (31U)
4742  #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
4743  #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4744  
4745  /*******************  Bit definition for CAN_F7R2 register  *******************/
4746  #define CAN_F7R2_FB0_Pos       (0U)
4747  #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
4748  #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4749  #define CAN_F7R2_FB1_Pos       (1U)
4750  #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
4751  #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4752  #define CAN_F7R2_FB2_Pos       (2U)
4753  #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
4754  #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4755  #define CAN_F7R2_FB3_Pos       (3U)
4756  #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
4757  #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4758  #define CAN_F7R2_FB4_Pos       (4U)
4759  #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
4760  #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4761  #define CAN_F7R2_FB5_Pos       (5U)
4762  #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
4763  #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4764  #define CAN_F7R2_FB6_Pos       (6U)
4765  #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
4766  #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4767  #define CAN_F7R2_FB7_Pos       (7U)
4768  #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
4769  #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4770  #define CAN_F7R2_FB8_Pos       (8U)
4771  #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
4772  #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4773  #define CAN_F7R2_FB9_Pos       (9U)
4774  #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
4775  #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
4776  #define CAN_F7R2_FB10_Pos      (10U)
4777  #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
4778  #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
4779  #define CAN_F7R2_FB11_Pos      (11U)
4780  #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
4781  #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
4782  #define CAN_F7R2_FB12_Pos      (12U)
4783  #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
4784  #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
4785  #define CAN_F7R2_FB13_Pos      (13U)
4786  #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
4787  #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
4788  #define CAN_F7R2_FB14_Pos      (14U)
4789  #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
4790  #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
4791  #define CAN_F7R2_FB15_Pos      (15U)
4792  #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
4793  #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
4794  #define CAN_F7R2_FB16_Pos      (16U)
4795  #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
4796  #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
4797  #define CAN_F7R2_FB17_Pos      (17U)
4798  #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
4799  #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
4800  #define CAN_F7R2_FB18_Pos      (18U)
4801  #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
4802  #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
4803  #define CAN_F7R2_FB19_Pos      (19U)
4804  #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
4805  #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
4806  #define CAN_F7R2_FB20_Pos      (20U)
4807  #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
4808  #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
4809  #define CAN_F7R2_FB21_Pos      (21U)
4810  #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
4811  #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
4812  #define CAN_F7R2_FB22_Pos      (22U)
4813  #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
4814  #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
4815  #define CAN_F7R2_FB23_Pos      (23U)
4816  #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
4817  #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
4818  #define CAN_F7R2_FB24_Pos      (24U)
4819  #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
4820  #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
4821  #define CAN_F7R2_FB25_Pos      (25U)
4822  #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
4823  #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
4824  #define CAN_F7R2_FB26_Pos      (26U)
4825  #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
4826  #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
4827  #define CAN_F7R2_FB27_Pos      (27U)
4828  #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
4829  #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
4830  #define CAN_F7R2_FB28_Pos      (28U)
4831  #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
4832  #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
4833  #define CAN_F7R2_FB29_Pos      (29U)
4834  #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
4835  #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
4836  #define CAN_F7R2_FB30_Pos      (30U)
4837  #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
4838  #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
4839  #define CAN_F7R2_FB31_Pos      (31U)
4840  #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
4841  #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
4842  
4843  /*******************  Bit definition for CAN_F8R2 register  *******************/
4844  #define CAN_F8R2_FB0_Pos       (0U)
4845  #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
4846  #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
4847  #define CAN_F8R2_FB1_Pos       (1U)
4848  #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
4849  #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
4850  #define CAN_F8R2_FB2_Pos       (2U)
4851  #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
4852  #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
4853  #define CAN_F8R2_FB3_Pos       (3U)
4854  #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
4855  #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
4856  #define CAN_F8R2_FB4_Pos       (4U)
4857  #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
4858  #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
4859  #define CAN_F8R2_FB5_Pos       (5U)
4860  #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
4861  #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
4862  #define CAN_F8R2_FB6_Pos       (6U)
4863  #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
4864  #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
4865  #define CAN_F8R2_FB7_Pos       (7U)
4866  #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
4867  #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
4868  #define CAN_F8R2_FB8_Pos       (8U)
4869  #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
4870  #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
4871  #define CAN_F8R2_FB9_Pos       (9U)
4872  #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
4873  #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
4874  #define CAN_F8R2_FB10_Pos      (10U)
4875  #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
4876  #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
4877  #define CAN_F8R2_FB11_Pos      (11U)
4878  #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
4879  #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
4880  #define CAN_F8R2_FB12_Pos      (12U)
4881  #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
4882  #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
4883  #define CAN_F8R2_FB13_Pos      (13U)
4884  #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
4885  #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
4886  #define CAN_F8R2_FB14_Pos      (14U)
4887  #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
4888  #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
4889  #define CAN_F8R2_FB15_Pos      (15U)
4890  #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
4891  #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
4892  #define CAN_F8R2_FB16_Pos      (16U)
4893  #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
4894  #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
4895  #define CAN_F8R2_FB17_Pos      (17U)
4896  #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
4897  #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
4898  #define CAN_F8R2_FB18_Pos      (18U)
4899  #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
4900  #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
4901  #define CAN_F8R2_FB19_Pos      (19U)
4902  #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
4903  #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
4904  #define CAN_F8R2_FB20_Pos      (20U)
4905  #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
4906  #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
4907  #define CAN_F8R2_FB21_Pos      (21U)
4908  #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
4909  #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
4910  #define CAN_F8R2_FB22_Pos      (22U)
4911  #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
4912  #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
4913  #define CAN_F8R2_FB23_Pos      (23U)
4914  #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
4915  #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
4916  #define CAN_F8R2_FB24_Pos      (24U)
4917  #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
4918  #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
4919  #define CAN_F8R2_FB25_Pos      (25U)
4920  #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
4921  #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
4922  #define CAN_F8R2_FB26_Pos      (26U)
4923  #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
4924  #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
4925  #define CAN_F8R2_FB27_Pos      (27U)
4926  #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
4927  #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
4928  #define CAN_F8R2_FB28_Pos      (28U)
4929  #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
4930  #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
4931  #define CAN_F8R2_FB29_Pos      (29U)
4932  #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
4933  #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
4934  #define CAN_F8R2_FB30_Pos      (30U)
4935  #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
4936  #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
4937  #define CAN_F8R2_FB31_Pos      (31U)
4938  #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
4939  #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
4940  
4941  /*******************  Bit definition for CAN_F9R2 register  *******************/
4942  #define CAN_F9R2_FB0_Pos       (0U)
4943  #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
4944  #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
4945  #define CAN_F9R2_FB1_Pos       (1U)
4946  #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
4947  #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
4948  #define CAN_F9R2_FB2_Pos       (2U)
4949  #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
4950  #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
4951  #define CAN_F9R2_FB3_Pos       (3U)
4952  #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
4953  #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
4954  #define CAN_F9R2_FB4_Pos       (4U)
4955  #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
4956  #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
4957  #define CAN_F9R2_FB5_Pos       (5U)
4958  #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
4959  #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
4960  #define CAN_F9R2_FB6_Pos       (6U)
4961  #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
4962  #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
4963  #define CAN_F9R2_FB7_Pos       (7U)
4964  #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
4965  #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
4966  #define CAN_F9R2_FB8_Pos       (8U)
4967  #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
4968  #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
4969  #define CAN_F9R2_FB9_Pos       (9U)
4970  #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
4971  #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
4972  #define CAN_F9R2_FB10_Pos      (10U)
4973  #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
4974  #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
4975  #define CAN_F9R2_FB11_Pos      (11U)
4976  #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
4977  #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
4978  #define CAN_F9R2_FB12_Pos      (12U)
4979  #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
4980  #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
4981  #define CAN_F9R2_FB13_Pos      (13U)
4982  #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
4983  #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
4984  #define CAN_F9R2_FB14_Pos      (14U)
4985  #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
4986  #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
4987  #define CAN_F9R2_FB15_Pos      (15U)
4988  #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
4989  #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
4990  #define CAN_F9R2_FB16_Pos      (16U)
4991  #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
4992  #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
4993  #define CAN_F9R2_FB17_Pos      (17U)
4994  #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
4995  #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
4996  #define CAN_F9R2_FB18_Pos      (18U)
4997  #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
4998  #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
4999  #define CAN_F9R2_FB19_Pos      (19U)
5000  #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
5001  #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5002  #define CAN_F9R2_FB20_Pos      (20U)
5003  #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
5004  #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5005  #define CAN_F9R2_FB21_Pos      (21U)
5006  #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
5007  #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5008  #define CAN_F9R2_FB22_Pos      (22U)
5009  #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
5010  #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5011  #define CAN_F9R2_FB23_Pos      (23U)
5012  #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5013  #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5014  #define CAN_F9R2_FB24_Pos      (24U)
5015  #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5016  #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5017  #define CAN_F9R2_FB25_Pos      (25U)
5018  #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5019  #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5020  #define CAN_F9R2_FB26_Pos      (26U)
5021  #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5022  #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5023  #define CAN_F9R2_FB27_Pos      (27U)
5024  #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5025  #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5026  #define CAN_F9R2_FB28_Pos      (28U)
5027  #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5028  #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5029  #define CAN_F9R2_FB29_Pos      (29U)
5030  #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5031  #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5032  #define CAN_F9R2_FB30_Pos      (30U)
5033  #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5034  #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5035  #define CAN_F9R2_FB31_Pos      (31U)
5036  #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5037  #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5038  
5039  /*******************  Bit definition for CAN_F10R2 register  ******************/
5040  #define CAN_F10R2_FB0_Pos      (0U)
5041  #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5042  #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5043  #define CAN_F10R2_FB1_Pos      (1U)
5044  #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5045  #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5046  #define CAN_F10R2_FB2_Pos      (2U)
5047  #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5048  #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5049  #define CAN_F10R2_FB3_Pos      (3U)
5050  #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5051  #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5052  #define CAN_F10R2_FB4_Pos      (4U)
5053  #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5054  #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5055  #define CAN_F10R2_FB5_Pos      (5U)
5056  #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5057  #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5058  #define CAN_F10R2_FB6_Pos      (6U)
5059  #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5060  #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5061  #define CAN_F10R2_FB7_Pos      (7U)
5062  #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5063  #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5064  #define CAN_F10R2_FB8_Pos      (8U)
5065  #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5066  #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5067  #define CAN_F10R2_FB9_Pos      (9U)
5068  #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5069  #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5070  #define CAN_F10R2_FB10_Pos     (10U)
5071  #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5072  #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5073  #define CAN_F10R2_FB11_Pos     (11U)
5074  #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5075  #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5076  #define CAN_F10R2_FB12_Pos     (12U)
5077  #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5078  #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5079  #define CAN_F10R2_FB13_Pos     (13U)
5080  #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5081  #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5082  #define CAN_F10R2_FB14_Pos     (14U)
5083  #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5084  #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5085  #define CAN_F10R2_FB15_Pos     (15U)
5086  #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5087  #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5088  #define CAN_F10R2_FB16_Pos     (16U)
5089  #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5090  #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5091  #define CAN_F10R2_FB17_Pos     (17U)
5092  #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5093  #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5094  #define CAN_F10R2_FB18_Pos     (18U)
5095  #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5096  #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5097  #define CAN_F10R2_FB19_Pos     (19U)
5098  #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5099  #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5100  #define CAN_F10R2_FB20_Pos     (20U)
5101  #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5102  #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5103  #define CAN_F10R2_FB21_Pos     (21U)
5104  #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5105  #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5106  #define CAN_F10R2_FB22_Pos     (22U)
5107  #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5108  #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5109  #define CAN_F10R2_FB23_Pos     (23U)
5110  #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5111  #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5112  #define CAN_F10R2_FB24_Pos     (24U)
5113  #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5114  #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5115  #define CAN_F10R2_FB25_Pos     (25U)
5116  #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5117  #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5118  #define CAN_F10R2_FB26_Pos     (26U)
5119  #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5120  #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5121  #define CAN_F10R2_FB27_Pos     (27U)
5122  #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5123  #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5124  #define CAN_F10R2_FB28_Pos     (28U)
5125  #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5126  #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5127  #define CAN_F10R2_FB29_Pos     (29U)
5128  #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5129  #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5130  #define CAN_F10R2_FB30_Pos     (30U)
5131  #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5132  #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5133  #define CAN_F10R2_FB31_Pos     (31U)
5134  #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5135  #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5136  
5137  /*******************  Bit definition for CAN_F11R2 register  ******************/
5138  #define CAN_F11R2_FB0_Pos      (0U)
5139  #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5140  #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5141  #define CAN_F11R2_FB1_Pos      (1U)
5142  #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5143  #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5144  #define CAN_F11R2_FB2_Pos      (2U)
5145  #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5146  #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5147  #define CAN_F11R2_FB3_Pos      (3U)
5148  #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5149  #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5150  #define CAN_F11R2_FB4_Pos      (4U)
5151  #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5152  #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5153  #define CAN_F11R2_FB5_Pos      (5U)
5154  #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5155  #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5156  #define CAN_F11R2_FB6_Pos      (6U)
5157  #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5158  #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5159  #define CAN_F11R2_FB7_Pos      (7U)
5160  #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5161  #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5162  #define CAN_F11R2_FB8_Pos      (8U)
5163  #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
5164  #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5165  #define CAN_F11R2_FB9_Pos      (9U)
5166  #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
5167  #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5168  #define CAN_F11R2_FB10_Pos     (10U)
5169  #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
5170  #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5171  #define CAN_F11R2_FB11_Pos     (11U)
5172  #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
5173  #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5174  #define CAN_F11R2_FB12_Pos     (12U)
5175  #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
5176  #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5177  #define CAN_F11R2_FB13_Pos     (13U)
5178  #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
5179  #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5180  #define CAN_F11R2_FB14_Pos     (14U)
5181  #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
5182  #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5183  #define CAN_F11R2_FB15_Pos     (15U)
5184  #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
5185  #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5186  #define CAN_F11R2_FB16_Pos     (16U)
5187  #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
5188  #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5189  #define CAN_F11R2_FB17_Pos     (17U)
5190  #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
5191  #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5192  #define CAN_F11R2_FB18_Pos     (18U)
5193  #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
5194  #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5195  #define CAN_F11R2_FB19_Pos     (19U)
5196  #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
5197  #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5198  #define CAN_F11R2_FB20_Pos     (20U)
5199  #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
5200  #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5201  #define CAN_F11R2_FB21_Pos     (21U)
5202  #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
5203  #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5204  #define CAN_F11R2_FB22_Pos     (22U)
5205  #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
5206  #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5207  #define CAN_F11R2_FB23_Pos     (23U)
5208  #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
5209  #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5210  #define CAN_F11R2_FB24_Pos     (24U)
5211  #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
5212  #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5213  #define CAN_F11R2_FB25_Pos     (25U)
5214  #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
5215  #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5216  #define CAN_F11R2_FB26_Pos     (26U)
5217  #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
5218  #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5219  #define CAN_F11R2_FB27_Pos     (27U)
5220  #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
5221  #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5222  #define CAN_F11R2_FB28_Pos     (28U)
5223  #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
5224  #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5225  #define CAN_F11R2_FB29_Pos     (29U)
5226  #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
5227  #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5228  #define CAN_F11R2_FB30_Pos     (30U)
5229  #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
5230  #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5231  #define CAN_F11R2_FB31_Pos     (31U)
5232  #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
5233  #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5234  
5235  /*******************  Bit definition for CAN_F12R2 register  ******************/
5236  #define CAN_F12R2_FB0_Pos      (0U)
5237  #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
5238  #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5239  #define CAN_F12R2_FB1_Pos      (1U)
5240  #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
5241  #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5242  #define CAN_F12R2_FB2_Pos      (2U)
5243  #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
5244  #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5245  #define CAN_F12R2_FB3_Pos      (3U)
5246  #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
5247  #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5248  #define CAN_F12R2_FB4_Pos      (4U)
5249  #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
5250  #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5251  #define CAN_F12R2_FB5_Pos      (5U)
5252  #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
5253  #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5254  #define CAN_F12R2_FB6_Pos      (6U)
5255  #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
5256  #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5257  #define CAN_F12R2_FB7_Pos      (7U)
5258  #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
5259  #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5260  #define CAN_F12R2_FB8_Pos      (8U)
5261  #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
5262  #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5263  #define CAN_F12R2_FB9_Pos      (9U)
5264  #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
5265  #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5266  #define CAN_F12R2_FB10_Pos     (10U)
5267  #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
5268  #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5269  #define CAN_F12R2_FB11_Pos     (11U)
5270  #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
5271  #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5272  #define CAN_F12R2_FB12_Pos     (12U)
5273  #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
5274  #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5275  #define CAN_F12R2_FB13_Pos     (13U)
5276  #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
5277  #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5278  #define CAN_F12R2_FB14_Pos     (14U)
5279  #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
5280  #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5281  #define CAN_F12R2_FB15_Pos     (15U)
5282  #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
5283  #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5284  #define CAN_F12R2_FB16_Pos     (16U)
5285  #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
5286  #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5287  #define CAN_F12R2_FB17_Pos     (17U)
5288  #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
5289  #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5290  #define CAN_F12R2_FB18_Pos     (18U)
5291  #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
5292  #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5293  #define CAN_F12R2_FB19_Pos     (19U)
5294  #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
5295  #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5296  #define CAN_F12R2_FB20_Pos     (20U)
5297  #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
5298  #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5299  #define CAN_F12R2_FB21_Pos     (21U)
5300  #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
5301  #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5302  #define CAN_F12R2_FB22_Pos     (22U)
5303  #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
5304  #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5305  #define CAN_F12R2_FB23_Pos     (23U)
5306  #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
5307  #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5308  #define CAN_F12R2_FB24_Pos     (24U)
5309  #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
5310  #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5311  #define CAN_F12R2_FB25_Pos     (25U)
5312  #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
5313  #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5314  #define CAN_F12R2_FB26_Pos     (26U)
5315  #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
5316  #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5317  #define CAN_F12R2_FB27_Pos     (27U)
5318  #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
5319  #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5320  #define CAN_F12R2_FB28_Pos     (28U)
5321  #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
5322  #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5323  #define CAN_F12R2_FB29_Pos     (29U)
5324  #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
5325  #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5326  #define CAN_F12R2_FB30_Pos     (30U)
5327  #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
5328  #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5329  #define CAN_F12R2_FB31_Pos     (31U)
5330  #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
5331  #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5332  
5333  /*******************  Bit definition for CAN_F13R2 register  ******************/
5334  #define CAN_F13R2_FB0_Pos      (0U)
5335  #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
5336  #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5337  #define CAN_F13R2_FB1_Pos      (1U)
5338  #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
5339  #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5340  #define CAN_F13R2_FB2_Pos      (2U)
5341  #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
5342  #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5343  #define CAN_F13R2_FB3_Pos      (3U)
5344  #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
5345  #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5346  #define CAN_F13R2_FB4_Pos      (4U)
5347  #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
5348  #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5349  #define CAN_F13R2_FB5_Pos      (5U)
5350  #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
5351  #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5352  #define CAN_F13R2_FB6_Pos      (6U)
5353  #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
5354  #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5355  #define CAN_F13R2_FB7_Pos      (7U)
5356  #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
5357  #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5358  #define CAN_F13R2_FB8_Pos      (8U)
5359  #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
5360  #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5361  #define CAN_F13R2_FB9_Pos      (9U)
5362  #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
5363  #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5364  #define CAN_F13R2_FB10_Pos     (10U)
5365  #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
5366  #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5367  #define CAN_F13R2_FB11_Pos     (11U)
5368  #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
5369  #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5370  #define CAN_F13R2_FB12_Pos     (12U)
5371  #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
5372  #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5373  #define CAN_F13R2_FB13_Pos     (13U)
5374  #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
5375  #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5376  #define CAN_F13R2_FB14_Pos     (14U)
5377  #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
5378  #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5379  #define CAN_F13R2_FB15_Pos     (15U)
5380  #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
5381  #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5382  #define CAN_F13R2_FB16_Pos     (16U)
5383  #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
5384  #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5385  #define CAN_F13R2_FB17_Pos     (17U)
5386  #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
5387  #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5388  #define CAN_F13R2_FB18_Pos     (18U)
5389  #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
5390  #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5391  #define CAN_F13R2_FB19_Pos     (19U)
5392  #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
5393  #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5394  #define CAN_F13R2_FB20_Pos     (20U)
5395  #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
5396  #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5397  #define CAN_F13R2_FB21_Pos     (21U)
5398  #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
5399  #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5400  #define CAN_F13R2_FB22_Pos     (22U)
5401  #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
5402  #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
5403  #define CAN_F13R2_FB23_Pos     (23U)
5404  #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
5405  #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
5406  #define CAN_F13R2_FB24_Pos     (24U)
5407  #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
5408  #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
5409  #define CAN_F13R2_FB25_Pos     (25U)
5410  #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
5411  #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
5412  #define CAN_F13R2_FB26_Pos     (26U)
5413  #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
5414  #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
5415  #define CAN_F13R2_FB27_Pos     (27U)
5416  #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
5417  #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
5418  #define CAN_F13R2_FB28_Pos     (28U)
5419  #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
5420  #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
5421  #define CAN_F13R2_FB29_Pos     (29U)
5422  #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
5423  #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
5424  #define CAN_F13R2_FB30_Pos     (30U)
5425  #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
5426  #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
5427  #define CAN_F13R2_FB31_Pos     (31U)
5428  #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
5429  #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
5430  
5431  /******************************************************************************/
5432  /*                                                                            */
5433  /*                          HDMI-CEC (CEC)                                    */
5434  /*                                                                            */
5435  /******************************************************************************/
5436  
5437  /*******************  Bit definition for CEC_CR register  *********************/
5438  #define CEC_CR_CECEN_Pos         (0U)
5439  #define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */
5440  #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                              */
5441  #define CEC_CR_TXSOM_Pos         (1U)
5442  #define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */
5443  #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                 */
5444  #define CEC_CR_TXEOM_Pos         (2U)
5445  #define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */
5446  #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                   */
5447  
5448  /*******************  Bit definition for CEC_CFGR register  *******************/
5449  #define CEC_CFGR_SFT_Pos         (0U)
5450  #define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */
5451  #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                    */
5452  #define CEC_CFGR_RXTOL_Pos       (3U)
5453  #define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */
5454  #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                           */
5455  #define CEC_CFGR_BRESTP_Pos      (4U)
5456  #define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */
5457  #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                             */
5458  #define CEC_CFGR_BREGEN_Pos      (5U)
5459  #define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */
5460  #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation         */
5461  #define CEC_CFGR_LBPEGEN_Pos     (6U)
5462  #define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */
5463  #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation    */
5464  #define CEC_CFGR_SFTOPT_Pos      (8U)
5465  #define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */
5466  #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional           */
5467  #define CEC_CFGR_BRDNOGEN_Pos    (7U)
5468  #define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */
5469  #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation       */
5470  #define CEC_CFGR_OAR_Pos         (16U)
5471  #define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */
5472  #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                         */
5473  #define CEC_CFGR_LSTN_Pos        (31U)
5474  #define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */
5475  #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                         */
5476  
5477  /*******************  Bit definition for CEC_TXDR register  *******************/
5478  #define CEC_TXDR_TXD_Pos         (0U)
5479  #define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */
5480  #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                              */
5481  
5482  /*******************  Bit definition for CEC_RXDR register  *******************/
5483  #define CEC_RXDR_RXD_Pos         (0U)
5484  #define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                   /*!< 0x000000FF */
5485  #define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                              */
5486  /*legacy define*/
5487  #define  CEC_TXDR_RXD                        CEC_RXDR_RXD      /*!< CEC Rx Data                              */
5488  
5489  /*******************  Bit definition for CEC_ISR register  ********************/
5490  #define CEC_ISR_RXBR_Pos         (0U)
5491  #define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */
5492  #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
5493  #define CEC_ISR_RXEND_Pos        (1U)
5494  #define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */
5495  #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
5496  #define CEC_ISR_RXOVR_Pos        (2U)
5497  #define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */
5498  #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
5499  #define CEC_ISR_BRE_Pos          (3U)
5500  #define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */
5501  #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
5502  #define CEC_ISR_SBPE_Pos         (4U)
5503  #define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */
5504  #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
5505  #define CEC_ISR_LBPE_Pos         (5U)
5506  #define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */
5507  #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
5508  #define CEC_ISR_RXACKE_Pos       (6U)
5509  #define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */
5510  #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
5511  #define CEC_ISR_ARBLST_Pos       (7U)
5512  #define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */
5513  #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
5514  #define CEC_ISR_TXBR_Pos         (8U)
5515  #define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */
5516  #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
5517  #define CEC_ISR_TXEND_Pos        (9U)
5518  #define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */
5519  #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
5520  #define CEC_ISR_TXUDR_Pos        (10U)
5521  #define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */
5522  #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
5523  #define CEC_ISR_TXERR_Pos        (11U)
5524  #define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */
5525  #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
5526  #define CEC_ISR_TXACKE_Pos       (12U)
5527  #define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */
5528  #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
5529  
5530  /*******************  Bit definition for CEC_IER register  ********************/
5531  #define CEC_IER_RXBRIE_Pos       (0U)
5532  #define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */
5533  #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
5534  #define CEC_IER_RXENDIE_Pos      (1U)
5535  #define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */
5536  #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
5537  #define CEC_IER_RXOVRIE_Pos      (2U)
5538  #define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */
5539  #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
5540  #define CEC_IER_BREIE_Pos        (3U)
5541  #define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */
5542  #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
5543  #define CEC_IER_SBPEIE_Pos       (4U)
5544  #define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */
5545  #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
5546  #define CEC_IER_LBPEIE_Pos       (5U)
5547  #define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */
5548  #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
5549  #define CEC_IER_RXACKEIE_Pos     (6U)
5550  #define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */
5551  #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
5552  #define CEC_IER_ARBLSTIE_Pos     (7U)
5553  #define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */
5554  #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
5555  #define CEC_IER_TXBRIE_Pos       (8U)
5556  #define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */
5557  #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
5558  #define CEC_IER_TXENDIE_Pos      (9U)
5559  #define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */
5560  #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
5561  #define CEC_IER_TXUDRIE_Pos      (10U)
5562  #define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */
5563  #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
5564  #define CEC_IER_TXERRIE_Pos      (11U)
5565  #define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */
5566  #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
5567  #define CEC_IER_TXACKEIE_Pos     (12U)
5568  #define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */
5569  #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
5570  
5571  /******************************************************************************/
5572  /*                                                                            */
5573  /*                          CRC calculation unit                              */
5574  /*                                                                            */
5575  /******************************************************************************/
5576  /*******************  Bit definition for CRC_DR register  *********************/
5577  #define CRC_DR_DR_Pos       (0U)
5578  #define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
5579  #define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
5580  
5581  
5582  /*******************  Bit definition for CRC_IDR register  ********************/
5583  #define CRC_IDR_IDR_Pos     (0U)
5584  #define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
5585  #define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
5586  
5587  
5588  /********************  Bit definition for CRC_CR register  ********************/
5589  #define CRC_CR_RESET_Pos    (0U)
5590  #define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
5591  #define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
5592  
5593  /******************************************************************************/
5594  /*                                                                            */
5595  /*                      Digital to Analog Converter                           */
5596  /*                                                                            */
5597  /******************************************************************************/
5598  /*
5599   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5600   */
5601  #define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5602  /********************  Bit definition for DAC_CR register  ********************/
5603  #define DAC_CR_EN1_Pos              (0U)
5604  #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
5605  #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
5606  #define DAC_CR_BOFF1_Pos            (1U)
5607  #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
5608  #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
5609  #define DAC_CR_TEN1_Pos             (2U)
5610  #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
5611  #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
5612  
5613  #define DAC_CR_TSEL1_Pos            (3U)
5614  #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
5615  #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5616  #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5617  #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5618  #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5619  
5620  #define DAC_CR_WAVE1_Pos            (6U)
5621  #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
5622  #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5623  #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5624  #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5625  
5626  #define DAC_CR_MAMP1_Pos            (8U)
5627  #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
5628  #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5629  #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5630  #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5631  #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5632  #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5633  
5634  #define DAC_CR_DMAEN1_Pos           (12U)
5635  #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
5636  #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
5637  #define DAC_CR_DMAUDRIE1_Pos        (13U)
5638  #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
5639  #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
5640  #define DAC_CR_EN2_Pos              (16U)
5641  #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
5642  #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
5643  #define DAC_CR_BOFF2_Pos            (17U)
5644  #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
5645  #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
5646  #define DAC_CR_TEN2_Pos             (18U)
5647  #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
5648  #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
5649  
5650  #define DAC_CR_TSEL2_Pos            (19U)
5651  #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
5652  #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5653  #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5654  #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5655  #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5656  
5657  #define DAC_CR_WAVE2_Pos            (22U)
5658  #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
5659  #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5660  #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5661  #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5662  
5663  #define DAC_CR_MAMP2_Pos            (24U)
5664  #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
5665  #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5666  #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5667  #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5668  #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5669  #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5670  
5671  #define DAC_CR_DMAEN2_Pos           (28U)
5672  #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
5673  #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
5674  #define DAC_CR_DMAUDRIE2_Pos        (29U)
5675  #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
5676  #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
5677  
5678  /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5679  #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5680  #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
5681  #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5682  #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5683  #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
5684  #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5685  
5686  /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5687  #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5688  #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
5689  #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5690  
5691  /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5692  #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5693  #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5694  #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5695  
5696  /******************  Bit definition for DAC_DHR8R1 register  ******************/
5697  #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5698  #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
5699  #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5700  
5701  /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5702  #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5703  #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
5704  #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5705  
5706  /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5707  #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5708  #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
5709  #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5710  
5711  /******************  Bit definition for DAC_DHR8R2 register  ******************/
5712  #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5713  #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
5714  #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5715  
5716  /*****************  Bit definition for DAC_DHR12RD register  ******************/
5717  #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5718  #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
5719  #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5720  #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5721  #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
5722  #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5723  
5724  /*****************  Bit definition for DAC_DHR12LD register  ******************/
5725  #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5726  #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5727  #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5728  #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5729  #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
5730  #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5731  
5732  /******************  Bit definition for DAC_DHR8RD register  ******************/
5733  #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5734  #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
5735  #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5736  #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5737  #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
5738  #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5739  
5740  /*******************  Bit definition for DAC_DOR1 register  *******************/
5741  #define DAC_DOR1_DACC1DOR_Pos       (0U)
5742  #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
5743  #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
5744  
5745  /*******************  Bit definition for DAC_DOR2 register  *******************/
5746  #define DAC_DOR2_DACC2DOR_Pos       (0U)
5747  #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
5748  #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
5749  
5750  /********************  Bit definition for DAC_SR register  ********************/
5751  #define DAC_SR_DMAUDR1_Pos          (13U)
5752  #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
5753  #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
5754  #define DAC_SR_DMAUDR2_Pos          (29U)
5755  #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
5756  #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
5757  
5758  /******************************************************************************/
5759  /*                                                                            */
5760  /*                                    DCMI                                    */
5761  /*                                                                            */
5762  /******************************************************************************/
5763  /********************  Bits definition for DCMI_CR register  ******************/
5764  #define DCMI_CR_CAPTURE_Pos        (0U)
5765  #define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
5766  #define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
5767  #define DCMI_CR_CM_Pos             (1U)
5768  #define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
5769  #define DCMI_CR_CM                 DCMI_CR_CM_Msk
5770  #define DCMI_CR_CROP_Pos           (2U)
5771  #define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
5772  #define DCMI_CR_CROP               DCMI_CR_CROP_Msk
5773  #define DCMI_CR_JPEG_Pos           (3U)
5774  #define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
5775  #define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
5776  #define DCMI_CR_ESS_Pos            (4U)
5777  #define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
5778  #define DCMI_CR_ESS                DCMI_CR_ESS_Msk
5779  #define DCMI_CR_PCKPOL_Pos         (5U)
5780  #define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
5781  #define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
5782  #define DCMI_CR_HSPOL_Pos          (6U)
5783  #define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
5784  #define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
5785  #define DCMI_CR_VSPOL_Pos          (7U)
5786  #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
5787  #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
5788  #define DCMI_CR_FCRC_0             0x00000100U
5789  #define DCMI_CR_FCRC_1             0x00000200U
5790  #define DCMI_CR_EDM_0              0x00000400U
5791  #define DCMI_CR_EDM_1              0x00000800U
5792  #define DCMI_CR_OUTEN_Pos          (13U)
5793  #define DCMI_CR_OUTEN_Msk          (0x1UL << DCMI_CR_OUTEN_Pos)                 /*!< 0x00002000 */
5794  #define DCMI_CR_OUTEN              DCMI_CR_OUTEN_Msk
5795  #define DCMI_CR_ENABLE_Pos         (14U)
5796  #define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
5797  #define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
5798  #define DCMI_CR_BSM_0              0x00010000U
5799  #define DCMI_CR_BSM_1              0x00020000U
5800  #define DCMI_CR_OEBS_Pos           (18U)
5801  #define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                  /*!< 0x00040000 */
5802  #define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
5803  #define DCMI_CR_LSM_Pos            (19U)
5804  #define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                   /*!< 0x00080000 */
5805  #define DCMI_CR_LSM                DCMI_CR_LSM_Msk
5806  #define DCMI_CR_OELS_Pos           (20U)
5807  #define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                  /*!< 0x00100000 */
5808  #define DCMI_CR_OELS               DCMI_CR_OELS_Msk
5809  
5810  /********************  Bits definition for DCMI_SR register  ******************/
5811  #define DCMI_SR_HSYNC_Pos          (0U)
5812  #define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
5813  #define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
5814  #define DCMI_SR_VSYNC_Pos          (1U)
5815  #define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
5816  #define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
5817  #define DCMI_SR_FNE_Pos            (2U)
5818  #define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
5819  #define DCMI_SR_FNE                DCMI_SR_FNE_Msk
5820  
5821  /********************  Bits definition for DCMI_RIS register  *****************/
5822  #define DCMI_RIS_FRAME_RIS_Pos     (0U)
5823  #define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
5824  #define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
5825  #define DCMI_RIS_OVR_RIS_Pos       (1U)
5826  #define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
5827  #define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
5828  #define DCMI_RIS_ERR_RIS_Pos       (2U)
5829  #define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
5830  #define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
5831  #define DCMI_RIS_VSYNC_RIS_Pos     (3U)
5832  #define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
5833  #define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
5834  #define DCMI_RIS_LINE_RIS_Pos      (4U)
5835  #define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
5836  #define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
5837  /* Legacy defines */
5838  #define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
5839  #define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
5840  #define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
5841  #define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
5842  #define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
5843  #define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
5844  
5845  /********************  Bits definition for DCMI_IER register  *****************/
5846  #define DCMI_IER_FRAME_IE_Pos      (0U)
5847  #define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
5848  #define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
5849  #define DCMI_IER_OVR_IE_Pos        (1U)
5850  #define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
5851  #define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
5852  #define DCMI_IER_ERR_IE_Pos        (2U)
5853  #define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
5854  #define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
5855  #define DCMI_IER_VSYNC_IE_Pos      (3U)
5856  #define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
5857  #define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
5858  #define DCMI_IER_LINE_IE_Pos       (4U)
5859  #define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
5860  #define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
5861  /* Legacy defines */
5862  #define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
5863  
5864  /********************  Bits definition for DCMI_MIS register  *****************/
5865  #define DCMI_MIS_FRAME_MIS_Pos     (0U)
5866  #define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
5867  #define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
5868  #define DCMI_MIS_OVR_MIS_Pos       (1U)
5869  #define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
5870  #define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
5871  #define DCMI_MIS_ERR_MIS_Pos       (2U)
5872  #define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
5873  #define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
5874  #define DCMI_MIS_VSYNC_MIS_Pos     (3U)
5875  #define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
5876  #define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
5877  #define DCMI_MIS_LINE_MIS_Pos      (4U)
5878  #define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
5879  #define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
5880  
5881  /* Legacy defines */
5882  #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
5883  #define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
5884  #define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
5885  #define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
5886  #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
5887  
5888  /********************  Bits definition for DCMI_ICR register  *****************/
5889  #define DCMI_ICR_FRAME_ISC_Pos     (0U)
5890  #define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
5891  #define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
5892  #define DCMI_ICR_OVR_ISC_Pos       (1U)
5893  #define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
5894  #define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
5895  #define DCMI_ICR_ERR_ISC_Pos       (2U)
5896  #define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
5897  #define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
5898  #define DCMI_ICR_VSYNC_ISC_Pos     (3U)
5899  #define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
5900  #define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
5901  #define DCMI_ICR_LINE_ISC_Pos      (4U)
5902  #define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
5903  #define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
5904  
5905  /* Legacy defines */
5906  #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
5907  
5908  /********************  Bits definition for DCMI_ESCR register  ******************/
5909  #define DCMI_ESCR_FSC_Pos          (0U)
5910  #define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
5911  #define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
5912  #define DCMI_ESCR_LSC_Pos          (8U)
5913  #define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
5914  #define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
5915  #define DCMI_ESCR_LEC_Pos          (16U)
5916  #define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
5917  #define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
5918  #define DCMI_ESCR_FEC_Pos          (24U)
5919  #define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
5920  #define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
5921  
5922  /********************  Bits definition for DCMI_ESUR register  ******************/
5923  #define DCMI_ESUR_FSU_Pos          (0U)
5924  #define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
5925  #define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
5926  #define DCMI_ESUR_LSU_Pos          (8U)
5927  #define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
5928  #define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
5929  #define DCMI_ESUR_LEU_Pos          (16U)
5930  #define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
5931  #define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
5932  #define DCMI_ESUR_FEU_Pos          (24U)
5933  #define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
5934  #define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
5935  
5936  /********************  Bits definition for DCMI_CWSTRT register  ******************/
5937  #define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
5938  #define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
5939  #define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
5940  #define DCMI_CWSTRT_VST_Pos        (16U)
5941  #define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
5942  #define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
5943  
5944  /********************  Bits definition for DCMI_CWSIZE register  ******************/
5945  #define DCMI_CWSIZE_CAPCNT_Pos     (0U)
5946  #define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
5947  #define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
5948  #define DCMI_CWSIZE_VLINE_Pos      (16U)
5949  #define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
5950  #define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
5951  
5952  /********************  Bits definition for DCMI_DR register  *********************/
5953  #define DCMI_DR_BYTE0_Pos          (0U)
5954  #define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
5955  #define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
5956  #define DCMI_DR_BYTE1_Pos          (8U)
5957  #define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
5958  #define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
5959  #define DCMI_DR_BYTE2_Pos          (16U)
5960  #define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
5961  #define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
5962  #define DCMI_DR_BYTE3_Pos          (24U)
5963  #define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
5964  #define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
5965  
5966  /******************************************************************************/
5967  /*                                                                            */
5968  /*                             DMA Controller                                 */
5969  /*                                                                            */
5970  /******************************************************************************/
5971  /********************  Bits definition for DMA_SxCR register  *****************/
5972  #define DMA_SxCR_CHSEL_Pos       (25U)
5973  #define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
5974  #define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk
5975  #define DMA_SxCR_CHSEL_0         0x02000000U
5976  #define DMA_SxCR_CHSEL_1         0x04000000U
5977  #define DMA_SxCR_CHSEL_2         0x08000000U
5978  #define DMA_SxCR_MBURST_Pos      (23U)
5979  #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
5980  #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
5981  #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
5982  #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
5983  #define DMA_SxCR_PBURST_Pos      (21U)
5984  #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
5985  #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
5986  #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
5987  #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
5988  #define DMA_SxCR_CT_Pos          (19U)
5989  #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
5990  #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
5991  #define DMA_SxCR_DBM_Pos         (18U)
5992  #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
5993  #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
5994  #define DMA_SxCR_PL_Pos          (16U)
5995  #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
5996  #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
5997  #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
5998  #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
5999  #define DMA_SxCR_PINCOS_Pos      (15U)
6000  #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
6001  #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
6002  #define DMA_SxCR_MSIZE_Pos       (13U)
6003  #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
6004  #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
6005  #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
6006  #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
6007  #define DMA_SxCR_PSIZE_Pos       (11U)
6008  #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
6009  #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
6010  #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
6011  #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
6012  #define DMA_SxCR_MINC_Pos        (10U)
6013  #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
6014  #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
6015  #define DMA_SxCR_PINC_Pos        (9U)
6016  #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
6017  #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
6018  #define DMA_SxCR_CIRC_Pos        (8U)
6019  #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
6020  #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
6021  #define DMA_SxCR_DIR_Pos         (6U)
6022  #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
6023  #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
6024  #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
6025  #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
6026  #define DMA_SxCR_PFCTRL_Pos      (5U)
6027  #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
6028  #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
6029  #define DMA_SxCR_TCIE_Pos        (4U)
6030  #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
6031  #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
6032  #define DMA_SxCR_HTIE_Pos        (3U)
6033  #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
6034  #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
6035  #define DMA_SxCR_TEIE_Pos        (2U)
6036  #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
6037  #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
6038  #define DMA_SxCR_DMEIE_Pos       (1U)
6039  #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
6040  #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
6041  #define DMA_SxCR_EN_Pos          (0U)
6042  #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
6043  #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
6044  
6045  /* Legacy defines */
6046  #define DMA_SxCR_ACK_Pos         (20U)
6047  #define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
6048  #define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk
6049  
6050  /********************  Bits definition for DMA_SxCNDTR register  **************/
6051  #define DMA_SxNDT_Pos            (0U)
6052  #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
6053  #define DMA_SxNDT                DMA_SxNDT_Msk
6054  #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
6055  #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
6056  #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
6057  #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
6058  #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
6059  #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
6060  #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
6061  #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
6062  #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
6063  #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
6064  #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
6065  #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
6066  #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
6067  #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
6068  #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
6069  #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
6070  
6071  /********************  Bits definition for DMA_SxFCR register  ****************/
6072  #define DMA_SxFCR_FEIE_Pos       (7U)
6073  #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
6074  #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
6075  #define DMA_SxFCR_FS_Pos         (3U)
6076  #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
6077  #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
6078  #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
6079  #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
6080  #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
6081  #define DMA_SxFCR_DMDIS_Pos      (2U)
6082  #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
6083  #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
6084  #define DMA_SxFCR_FTH_Pos        (0U)
6085  #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
6086  #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
6087  #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
6088  #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
6089  
6090  /********************  Bits definition for DMA_LISR register  *****************/
6091  #define DMA_LISR_TCIF3_Pos       (27U)
6092  #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
6093  #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
6094  #define DMA_LISR_HTIF3_Pos       (26U)
6095  #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
6096  #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
6097  #define DMA_LISR_TEIF3_Pos       (25U)
6098  #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
6099  #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
6100  #define DMA_LISR_DMEIF3_Pos      (24U)
6101  #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
6102  #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
6103  #define DMA_LISR_FEIF3_Pos       (22U)
6104  #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
6105  #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
6106  #define DMA_LISR_TCIF2_Pos       (21U)
6107  #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
6108  #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
6109  #define DMA_LISR_HTIF2_Pos       (20U)
6110  #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
6111  #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
6112  #define DMA_LISR_TEIF2_Pos       (19U)
6113  #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
6114  #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
6115  #define DMA_LISR_DMEIF2_Pos      (18U)
6116  #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
6117  #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
6118  #define DMA_LISR_FEIF2_Pos       (16U)
6119  #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
6120  #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
6121  #define DMA_LISR_TCIF1_Pos       (11U)
6122  #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
6123  #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
6124  #define DMA_LISR_HTIF1_Pos       (10U)
6125  #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
6126  #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
6127  #define DMA_LISR_TEIF1_Pos       (9U)
6128  #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
6129  #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
6130  #define DMA_LISR_DMEIF1_Pos      (8U)
6131  #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
6132  #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
6133  #define DMA_LISR_FEIF1_Pos       (6U)
6134  #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
6135  #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
6136  #define DMA_LISR_TCIF0_Pos       (5U)
6137  #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
6138  #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
6139  #define DMA_LISR_HTIF0_Pos       (4U)
6140  #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
6141  #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
6142  #define DMA_LISR_TEIF0_Pos       (3U)
6143  #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
6144  #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
6145  #define DMA_LISR_DMEIF0_Pos      (2U)
6146  #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
6147  #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
6148  #define DMA_LISR_FEIF0_Pos       (0U)
6149  #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
6150  #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
6151  
6152  /********************  Bits definition for DMA_HISR register  *****************/
6153  #define DMA_HISR_TCIF7_Pos       (27U)
6154  #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
6155  #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
6156  #define DMA_HISR_HTIF7_Pos       (26U)
6157  #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
6158  #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
6159  #define DMA_HISR_TEIF7_Pos       (25U)
6160  #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
6161  #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
6162  #define DMA_HISR_DMEIF7_Pos      (24U)
6163  #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
6164  #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
6165  #define DMA_HISR_FEIF7_Pos       (22U)
6166  #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
6167  #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
6168  #define DMA_HISR_TCIF6_Pos       (21U)
6169  #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
6170  #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
6171  #define DMA_HISR_HTIF6_Pos       (20U)
6172  #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
6173  #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
6174  #define DMA_HISR_TEIF6_Pos       (19U)
6175  #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
6176  #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
6177  #define DMA_HISR_DMEIF6_Pos      (18U)
6178  #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
6179  #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
6180  #define DMA_HISR_FEIF6_Pos       (16U)
6181  #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
6182  #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
6183  #define DMA_HISR_TCIF5_Pos       (11U)
6184  #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
6185  #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
6186  #define DMA_HISR_HTIF5_Pos       (10U)
6187  #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
6188  #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
6189  #define DMA_HISR_TEIF5_Pos       (9U)
6190  #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
6191  #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
6192  #define DMA_HISR_DMEIF5_Pos      (8U)
6193  #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
6194  #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
6195  #define DMA_HISR_FEIF5_Pos       (6U)
6196  #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
6197  #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
6198  #define DMA_HISR_TCIF4_Pos       (5U)
6199  #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
6200  #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
6201  #define DMA_HISR_HTIF4_Pos       (4U)
6202  #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
6203  #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
6204  #define DMA_HISR_TEIF4_Pos       (3U)
6205  #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
6206  #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
6207  #define DMA_HISR_DMEIF4_Pos      (2U)
6208  #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
6209  #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
6210  #define DMA_HISR_FEIF4_Pos       (0U)
6211  #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
6212  #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
6213  
6214  /********************  Bits definition for DMA_LIFCR register  ****************/
6215  #define DMA_LIFCR_CTCIF3_Pos     (27U)
6216  #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
6217  #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
6218  #define DMA_LIFCR_CHTIF3_Pos     (26U)
6219  #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
6220  #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
6221  #define DMA_LIFCR_CTEIF3_Pos     (25U)
6222  #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
6223  #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
6224  #define DMA_LIFCR_CDMEIF3_Pos    (24U)
6225  #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
6226  #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
6227  #define DMA_LIFCR_CFEIF3_Pos     (22U)
6228  #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
6229  #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
6230  #define DMA_LIFCR_CTCIF2_Pos     (21U)
6231  #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
6232  #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
6233  #define DMA_LIFCR_CHTIF2_Pos     (20U)
6234  #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
6235  #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
6236  #define DMA_LIFCR_CTEIF2_Pos     (19U)
6237  #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
6238  #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
6239  #define DMA_LIFCR_CDMEIF2_Pos    (18U)
6240  #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
6241  #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
6242  #define DMA_LIFCR_CFEIF2_Pos     (16U)
6243  #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
6244  #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
6245  #define DMA_LIFCR_CTCIF1_Pos     (11U)
6246  #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
6247  #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
6248  #define DMA_LIFCR_CHTIF1_Pos     (10U)
6249  #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
6250  #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
6251  #define DMA_LIFCR_CTEIF1_Pos     (9U)
6252  #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
6253  #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
6254  #define DMA_LIFCR_CDMEIF1_Pos    (8U)
6255  #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
6256  #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
6257  #define DMA_LIFCR_CFEIF1_Pos     (6U)
6258  #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
6259  #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
6260  #define DMA_LIFCR_CTCIF0_Pos     (5U)
6261  #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
6262  #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
6263  #define DMA_LIFCR_CHTIF0_Pos     (4U)
6264  #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
6265  #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
6266  #define DMA_LIFCR_CTEIF0_Pos     (3U)
6267  #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
6268  #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
6269  #define DMA_LIFCR_CDMEIF0_Pos    (2U)
6270  #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
6271  #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
6272  #define DMA_LIFCR_CFEIF0_Pos     (0U)
6273  #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
6274  #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
6275  
6276  /********************  Bits definition for DMA_HIFCR  register  ****************/
6277  #define DMA_HIFCR_CTCIF7_Pos     (27U)
6278  #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
6279  #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
6280  #define DMA_HIFCR_CHTIF7_Pos     (26U)
6281  #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
6282  #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
6283  #define DMA_HIFCR_CTEIF7_Pos     (25U)
6284  #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
6285  #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
6286  #define DMA_HIFCR_CDMEIF7_Pos    (24U)
6287  #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
6288  #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
6289  #define DMA_HIFCR_CFEIF7_Pos     (22U)
6290  #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
6291  #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
6292  #define DMA_HIFCR_CTCIF6_Pos     (21U)
6293  #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
6294  #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
6295  #define DMA_HIFCR_CHTIF6_Pos     (20U)
6296  #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
6297  #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
6298  #define DMA_HIFCR_CTEIF6_Pos     (19U)
6299  #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
6300  #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
6301  #define DMA_HIFCR_CDMEIF6_Pos    (18U)
6302  #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
6303  #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
6304  #define DMA_HIFCR_CFEIF6_Pos     (16U)
6305  #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
6306  #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
6307  #define DMA_HIFCR_CTCIF5_Pos     (11U)
6308  #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
6309  #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
6310  #define DMA_HIFCR_CHTIF5_Pos     (10U)
6311  #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
6312  #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
6313  #define DMA_HIFCR_CTEIF5_Pos     (9U)
6314  #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
6315  #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
6316  #define DMA_HIFCR_CDMEIF5_Pos    (8U)
6317  #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
6318  #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
6319  #define DMA_HIFCR_CFEIF5_Pos     (6U)
6320  #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
6321  #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
6322  #define DMA_HIFCR_CTCIF4_Pos     (5U)
6323  #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
6324  #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
6325  #define DMA_HIFCR_CHTIF4_Pos     (4U)
6326  #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
6327  #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
6328  #define DMA_HIFCR_CTEIF4_Pos     (3U)
6329  #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
6330  #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
6331  #define DMA_HIFCR_CDMEIF4_Pos    (2U)
6332  #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
6333  #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
6334  #define DMA_HIFCR_CFEIF4_Pos     (0U)
6335  #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
6336  #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
6337  
6338  /******************  Bit definition for DMA_SxPAR register  ********************/
6339  #define DMA_SxPAR_PA_Pos         (0U)
6340  #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
6341  #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
6342  
6343  /******************  Bit definition for DMA_SxM0AR register  ********************/
6344  #define DMA_SxM0AR_M0A_Pos       (0U)
6345  #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
6346  #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
6347  
6348  /******************  Bit definition for DMA_SxM1AR register  ********************/
6349  #define DMA_SxM1AR_M1A_Pos       (0U)
6350  #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
6351  #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
6352  
6353  
6354  /******************************************************************************/
6355  /*                                                                            */
6356  /*                    External Interrupt/Event Controller                     */
6357  /*                                                                            */
6358  /******************************************************************************/
6359  /*******************  Bit definition for EXTI_IMR register  *******************/
6360  #define EXTI_IMR_MR0_Pos          (0U)
6361  #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
6362  #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
6363  #define EXTI_IMR_MR1_Pos          (1U)
6364  #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
6365  #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
6366  #define EXTI_IMR_MR2_Pos          (2U)
6367  #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
6368  #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
6369  #define EXTI_IMR_MR3_Pos          (3U)
6370  #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
6371  #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
6372  #define EXTI_IMR_MR4_Pos          (4U)
6373  #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
6374  #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
6375  #define EXTI_IMR_MR5_Pos          (5U)
6376  #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
6377  #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
6378  #define EXTI_IMR_MR6_Pos          (6U)
6379  #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
6380  #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
6381  #define EXTI_IMR_MR7_Pos          (7U)
6382  #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
6383  #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
6384  #define EXTI_IMR_MR8_Pos          (8U)
6385  #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
6386  #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
6387  #define EXTI_IMR_MR9_Pos          (9U)
6388  #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
6389  #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
6390  #define EXTI_IMR_MR10_Pos         (10U)
6391  #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
6392  #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
6393  #define EXTI_IMR_MR11_Pos         (11U)
6394  #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
6395  #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
6396  #define EXTI_IMR_MR12_Pos         (12U)
6397  #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
6398  #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
6399  #define EXTI_IMR_MR13_Pos         (13U)
6400  #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
6401  #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
6402  #define EXTI_IMR_MR14_Pos         (14U)
6403  #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
6404  #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
6405  #define EXTI_IMR_MR15_Pos         (15U)
6406  #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
6407  #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
6408  #define EXTI_IMR_MR16_Pos         (16U)
6409  #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
6410  #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
6411  #define EXTI_IMR_MR17_Pos         (17U)
6412  #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
6413  #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
6414  #define EXTI_IMR_MR18_Pos         (18U)
6415  #define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
6416  #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
6417  #define EXTI_IMR_MR19_Pos         (19U)
6418  #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
6419  #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
6420  #define EXTI_IMR_MR20_Pos         (20U)
6421  #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
6422  #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
6423  #define EXTI_IMR_MR21_Pos         (21U)
6424  #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
6425  #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
6426  #define EXTI_IMR_MR22_Pos         (22U)
6427  #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
6428  #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
6429  
6430  /* Reference Defines */
6431  #define  EXTI_IMR_IM0                        EXTI_IMR_MR0
6432  #define  EXTI_IMR_IM1                        EXTI_IMR_MR1
6433  #define  EXTI_IMR_IM2                        EXTI_IMR_MR2
6434  #define  EXTI_IMR_IM3                        EXTI_IMR_MR3
6435  #define  EXTI_IMR_IM4                        EXTI_IMR_MR4
6436  #define  EXTI_IMR_IM5                        EXTI_IMR_MR5
6437  #define  EXTI_IMR_IM6                        EXTI_IMR_MR6
6438  #define  EXTI_IMR_IM7                        EXTI_IMR_MR7
6439  #define  EXTI_IMR_IM8                        EXTI_IMR_MR8
6440  #define  EXTI_IMR_IM9                        EXTI_IMR_MR9
6441  #define  EXTI_IMR_IM10                       EXTI_IMR_MR10
6442  #define  EXTI_IMR_IM11                       EXTI_IMR_MR11
6443  #define  EXTI_IMR_IM12                       EXTI_IMR_MR12
6444  #define  EXTI_IMR_IM13                       EXTI_IMR_MR13
6445  #define  EXTI_IMR_IM14                       EXTI_IMR_MR14
6446  #define  EXTI_IMR_IM15                       EXTI_IMR_MR15
6447  #define  EXTI_IMR_IM16                       EXTI_IMR_MR16
6448  #define  EXTI_IMR_IM17                       EXTI_IMR_MR17
6449  #define  EXTI_IMR_IM18                       EXTI_IMR_MR18
6450  #define  EXTI_IMR_IM19                       EXTI_IMR_MR19
6451  #define  EXTI_IMR_IM20                       EXTI_IMR_MR20
6452  #define  EXTI_IMR_IM21                       EXTI_IMR_MR21
6453  #define  EXTI_IMR_IM22                       EXTI_IMR_MR22
6454  #define EXTI_IMR_IM_Pos           (0U)
6455  #define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
6456  #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
6457  
6458  /*******************  Bit definition for EXTI_EMR register  *******************/
6459  #define EXTI_EMR_MR0_Pos          (0U)
6460  #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
6461  #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
6462  #define EXTI_EMR_MR1_Pos          (1U)
6463  #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
6464  #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
6465  #define EXTI_EMR_MR2_Pos          (2U)
6466  #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
6467  #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
6468  #define EXTI_EMR_MR3_Pos          (3U)
6469  #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
6470  #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
6471  #define EXTI_EMR_MR4_Pos          (4U)
6472  #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
6473  #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
6474  #define EXTI_EMR_MR5_Pos          (5U)
6475  #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
6476  #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
6477  #define EXTI_EMR_MR6_Pos          (6U)
6478  #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
6479  #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
6480  #define EXTI_EMR_MR7_Pos          (7U)
6481  #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
6482  #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
6483  #define EXTI_EMR_MR8_Pos          (8U)
6484  #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
6485  #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
6486  #define EXTI_EMR_MR9_Pos          (9U)
6487  #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
6488  #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
6489  #define EXTI_EMR_MR10_Pos         (10U)
6490  #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
6491  #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
6492  #define EXTI_EMR_MR11_Pos         (11U)
6493  #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
6494  #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
6495  #define EXTI_EMR_MR12_Pos         (12U)
6496  #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
6497  #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
6498  #define EXTI_EMR_MR13_Pos         (13U)
6499  #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
6500  #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
6501  #define EXTI_EMR_MR14_Pos         (14U)
6502  #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
6503  #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
6504  #define EXTI_EMR_MR15_Pos         (15U)
6505  #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
6506  #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
6507  #define EXTI_EMR_MR16_Pos         (16U)
6508  #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
6509  #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
6510  #define EXTI_EMR_MR17_Pos         (17U)
6511  #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
6512  #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
6513  #define EXTI_EMR_MR18_Pos         (18U)
6514  #define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
6515  #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
6516  #define EXTI_EMR_MR19_Pos         (19U)
6517  #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
6518  #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
6519  #define EXTI_EMR_MR20_Pos         (20U)
6520  #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
6521  #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
6522  #define EXTI_EMR_MR21_Pos         (21U)
6523  #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
6524  #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
6525  #define EXTI_EMR_MR22_Pos         (22U)
6526  #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
6527  #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
6528  
6529  /* Reference Defines */
6530  #define  EXTI_EMR_EM0                        EXTI_EMR_MR0
6531  #define  EXTI_EMR_EM1                        EXTI_EMR_MR1
6532  #define  EXTI_EMR_EM2                        EXTI_EMR_MR2
6533  #define  EXTI_EMR_EM3                        EXTI_EMR_MR3
6534  #define  EXTI_EMR_EM4                        EXTI_EMR_MR4
6535  #define  EXTI_EMR_EM5                        EXTI_EMR_MR5
6536  #define  EXTI_EMR_EM6                        EXTI_EMR_MR6
6537  #define  EXTI_EMR_EM7                        EXTI_EMR_MR7
6538  #define  EXTI_EMR_EM8                        EXTI_EMR_MR8
6539  #define  EXTI_EMR_EM9                        EXTI_EMR_MR9
6540  #define  EXTI_EMR_EM10                       EXTI_EMR_MR10
6541  #define  EXTI_EMR_EM11                       EXTI_EMR_MR11
6542  #define  EXTI_EMR_EM12                       EXTI_EMR_MR12
6543  #define  EXTI_EMR_EM13                       EXTI_EMR_MR13
6544  #define  EXTI_EMR_EM14                       EXTI_EMR_MR14
6545  #define  EXTI_EMR_EM15                       EXTI_EMR_MR15
6546  #define  EXTI_EMR_EM16                       EXTI_EMR_MR16
6547  #define  EXTI_EMR_EM17                       EXTI_EMR_MR17
6548  #define  EXTI_EMR_EM18                       EXTI_EMR_MR18
6549  #define  EXTI_EMR_EM19                       EXTI_EMR_MR19
6550  #define  EXTI_EMR_EM20                       EXTI_EMR_MR20
6551  #define  EXTI_EMR_EM21                       EXTI_EMR_MR21
6552  #define  EXTI_EMR_EM22                       EXTI_EMR_MR22
6553  
6554  /******************  Bit definition for EXTI_RTSR register  *******************/
6555  #define EXTI_RTSR_TR0_Pos         (0U)
6556  #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
6557  #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
6558  #define EXTI_RTSR_TR1_Pos         (1U)
6559  #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
6560  #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
6561  #define EXTI_RTSR_TR2_Pos         (2U)
6562  #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
6563  #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
6564  #define EXTI_RTSR_TR3_Pos         (3U)
6565  #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
6566  #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
6567  #define EXTI_RTSR_TR4_Pos         (4U)
6568  #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
6569  #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
6570  #define EXTI_RTSR_TR5_Pos         (5U)
6571  #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
6572  #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
6573  #define EXTI_RTSR_TR6_Pos         (6U)
6574  #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
6575  #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
6576  #define EXTI_RTSR_TR7_Pos         (7U)
6577  #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
6578  #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
6579  #define EXTI_RTSR_TR8_Pos         (8U)
6580  #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
6581  #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
6582  #define EXTI_RTSR_TR9_Pos         (9U)
6583  #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
6584  #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
6585  #define EXTI_RTSR_TR10_Pos        (10U)
6586  #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
6587  #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
6588  #define EXTI_RTSR_TR11_Pos        (11U)
6589  #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
6590  #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
6591  #define EXTI_RTSR_TR12_Pos        (12U)
6592  #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
6593  #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
6594  #define EXTI_RTSR_TR13_Pos        (13U)
6595  #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
6596  #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
6597  #define EXTI_RTSR_TR14_Pos        (14U)
6598  #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
6599  #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
6600  #define EXTI_RTSR_TR15_Pos        (15U)
6601  #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
6602  #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
6603  #define EXTI_RTSR_TR16_Pos        (16U)
6604  #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
6605  #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
6606  #define EXTI_RTSR_TR17_Pos        (17U)
6607  #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
6608  #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
6609  #define EXTI_RTSR_TR18_Pos        (18U)
6610  #define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
6611  #define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
6612  #define EXTI_RTSR_TR19_Pos        (19U)
6613  #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
6614  #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
6615  #define EXTI_RTSR_TR20_Pos        (20U)
6616  #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
6617  #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
6618  #define EXTI_RTSR_TR21_Pos        (21U)
6619  #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
6620  #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
6621  #define EXTI_RTSR_TR22_Pos        (22U)
6622  #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
6623  #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
6624  
6625  /******************  Bit definition for EXTI_FTSR register  *******************/
6626  #define EXTI_FTSR_TR0_Pos         (0U)
6627  #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
6628  #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
6629  #define EXTI_FTSR_TR1_Pos         (1U)
6630  #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
6631  #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
6632  #define EXTI_FTSR_TR2_Pos         (2U)
6633  #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
6634  #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
6635  #define EXTI_FTSR_TR3_Pos         (3U)
6636  #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
6637  #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
6638  #define EXTI_FTSR_TR4_Pos         (4U)
6639  #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
6640  #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
6641  #define EXTI_FTSR_TR5_Pos         (5U)
6642  #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
6643  #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
6644  #define EXTI_FTSR_TR6_Pos         (6U)
6645  #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
6646  #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
6647  #define EXTI_FTSR_TR7_Pos         (7U)
6648  #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
6649  #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
6650  #define EXTI_FTSR_TR8_Pos         (8U)
6651  #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
6652  #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
6653  #define EXTI_FTSR_TR9_Pos         (9U)
6654  #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
6655  #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
6656  #define EXTI_FTSR_TR10_Pos        (10U)
6657  #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
6658  #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
6659  #define EXTI_FTSR_TR11_Pos        (11U)
6660  #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
6661  #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
6662  #define EXTI_FTSR_TR12_Pos        (12U)
6663  #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
6664  #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
6665  #define EXTI_FTSR_TR13_Pos        (13U)
6666  #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
6667  #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
6668  #define EXTI_FTSR_TR14_Pos        (14U)
6669  #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
6670  #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
6671  #define EXTI_FTSR_TR15_Pos        (15U)
6672  #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
6673  #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
6674  #define EXTI_FTSR_TR16_Pos        (16U)
6675  #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
6676  #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
6677  #define EXTI_FTSR_TR17_Pos        (17U)
6678  #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
6679  #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
6680  #define EXTI_FTSR_TR18_Pos        (18U)
6681  #define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
6682  #define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
6683  #define EXTI_FTSR_TR19_Pos        (19U)
6684  #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
6685  #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
6686  #define EXTI_FTSR_TR20_Pos        (20U)
6687  #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
6688  #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
6689  #define EXTI_FTSR_TR21_Pos        (21U)
6690  #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
6691  #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
6692  #define EXTI_FTSR_TR22_Pos        (22U)
6693  #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
6694  #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
6695  
6696  /******************  Bit definition for EXTI_SWIER register  ******************/
6697  #define EXTI_SWIER_SWIER0_Pos     (0U)
6698  #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
6699  #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
6700  #define EXTI_SWIER_SWIER1_Pos     (1U)
6701  #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
6702  #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
6703  #define EXTI_SWIER_SWIER2_Pos     (2U)
6704  #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
6705  #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
6706  #define EXTI_SWIER_SWIER3_Pos     (3U)
6707  #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
6708  #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
6709  #define EXTI_SWIER_SWIER4_Pos     (4U)
6710  #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
6711  #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
6712  #define EXTI_SWIER_SWIER5_Pos     (5U)
6713  #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
6714  #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
6715  #define EXTI_SWIER_SWIER6_Pos     (6U)
6716  #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
6717  #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
6718  #define EXTI_SWIER_SWIER7_Pos     (7U)
6719  #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
6720  #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
6721  #define EXTI_SWIER_SWIER8_Pos     (8U)
6722  #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
6723  #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
6724  #define EXTI_SWIER_SWIER9_Pos     (9U)
6725  #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
6726  #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
6727  #define EXTI_SWIER_SWIER10_Pos    (10U)
6728  #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
6729  #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
6730  #define EXTI_SWIER_SWIER11_Pos    (11U)
6731  #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
6732  #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
6733  #define EXTI_SWIER_SWIER12_Pos    (12U)
6734  #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
6735  #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
6736  #define EXTI_SWIER_SWIER13_Pos    (13U)
6737  #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
6738  #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
6739  #define EXTI_SWIER_SWIER14_Pos    (14U)
6740  #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
6741  #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
6742  #define EXTI_SWIER_SWIER15_Pos    (15U)
6743  #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
6744  #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
6745  #define EXTI_SWIER_SWIER16_Pos    (16U)
6746  #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
6747  #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
6748  #define EXTI_SWIER_SWIER17_Pos    (17U)
6749  #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
6750  #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
6751  #define EXTI_SWIER_SWIER18_Pos    (18U)
6752  #define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
6753  #define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
6754  #define EXTI_SWIER_SWIER19_Pos    (19U)
6755  #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
6756  #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
6757  #define EXTI_SWIER_SWIER20_Pos    (20U)
6758  #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
6759  #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
6760  #define EXTI_SWIER_SWIER21_Pos    (21U)
6761  #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
6762  #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
6763  #define EXTI_SWIER_SWIER22_Pos    (22U)
6764  #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
6765  #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
6766  
6767  /*******************  Bit definition for EXTI_PR register  ********************/
6768  #define EXTI_PR_PR0_Pos           (0U)
6769  #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
6770  #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
6771  #define EXTI_PR_PR1_Pos           (1U)
6772  #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
6773  #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
6774  #define EXTI_PR_PR2_Pos           (2U)
6775  #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
6776  #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
6777  #define EXTI_PR_PR3_Pos           (3U)
6778  #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
6779  #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
6780  #define EXTI_PR_PR4_Pos           (4U)
6781  #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
6782  #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
6783  #define EXTI_PR_PR5_Pos           (5U)
6784  #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
6785  #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
6786  #define EXTI_PR_PR6_Pos           (6U)
6787  #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
6788  #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
6789  #define EXTI_PR_PR7_Pos           (7U)
6790  #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
6791  #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
6792  #define EXTI_PR_PR8_Pos           (8U)
6793  #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
6794  #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
6795  #define EXTI_PR_PR9_Pos           (9U)
6796  #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
6797  #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
6798  #define EXTI_PR_PR10_Pos          (10U)
6799  #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
6800  #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
6801  #define EXTI_PR_PR11_Pos          (11U)
6802  #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
6803  #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
6804  #define EXTI_PR_PR12_Pos          (12U)
6805  #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
6806  #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
6807  #define EXTI_PR_PR13_Pos          (13U)
6808  #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
6809  #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
6810  #define EXTI_PR_PR14_Pos          (14U)
6811  #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
6812  #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
6813  #define EXTI_PR_PR15_Pos          (15U)
6814  #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
6815  #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
6816  #define EXTI_PR_PR16_Pos          (16U)
6817  #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
6818  #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
6819  #define EXTI_PR_PR17_Pos          (17U)
6820  #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
6821  #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
6822  #define EXTI_PR_PR18_Pos          (18U)
6823  #define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
6824  #define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
6825  #define EXTI_PR_PR19_Pos          (19U)
6826  #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
6827  #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
6828  #define EXTI_PR_PR20_Pos          (20U)
6829  #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
6830  #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
6831  #define EXTI_PR_PR21_Pos          (21U)
6832  #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
6833  #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
6834  #define EXTI_PR_PR22_Pos          (22U)
6835  #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
6836  #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
6837  
6838  /******************************************************************************/
6839  /*                                                                            */
6840  /*                                    FLASH                                   */
6841  /*                                                                            */
6842  /******************************************************************************/
6843  /*******************  Bits definition for FLASH_ACR register  *****************/
6844  #define FLASH_ACR_LATENCY_Pos          (0U)
6845  #define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */
6846  #define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
6847  #define FLASH_ACR_LATENCY_0WS          0x00000000U
6848  #define FLASH_ACR_LATENCY_1WS          0x00000001U
6849  #define FLASH_ACR_LATENCY_2WS          0x00000002U
6850  #define FLASH_ACR_LATENCY_3WS          0x00000003U
6851  #define FLASH_ACR_LATENCY_4WS          0x00000004U
6852  #define FLASH_ACR_LATENCY_5WS          0x00000005U
6853  #define FLASH_ACR_LATENCY_6WS          0x00000006U
6854  #define FLASH_ACR_LATENCY_7WS          0x00000007U
6855  
6856  #define FLASH_ACR_LATENCY_8WS          0x00000008U
6857  #define FLASH_ACR_LATENCY_9WS          0x00000009U
6858  #define FLASH_ACR_LATENCY_10WS         0x0000000AU
6859  #define FLASH_ACR_LATENCY_11WS         0x0000000BU
6860  #define FLASH_ACR_LATENCY_12WS         0x0000000CU
6861  #define FLASH_ACR_LATENCY_13WS         0x0000000DU
6862  #define FLASH_ACR_LATENCY_14WS         0x0000000EU
6863  #define FLASH_ACR_LATENCY_15WS         0x0000000FU
6864  #define FLASH_ACR_PRFTEN_Pos           (8U)
6865  #define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
6866  #define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk
6867  #define FLASH_ACR_ICEN_Pos             (9U)
6868  #define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
6869  #define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk
6870  #define FLASH_ACR_DCEN_Pos             (10U)
6871  #define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
6872  #define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk
6873  #define FLASH_ACR_ICRST_Pos            (11U)
6874  #define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
6875  #define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk
6876  #define FLASH_ACR_DCRST_Pos            (12U)
6877  #define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
6878  #define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk
6879  #define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)
6880  #define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
6881  #define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk
6882  #define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)
6883  #define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
6884  #define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk
6885  
6886  /*******************  Bits definition for FLASH_SR register  ******************/
6887  #define FLASH_SR_EOP_Pos               (0U)
6888  #define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
6889  #define FLASH_SR_EOP                   FLASH_SR_EOP_Msk
6890  #define FLASH_SR_SOP_Pos               (1U)
6891  #define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
6892  #define FLASH_SR_SOP                   FLASH_SR_SOP_Msk
6893  #define FLASH_SR_WRPERR_Pos            (4U)
6894  #define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
6895  #define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk
6896  #define FLASH_SR_PGAERR_Pos            (5U)
6897  #define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
6898  #define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk
6899  #define FLASH_SR_PGPERR_Pos            (6U)
6900  #define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
6901  #define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk
6902  #define FLASH_SR_PGSERR_Pos            (7U)
6903  #define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
6904  #define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk
6905  #define FLASH_SR_RDERR_Pos            (8U)
6906  #define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */
6907  #define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk
6908  #define FLASH_SR_BSY_Pos               (16U)
6909  #define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
6910  #define FLASH_SR_BSY                   FLASH_SR_BSY_Msk
6911  
6912  /*******************  Bits definition for FLASH_CR register  ******************/
6913  #define FLASH_CR_PG_Pos                (0U)
6914  #define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
6915  #define FLASH_CR_PG                    FLASH_CR_PG_Msk
6916  #define FLASH_CR_SER_Pos               (1U)
6917  #define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
6918  #define FLASH_CR_SER                   FLASH_CR_SER_Msk
6919  #define FLASH_CR_MER_Pos               (2U)
6920  #define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
6921  #define FLASH_CR_MER                   FLASH_CR_MER_Msk
6922  #define FLASH_CR_MER1                        FLASH_CR_MER
6923  #define FLASH_CR_SNB_Pos               (3U)
6924  #define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
6925  #define FLASH_CR_SNB                   FLASH_CR_SNB_Msk
6926  #define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
6927  #define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
6928  #define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
6929  #define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
6930  #define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
6931  #define FLASH_CR_PSIZE_Pos             (8U)
6932  #define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
6933  #define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk
6934  #define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
6935  #define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
6936  #define FLASH_CR_MER2_Pos              (15U)
6937  #define FLASH_CR_MER2_Msk              (0x1UL << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */
6938  #define FLASH_CR_MER2                  FLASH_CR_MER2_Msk
6939  #define FLASH_CR_STRT_Pos              (16U)
6940  #define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
6941  #define FLASH_CR_STRT                  FLASH_CR_STRT_Msk
6942  #define FLASH_CR_EOPIE_Pos             (24U)
6943  #define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
6944  #define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk
6945  #define FLASH_CR_LOCK_Pos              (31U)
6946  #define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
6947  #define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk
6948  
6949  /*******************  Bits definition for FLASH_OPTCR register  ***************/
6950  #define FLASH_OPTCR_OPTLOCK_Pos        (0U)
6951  #define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
6952  #define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk
6953  #define FLASH_OPTCR_OPTSTRT_Pos        (1U)
6954  #define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
6955  #define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk
6956  
6957  #define FLASH_OPTCR_BOR_LEV_0          0x00000004U
6958  #define FLASH_OPTCR_BOR_LEV_1          0x00000008U
6959  #define FLASH_OPTCR_BOR_LEV_Pos        (2U)
6960  #define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
6961  #define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk
6962  #define FLASH_OPTCR_BFB2_Pos           (4U)
6963  #define FLASH_OPTCR_BFB2_Msk           (0x1UL << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */
6964  #define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk
6965  #define FLASH_OPTCR_WDG_SW_Pos         (5U)
6966  #define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
6967  #define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk
6968  #define FLASH_OPTCR_nRST_STOP_Pos      (6U)
6969  #define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
6970  #define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk
6971  #define FLASH_OPTCR_nRST_STDBY_Pos     (7U)
6972  #define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
6973  #define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk
6974  #define FLASH_OPTCR_RDP_Pos            (8U)
6975  #define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
6976  #define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk
6977  #define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
6978  #define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
6979  #define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
6980  #define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
6981  #define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
6982  #define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
6983  #define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
6984  #define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
6985  #define FLASH_OPTCR_nWRP_Pos           (16U)
6986  #define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
6987  #define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk
6988  #define FLASH_OPTCR_nWRP_0             0x00010000U
6989  #define FLASH_OPTCR_nWRP_1             0x00020000U
6990  #define FLASH_OPTCR_nWRP_2             0x00040000U
6991  #define FLASH_OPTCR_nWRP_3             0x00080000U
6992  #define FLASH_OPTCR_nWRP_4             0x00100000U
6993  #define FLASH_OPTCR_nWRP_5             0x00200000U
6994  #define FLASH_OPTCR_nWRP_6             0x00400000U
6995  #define FLASH_OPTCR_nWRP_7             0x00800000U
6996  #define FLASH_OPTCR_nWRP_8             0x01000000U
6997  #define FLASH_OPTCR_nWRP_9             0x02000000U
6998  #define FLASH_OPTCR_nWRP_10            0x04000000U
6999  #define FLASH_OPTCR_nWRP_11            0x08000000U
7000  #define FLASH_OPTCR_DB1M_Pos           (30U)
7001  #define FLASH_OPTCR_DB1M_Msk           (0x1UL << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */
7002  #define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk
7003  #define FLASH_OPTCR_SPRMOD_Pos         (31U)
7004  #define FLASH_OPTCR_SPRMOD_Msk         (0x1UL << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */
7005  #define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk
7006  
7007  /******************  Bits definition for FLASH_OPTCR1 register  ***************/
7008  #define FLASH_OPTCR1_nWRP_Pos          (16U)
7009  #define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
7010  #define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk
7011  #define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
7012  #define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
7013  #define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
7014  #define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
7015  #define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
7016  #define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
7017  #define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
7018  #define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
7019  #define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
7020  #define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
7021  #define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
7022  #define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
7023  
7024  /******************************************************************************/
7025  /*                                                                            */
7026  /*                          Flexible Memory Controller                        */
7027  /*                                                                            */
7028  /******************************************************************************/
7029  /******************  Bit definition for FMC_BCR1 register  *******************/
7030  #define FMC_BCR1_MBKEN_Pos          (0U)
7031  #define FMC_BCR1_MBKEN_Msk          (0x1UL << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */
7032  #define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7033  #define FMC_BCR1_MUXEN_Pos          (1U)
7034  #define FMC_BCR1_MUXEN_Msk          (0x1UL << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */
7035  #define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7036  
7037  #define FMC_BCR1_MTYP_Pos           (2U)
7038  #define FMC_BCR1_MTYP_Msk           (0x3UL << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */
7039  #define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7040  #define FMC_BCR1_MTYP_0             (0x1UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */
7041  #define FMC_BCR1_MTYP_1             (0x2UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */
7042  
7043  #define FMC_BCR1_MWID_Pos           (4U)
7044  #define FMC_BCR1_MWID_Msk           (0x3UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */
7045  #define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7046  #define FMC_BCR1_MWID_0             (0x1UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */
7047  #define FMC_BCR1_MWID_1             (0x2UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */
7048  
7049  #define FMC_BCR1_FACCEN_Pos         (6U)
7050  #define FMC_BCR1_FACCEN_Msk         (0x1UL << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */
7051  #define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */
7052  #define FMC_BCR1_BURSTEN_Pos        (8U)
7053  #define FMC_BCR1_BURSTEN_Msk        (0x1UL << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */
7054  #define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */
7055  #define FMC_BCR1_WAITPOL_Pos        (9U)
7056  #define FMC_BCR1_WAITPOL_Msk        (0x1UL << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */
7057  #define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7058  #define FMC_BCR1_WAITCFG_Pos        (11U)
7059  #define FMC_BCR1_WAITCFG_Msk        (0x1UL << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */
7060  #define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */
7061  #define FMC_BCR1_WREN_Pos           (12U)
7062  #define FMC_BCR1_WREN_Msk           (0x1UL << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */
7063  #define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */
7064  #define FMC_BCR1_WAITEN_Pos         (13U)
7065  #define FMC_BCR1_WAITEN_Msk         (0x1UL << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */
7066  #define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */
7067  #define FMC_BCR1_EXTMOD_Pos         (14U)
7068  #define FMC_BCR1_EXTMOD_Msk         (0x1UL << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */
7069  #define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */
7070  #define FMC_BCR1_ASYNCWAIT_Pos      (15U)
7071  #define FMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7072  #define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7073  #define FMC_BCR1_CPSIZE_Pos         (16U)
7074  #define FMC_BCR1_CPSIZE_Msk         (0x7UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */
7075  #define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */
7076  #define FMC_BCR1_CPSIZE_0           (0x1UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */
7077  #define FMC_BCR1_CPSIZE_1           (0x2UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */
7078  #define FMC_BCR1_CPSIZE_2           (0x4UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */
7079  #define FMC_BCR1_CBURSTRW_Pos       (19U)
7080  #define FMC_BCR1_CBURSTRW_Msk       (0x1UL << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */
7081  #define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */
7082  #define FMC_BCR1_CCLKEN_Pos         (20U)
7083  #define FMC_BCR1_CCLKEN_Msk         (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
7084  #define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */
7085  #define FMC_BCR1_WFDIS_Pos          (21U)
7086  #define FMC_BCR1_WFDIS_Msk          (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
7087  #define FMC_BCR1_WFDIS              FMC_BCR1_WFDIS_Msk                         /*!<Write FIFO Disable         */
7088  
7089  /******************  Bit definition for FMC_BCR2 register  *******************/
7090  #define FMC_BCR2_MBKEN_Pos          (0U)
7091  #define FMC_BCR2_MBKEN_Msk          (0x1UL << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */
7092  #define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7093  #define FMC_BCR2_MUXEN_Pos          (1U)
7094  #define FMC_BCR2_MUXEN_Msk          (0x1UL << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */
7095  #define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7096  
7097  #define FMC_BCR2_MTYP_Pos           (2U)
7098  #define FMC_BCR2_MTYP_Msk           (0x3UL << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */
7099  #define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7100  #define FMC_BCR2_MTYP_0             (0x1UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */
7101  #define FMC_BCR2_MTYP_1             (0x2UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */
7102  
7103  #define FMC_BCR2_MWID_Pos           (4U)
7104  #define FMC_BCR2_MWID_Msk           (0x3UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */
7105  #define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7106  #define FMC_BCR2_MWID_0             (0x1UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */
7107  #define FMC_BCR2_MWID_1             (0x2UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */
7108  
7109  #define FMC_BCR2_FACCEN_Pos         (6U)
7110  #define FMC_BCR2_FACCEN_Msk         (0x1UL << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */
7111  #define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */
7112  #define FMC_BCR2_BURSTEN_Pos        (8U)
7113  #define FMC_BCR2_BURSTEN_Msk        (0x1UL << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */
7114  #define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */
7115  #define FMC_BCR2_WAITPOL_Pos        (9U)
7116  #define FMC_BCR2_WAITPOL_Msk        (0x1UL << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */
7117  #define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7118  #define FMC_BCR2_WAITCFG_Pos        (11U)
7119  #define FMC_BCR2_WAITCFG_Msk        (0x1UL << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */
7120  #define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */
7121  #define FMC_BCR2_WREN_Pos           (12U)
7122  #define FMC_BCR2_WREN_Msk           (0x1UL << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */
7123  #define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */
7124  #define FMC_BCR2_WAITEN_Pos         (13U)
7125  #define FMC_BCR2_WAITEN_Msk         (0x1UL << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */
7126  #define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */
7127  #define FMC_BCR2_EXTMOD_Pos         (14U)
7128  #define FMC_BCR2_EXTMOD_Msk         (0x1UL << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */
7129  #define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */
7130  #define FMC_BCR2_ASYNCWAIT_Pos      (15U)
7131  #define FMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7132  #define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7133  #define FMC_BCR2_CBURSTRW_Pos       (19U)
7134  #define FMC_BCR2_CBURSTRW_Msk       (0x1UL << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */
7135  #define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */
7136  
7137  /******************  Bit definition for FMC_BCR3 register  *******************/
7138  #define FMC_BCR3_MBKEN_Pos          (0U)
7139  #define FMC_BCR3_MBKEN_Msk          (0x1UL << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */
7140  #define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7141  #define FMC_BCR3_MUXEN_Pos          (1U)
7142  #define FMC_BCR3_MUXEN_Msk          (0x1UL << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */
7143  #define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7144  
7145  #define FMC_BCR3_MTYP_Pos           (2U)
7146  #define FMC_BCR3_MTYP_Msk           (0x3UL << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */
7147  #define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7148  #define FMC_BCR3_MTYP_0             (0x1UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */
7149  #define FMC_BCR3_MTYP_1             (0x2UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */
7150  
7151  #define FMC_BCR3_MWID_Pos           (4U)
7152  #define FMC_BCR3_MWID_Msk           (0x3UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */
7153  #define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7154  #define FMC_BCR3_MWID_0             (0x1UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */
7155  #define FMC_BCR3_MWID_1             (0x2UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */
7156  
7157  #define FMC_BCR3_FACCEN_Pos         (6U)
7158  #define FMC_BCR3_FACCEN_Msk         (0x1UL << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */
7159  #define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */
7160  #define FMC_BCR3_BURSTEN_Pos        (8U)
7161  #define FMC_BCR3_BURSTEN_Msk        (0x1UL << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */
7162  #define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */
7163  #define FMC_BCR3_WAITPOL_Pos        (9U)
7164  #define FMC_BCR3_WAITPOL_Msk        (0x1UL << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */
7165  #define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7166  #define FMC_BCR3_WAITCFG_Pos        (11U)
7167  #define FMC_BCR3_WAITCFG_Msk        (0x1UL << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */
7168  #define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */
7169  #define FMC_BCR3_WREN_Pos           (12U)
7170  #define FMC_BCR3_WREN_Msk           (0x1UL << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */
7171  #define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */
7172  #define FMC_BCR3_WAITEN_Pos         (13U)
7173  #define FMC_BCR3_WAITEN_Msk         (0x1UL << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */
7174  #define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */
7175  #define FMC_BCR3_EXTMOD_Pos         (14U)
7176  #define FMC_BCR3_EXTMOD_Msk         (0x1UL << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */
7177  #define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */
7178  #define FMC_BCR3_ASYNCWAIT_Pos      (15U)
7179  #define FMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7180  #define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7181  #define FMC_BCR3_CBURSTRW_Pos       (19U)
7182  #define FMC_BCR3_CBURSTRW_Msk       (0x1UL << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */
7183  #define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */
7184  
7185  /******************  Bit definition for FMC_BCR4 register  *******************/
7186  #define FMC_BCR4_MBKEN_Pos          (0U)
7187  #define FMC_BCR4_MBKEN_Msk          (0x1UL << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */
7188  #define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7189  #define FMC_BCR4_MUXEN_Pos          (1U)
7190  #define FMC_BCR4_MUXEN_Msk          (0x1UL << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */
7191  #define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7192  
7193  #define FMC_BCR4_MTYP_Pos           (2U)
7194  #define FMC_BCR4_MTYP_Msk           (0x3UL << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */
7195  #define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7196  #define FMC_BCR4_MTYP_0             (0x1UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */
7197  #define FMC_BCR4_MTYP_1             (0x2UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */
7198  
7199  #define FMC_BCR4_MWID_Pos           (4U)
7200  #define FMC_BCR4_MWID_Msk           (0x3UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */
7201  #define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7202  #define FMC_BCR4_MWID_0             (0x1UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */
7203  #define FMC_BCR4_MWID_1             (0x2UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */
7204  
7205  #define FMC_BCR4_FACCEN_Pos         (6U)
7206  #define FMC_BCR4_FACCEN_Msk         (0x1UL << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */
7207  #define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */
7208  #define FMC_BCR4_BURSTEN_Pos        (8U)
7209  #define FMC_BCR4_BURSTEN_Msk        (0x1UL << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */
7210  #define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */
7211  #define FMC_BCR4_WAITPOL_Pos        (9U)
7212  #define FMC_BCR4_WAITPOL_Msk        (0x1UL << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */
7213  #define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7214  #define FMC_BCR4_WAITCFG_Pos        (11U)
7215  #define FMC_BCR4_WAITCFG_Msk        (0x1UL << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */
7216  #define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */
7217  #define FMC_BCR4_WREN_Pos           (12U)
7218  #define FMC_BCR4_WREN_Msk           (0x1UL << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */
7219  #define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */
7220  #define FMC_BCR4_WAITEN_Pos         (13U)
7221  #define FMC_BCR4_WAITEN_Msk         (0x1UL << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */
7222  #define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */
7223  #define FMC_BCR4_EXTMOD_Pos         (14U)
7224  #define FMC_BCR4_EXTMOD_Msk         (0x1UL << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */
7225  #define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */
7226  #define FMC_BCR4_ASYNCWAIT_Pos      (15U)
7227  #define FMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7228  #define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7229  #define FMC_BCR4_CBURSTRW_Pos       (19U)
7230  #define FMC_BCR4_CBURSTRW_Msk       (0x1UL << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */
7231  #define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */
7232  
7233  /******************  Bit definition for FMC_BTR1 register  ******************/
7234  #define FMC_BTR1_ADDSET_Pos         (0U)
7235  #define FMC_BTR1_ADDSET_Msk         (0xFUL << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */
7236  #define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7237  #define FMC_BTR1_ADDSET_0           (0x1UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */
7238  #define FMC_BTR1_ADDSET_1           (0x2UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */
7239  #define FMC_BTR1_ADDSET_2           (0x4UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */
7240  #define FMC_BTR1_ADDSET_3           (0x8UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */
7241  
7242  #define FMC_BTR1_ADDHLD_Pos         (4U)
7243  #define FMC_BTR1_ADDHLD_Msk         (0xFUL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
7244  #define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
7245  #define FMC_BTR1_ADDHLD_0           (0x1UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */
7246  #define FMC_BTR1_ADDHLD_1           (0x2UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */
7247  #define FMC_BTR1_ADDHLD_2           (0x4UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */
7248  #define FMC_BTR1_ADDHLD_3           (0x8UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */
7249  
7250  #define FMC_BTR1_DATAST_Pos         (8U)
7251  #define FMC_BTR1_DATAST_Msk         (0xFFUL << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */
7252  #define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7253  #define FMC_BTR1_DATAST_0           (0x01UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */
7254  #define FMC_BTR1_DATAST_1           (0x02UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */
7255  #define FMC_BTR1_DATAST_2           (0x04UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */
7256  #define FMC_BTR1_DATAST_3           (0x08UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */
7257  #define FMC_BTR1_DATAST_4           (0x10UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */
7258  #define FMC_BTR1_DATAST_5           (0x20UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */
7259  #define FMC_BTR1_DATAST_6           (0x40UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */
7260  #define FMC_BTR1_DATAST_7           (0x80UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */
7261  
7262  #define FMC_BTR1_BUSTURN_Pos        (16U)
7263  #define FMC_BTR1_BUSTURN_Msk        (0xFUL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
7264  #define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7265  #define FMC_BTR1_BUSTURN_0          (0x1UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */
7266  #define FMC_BTR1_BUSTURN_1          (0x2UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */
7267  #define FMC_BTR1_BUSTURN_2          (0x4UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */
7268  #define FMC_BTR1_BUSTURN_3          (0x8UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */
7269  
7270  #define FMC_BTR1_CLKDIV_Pos         (20U)
7271  #define FMC_BTR1_CLKDIV_Msk         (0xFUL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */
7272  #define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7273  #define FMC_BTR1_CLKDIV_0           (0x1UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */
7274  #define FMC_BTR1_CLKDIV_1           (0x2UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */
7275  #define FMC_BTR1_CLKDIV_2           (0x4UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */
7276  #define FMC_BTR1_CLKDIV_3           (0x8UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */
7277  
7278  #define FMC_BTR1_DATLAT_Pos         (24U)
7279  #define FMC_BTR1_DATLAT_Msk         (0xFUL << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */
7280  #define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7281  #define FMC_BTR1_DATLAT_0           (0x1UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */
7282  #define FMC_BTR1_DATLAT_1           (0x2UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */
7283  #define FMC_BTR1_DATLAT_2           (0x4UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */
7284  #define FMC_BTR1_DATLAT_3           (0x8UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */
7285  
7286  #define FMC_BTR1_ACCMOD_Pos         (28U)
7287  #define FMC_BTR1_ACCMOD_Msk         (0x3UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */
7288  #define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7289  #define FMC_BTR1_ACCMOD_0           (0x1UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */
7290  #define FMC_BTR1_ACCMOD_1           (0x2UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */
7291  
7292  /******************  Bit definition for FMC_BTR2 register  *******************/
7293  #define FMC_BTR2_ADDSET_Pos         (0U)
7294  #define FMC_BTR2_ADDSET_Msk         (0xFUL << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */
7295  #define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7296  #define FMC_BTR2_ADDSET_0           (0x1UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */
7297  #define FMC_BTR2_ADDSET_1           (0x2UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */
7298  #define FMC_BTR2_ADDSET_2           (0x4UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */
7299  #define FMC_BTR2_ADDSET_3           (0x8UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */
7300  
7301  #define FMC_BTR2_ADDHLD_Pos         (4U)
7302  #define FMC_BTR2_ADDHLD_Msk         (0xFUL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
7303  #define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7304  #define FMC_BTR2_ADDHLD_0           (0x1UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */
7305  #define FMC_BTR2_ADDHLD_1           (0x2UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */
7306  #define FMC_BTR2_ADDHLD_2           (0x4UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */
7307  #define FMC_BTR2_ADDHLD_3           (0x8UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */
7308  
7309  #define FMC_BTR2_DATAST_Pos         (8U)
7310  #define FMC_BTR2_DATAST_Msk         (0xFFUL << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */
7311  #define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7312  #define FMC_BTR2_DATAST_0           (0x01UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */
7313  #define FMC_BTR2_DATAST_1           (0x02UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */
7314  #define FMC_BTR2_DATAST_2           (0x04UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */
7315  #define FMC_BTR2_DATAST_3           (0x08UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */
7316  #define FMC_BTR2_DATAST_4           (0x10UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */
7317  #define FMC_BTR2_DATAST_5           (0x20UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */
7318  #define FMC_BTR2_DATAST_6           (0x40UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */
7319  #define FMC_BTR2_DATAST_7           (0x80UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */
7320  
7321  #define FMC_BTR2_BUSTURN_Pos        (16U)
7322  #define FMC_BTR2_BUSTURN_Msk        (0xFUL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */
7323  #define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7324  #define FMC_BTR2_BUSTURN_0          (0x1UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */
7325  #define FMC_BTR2_BUSTURN_1          (0x2UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */
7326  #define FMC_BTR2_BUSTURN_2          (0x4UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */
7327  #define FMC_BTR2_BUSTURN_3          (0x8UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */
7328  
7329  #define FMC_BTR2_CLKDIV_Pos         (20U)
7330  #define FMC_BTR2_CLKDIV_Msk         (0xFUL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */
7331  #define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7332  #define FMC_BTR2_CLKDIV_0           (0x1UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */
7333  #define FMC_BTR2_CLKDIV_1           (0x2UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */
7334  #define FMC_BTR2_CLKDIV_2           (0x4UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */
7335  #define FMC_BTR2_CLKDIV_3           (0x8UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */
7336  
7337  #define FMC_BTR2_DATLAT_Pos         (24U)
7338  #define FMC_BTR2_DATLAT_Msk         (0xFUL << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */
7339  #define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7340  #define FMC_BTR2_DATLAT_0           (0x1UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */
7341  #define FMC_BTR2_DATLAT_1           (0x2UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */
7342  #define FMC_BTR2_DATLAT_2           (0x4UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */
7343  #define FMC_BTR2_DATLAT_3           (0x8UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */
7344  
7345  #define FMC_BTR2_ACCMOD_Pos         (28U)
7346  #define FMC_BTR2_ACCMOD_Msk         (0x3UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */
7347  #define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7348  #define FMC_BTR2_ACCMOD_0           (0x1UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */
7349  #define FMC_BTR2_ACCMOD_1           (0x2UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */
7350  
7351  /*******************  Bit definition for FMC_BTR3 register  *******************/
7352  #define FMC_BTR3_ADDSET_Pos         (0U)
7353  #define FMC_BTR3_ADDSET_Msk         (0xFUL << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */
7354  #define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7355  #define FMC_BTR3_ADDSET_0           (0x1UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */
7356  #define FMC_BTR3_ADDSET_1           (0x2UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */
7357  #define FMC_BTR3_ADDSET_2           (0x4UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */
7358  #define FMC_BTR3_ADDSET_3           (0x8UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */
7359  
7360  #define FMC_BTR3_ADDHLD_Pos         (4U)
7361  #define FMC_BTR3_ADDHLD_Msk         (0xFUL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
7362  #define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7363  #define FMC_BTR3_ADDHLD_0           (0x1UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */
7364  #define FMC_BTR3_ADDHLD_1           (0x2UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */
7365  #define FMC_BTR3_ADDHLD_2           (0x4UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */
7366  #define FMC_BTR3_ADDHLD_3           (0x8UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */
7367  
7368  #define FMC_BTR3_DATAST_Pos         (8U)
7369  #define FMC_BTR3_DATAST_Msk         (0xFFUL << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */
7370  #define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7371  #define FMC_BTR3_DATAST_0           (0x01UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */
7372  #define FMC_BTR3_DATAST_1           (0x02UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */
7373  #define FMC_BTR3_DATAST_2           (0x04UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */
7374  #define FMC_BTR3_DATAST_3           (0x08UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */
7375  #define FMC_BTR3_DATAST_4           (0x10UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */
7376  #define FMC_BTR3_DATAST_5           (0x20UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */
7377  #define FMC_BTR3_DATAST_6           (0x40UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */
7378  #define FMC_BTR3_DATAST_7           (0x80UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */
7379  
7380  #define FMC_BTR3_BUSTURN_Pos        (16U)
7381  #define FMC_BTR3_BUSTURN_Msk        (0xFUL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */
7382  #define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7383  #define FMC_BTR3_BUSTURN_0          (0x1UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */
7384  #define FMC_BTR3_BUSTURN_1          (0x2UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */
7385  #define FMC_BTR3_BUSTURN_2          (0x4UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */
7386  #define FMC_BTR3_BUSTURN_3          (0x8UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */
7387  
7388  #define FMC_BTR3_CLKDIV_Pos         (20U)
7389  #define FMC_BTR3_CLKDIV_Msk         (0xFUL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */
7390  #define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7391  #define FMC_BTR3_CLKDIV_0           (0x1UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */
7392  #define FMC_BTR3_CLKDIV_1           (0x2UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */
7393  #define FMC_BTR3_CLKDIV_2           (0x4UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */
7394  #define FMC_BTR3_CLKDIV_3           (0x8UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */
7395  
7396  #define FMC_BTR3_DATLAT_Pos         (24U)
7397  #define FMC_BTR3_DATLAT_Msk         (0xFUL << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */
7398  #define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7399  #define FMC_BTR3_DATLAT_0           (0x1UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */
7400  #define FMC_BTR3_DATLAT_1           (0x2UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */
7401  #define FMC_BTR3_DATLAT_2           (0x4UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */
7402  #define FMC_BTR3_DATLAT_3           (0x8UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */
7403  
7404  #define FMC_BTR3_ACCMOD_Pos         (28U)
7405  #define FMC_BTR3_ACCMOD_Msk         (0x3UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */
7406  #define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7407  #define FMC_BTR3_ACCMOD_0           (0x1UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */
7408  #define FMC_BTR3_ACCMOD_1           (0x2UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */
7409  
7410  /******************  Bit definition for FMC_BTR4 register  *******************/
7411  #define FMC_BTR4_ADDSET_Pos         (0U)
7412  #define FMC_BTR4_ADDSET_Msk         (0xFUL << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */
7413  #define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7414  #define FMC_BTR4_ADDSET_0           (0x1UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */
7415  #define FMC_BTR4_ADDSET_1           (0x2UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */
7416  #define FMC_BTR4_ADDSET_2           (0x4UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */
7417  #define FMC_BTR4_ADDSET_3           (0x8UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */
7418  
7419  #define FMC_BTR4_ADDHLD_Pos         (4U)
7420  #define FMC_BTR4_ADDHLD_Msk         (0xFUL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
7421  #define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7422  #define FMC_BTR4_ADDHLD_0           (0x1UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */
7423  #define FMC_BTR4_ADDHLD_1           (0x2UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */
7424  #define FMC_BTR4_ADDHLD_2           (0x4UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */
7425  #define FMC_BTR4_ADDHLD_3           (0x8UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */
7426  
7427  #define FMC_BTR4_DATAST_Pos         (8U)
7428  #define FMC_BTR4_DATAST_Msk         (0xFFUL << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */
7429  #define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7430  #define FMC_BTR4_DATAST_0           (0x01UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */
7431  #define FMC_BTR4_DATAST_1           (0x02UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */
7432  #define FMC_BTR4_DATAST_2           (0x04UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */
7433  #define FMC_BTR4_DATAST_3           (0x08UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */
7434  #define FMC_BTR4_DATAST_4           (0x10UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */
7435  #define FMC_BTR4_DATAST_5           (0x20UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */
7436  #define FMC_BTR4_DATAST_6           (0x40UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */
7437  #define FMC_BTR4_DATAST_7           (0x80UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */
7438  
7439  #define FMC_BTR4_BUSTURN_Pos        (16U)
7440  #define FMC_BTR4_BUSTURN_Msk        (0xFUL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */
7441  #define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7442  #define FMC_BTR4_BUSTURN_0          (0x1UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */
7443  #define FMC_BTR4_BUSTURN_1          (0x2UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */
7444  #define FMC_BTR4_BUSTURN_2          (0x4UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */
7445  #define FMC_BTR4_BUSTURN_3          (0x8UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */
7446  
7447  #define FMC_BTR4_CLKDIV_Pos         (20U)
7448  #define FMC_BTR4_CLKDIV_Msk         (0xFUL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */
7449  #define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7450  #define FMC_BTR4_CLKDIV_0           (0x1UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */
7451  #define FMC_BTR4_CLKDIV_1           (0x2UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */
7452  #define FMC_BTR4_CLKDIV_2           (0x4UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */
7453  #define FMC_BTR4_CLKDIV_3           (0x8UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */
7454  
7455  #define FMC_BTR4_DATLAT_Pos         (24U)
7456  #define FMC_BTR4_DATLAT_Msk         (0xFUL << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */
7457  #define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7458  #define FMC_BTR4_DATLAT_0           (0x1UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */
7459  #define FMC_BTR4_DATLAT_1           (0x2UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */
7460  #define FMC_BTR4_DATLAT_2           (0x4UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */
7461  #define FMC_BTR4_DATLAT_3           (0x8UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */
7462  
7463  #define FMC_BTR4_ACCMOD_Pos         (28U)
7464  #define FMC_BTR4_ACCMOD_Msk         (0x3UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */
7465  #define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7466  #define FMC_BTR4_ACCMOD_0           (0x1UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */
7467  #define FMC_BTR4_ACCMOD_1           (0x2UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */
7468  
7469  /******************  Bit definition for FMC_BWTR1 register  ******************/
7470  #define FMC_BWTR1_ADDSET_Pos        (0U)
7471  #define FMC_BWTR1_ADDSET_Msk        (0xFUL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */
7472  #define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7473  #define FMC_BWTR1_ADDSET_0          (0x1UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */
7474  #define FMC_BWTR1_ADDSET_1          (0x2UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */
7475  #define FMC_BWTR1_ADDSET_2          (0x4UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */
7476  #define FMC_BWTR1_ADDSET_3          (0x8UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */
7477  
7478  #define FMC_BWTR1_ADDHLD_Pos        (4U)
7479  #define FMC_BWTR1_ADDHLD_Msk        (0xFUL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */
7480  #define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7481  #define FMC_BWTR1_ADDHLD_0          (0x1UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */
7482  #define FMC_BWTR1_ADDHLD_1          (0x2UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */
7483  #define FMC_BWTR1_ADDHLD_2          (0x4UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */
7484  #define FMC_BWTR1_ADDHLD_3          (0x8UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */
7485  
7486  #define FMC_BWTR1_DATAST_Pos        (8U)
7487  #define FMC_BWTR1_DATAST_Msk        (0xFFUL << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */
7488  #define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7489  #define FMC_BWTR1_DATAST_0          (0x01UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */
7490  #define FMC_BWTR1_DATAST_1          (0x02UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */
7491  #define FMC_BWTR1_DATAST_2          (0x04UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */
7492  #define FMC_BWTR1_DATAST_3          (0x08UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */
7493  #define FMC_BWTR1_DATAST_4          (0x10UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */
7494  #define FMC_BWTR1_DATAST_5          (0x20UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */
7495  #define FMC_BWTR1_DATAST_6          (0x40UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */
7496  #define FMC_BWTR1_DATAST_7          (0x80UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */
7497  
7498  #define FMC_BWTR1_BUSTURN_Pos       (16U)
7499  #define FMC_BWTR1_BUSTURN_Msk       (0xFUL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */
7500  #define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7501  #define FMC_BWTR1_BUSTURN_0         (0x1UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */
7502  #define FMC_BWTR1_BUSTURN_1         (0x2UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */
7503  #define FMC_BWTR1_BUSTURN_2         (0x4UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */
7504  #define FMC_BWTR1_BUSTURN_3         (0x8UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */
7505  
7506  #define FMC_BWTR1_ACCMOD_Pos        (28U)
7507  #define FMC_BWTR1_ACCMOD_Msk        (0x3UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */
7508  #define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7509  #define FMC_BWTR1_ACCMOD_0          (0x1UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */
7510  #define FMC_BWTR1_ACCMOD_1          (0x2UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */
7511  
7512  /******************  Bit definition for FMC_BWTR2 register  ******************/
7513  #define FMC_BWTR2_ADDSET_Pos        (0U)
7514  #define FMC_BWTR2_ADDSET_Msk        (0xFUL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */
7515  #define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7516  #define FMC_BWTR2_ADDSET_0          (0x1UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */
7517  #define FMC_BWTR2_ADDSET_1          (0x2UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */
7518  #define FMC_BWTR2_ADDSET_2          (0x4UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */
7519  #define FMC_BWTR2_ADDSET_3          (0x8UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */
7520  
7521  #define FMC_BWTR2_ADDHLD_Pos        (4U)
7522  #define FMC_BWTR2_ADDHLD_Msk        (0xFUL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */
7523  #define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7524  #define FMC_BWTR2_ADDHLD_0          (0x1UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */
7525  #define FMC_BWTR2_ADDHLD_1          (0x2UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */
7526  #define FMC_BWTR2_ADDHLD_2          (0x4UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */
7527  #define FMC_BWTR2_ADDHLD_3          (0x8UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */
7528  
7529  #define FMC_BWTR2_DATAST_Pos        (8U)
7530  #define FMC_BWTR2_DATAST_Msk        (0xFFUL << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */
7531  #define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7532  #define FMC_BWTR2_DATAST_0          (0x01UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */
7533  #define FMC_BWTR2_DATAST_1          (0x02UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */
7534  #define FMC_BWTR2_DATAST_2          (0x04UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */
7535  #define FMC_BWTR2_DATAST_3          (0x08UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */
7536  #define FMC_BWTR2_DATAST_4          (0x10UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */
7537  #define FMC_BWTR2_DATAST_5          (0x20UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */
7538  #define FMC_BWTR2_DATAST_6          (0x40UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */
7539  #define FMC_BWTR2_DATAST_7          (0x80UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */
7540  
7541  #define FMC_BWTR2_BUSTURN_Pos       (16U)
7542  #define FMC_BWTR2_BUSTURN_Msk       (0xFUL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */
7543  #define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7544  #define FMC_BWTR2_BUSTURN_0         (0x1UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */
7545  #define FMC_BWTR2_BUSTURN_1         (0x2UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */
7546  #define FMC_BWTR2_BUSTURN_2         (0x4UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */
7547  #define FMC_BWTR2_BUSTURN_3         (0x8UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */
7548  
7549  #define FMC_BWTR2_ACCMOD_Pos        (28U)
7550  #define FMC_BWTR2_ACCMOD_Msk        (0x3UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */
7551  #define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7552  #define FMC_BWTR2_ACCMOD_0          (0x1UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */
7553  #define FMC_BWTR2_ACCMOD_1          (0x2UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */
7554  
7555  /******************  Bit definition for FMC_BWTR3 register  ******************/
7556  #define FMC_BWTR3_ADDSET_Pos        (0U)
7557  #define FMC_BWTR3_ADDSET_Msk        (0xFUL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */
7558  #define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7559  #define FMC_BWTR3_ADDSET_0          (0x1UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */
7560  #define FMC_BWTR3_ADDSET_1          (0x2UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */
7561  #define FMC_BWTR3_ADDSET_2          (0x4UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */
7562  #define FMC_BWTR3_ADDSET_3          (0x8UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */
7563  
7564  #define FMC_BWTR3_ADDHLD_Pos        (4U)
7565  #define FMC_BWTR3_ADDHLD_Msk        (0xFUL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */
7566  #define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7567  #define FMC_BWTR3_ADDHLD_0          (0x1UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */
7568  #define FMC_BWTR3_ADDHLD_1          (0x2UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */
7569  #define FMC_BWTR3_ADDHLD_2          (0x4UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */
7570  #define FMC_BWTR3_ADDHLD_3          (0x8UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */
7571  
7572  #define FMC_BWTR3_DATAST_Pos        (8U)
7573  #define FMC_BWTR3_DATAST_Msk        (0xFFUL << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */
7574  #define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7575  #define FMC_BWTR3_DATAST_0          (0x01UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */
7576  #define FMC_BWTR3_DATAST_1          (0x02UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */
7577  #define FMC_BWTR3_DATAST_2          (0x04UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */
7578  #define FMC_BWTR3_DATAST_3          (0x08UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */
7579  #define FMC_BWTR3_DATAST_4          (0x10UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */
7580  #define FMC_BWTR3_DATAST_5          (0x20UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */
7581  #define FMC_BWTR3_DATAST_6          (0x40UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */
7582  #define FMC_BWTR3_DATAST_7          (0x80UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */
7583  
7584  #define FMC_BWTR3_BUSTURN_Pos       (16U)
7585  #define FMC_BWTR3_BUSTURN_Msk       (0xFUL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */
7586  #define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7587  #define FMC_BWTR3_BUSTURN_0         (0x1UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */
7588  #define FMC_BWTR3_BUSTURN_1         (0x2UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */
7589  #define FMC_BWTR3_BUSTURN_2         (0x4UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */
7590  #define FMC_BWTR3_BUSTURN_3         (0x8UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */
7591  
7592  #define FMC_BWTR3_ACCMOD_Pos        (28U)
7593  #define FMC_BWTR3_ACCMOD_Msk        (0x3UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */
7594  #define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7595  #define FMC_BWTR3_ACCMOD_0          (0x1UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */
7596  #define FMC_BWTR3_ACCMOD_1          (0x2UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */
7597  
7598  /******************  Bit definition for FMC_BWTR4 register  ******************/
7599  #define FMC_BWTR4_ADDSET_Pos        (0U)
7600  #define FMC_BWTR4_ADDSET_Msk        (0xFUL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */
7601  #define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7602  #define FMC_BWTR4_ADDSET_0          (0x1UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */
7603  #define FMC_BWTR4_ADDSET_1          (0x2UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */
7604  #define FMC_BWTR4_ADDSET_2          (0x4UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */
7605  #define FMC_BWTR4_ADDSET_3          (0x8UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */
7606  
7607  #define FMC_BWTR4_ADDHLD_Pos        (4U)
7608  #define FMC_BWTR4_ADDHLD_Msk        (0xFUL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */
7609  #define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7610  #define FMC_BWTR4_ADDHLD_0          (0x1UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */
7611  #define FMC_BWTR4_ADDHLD_1          (0x2UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */
7612  #define FMC_BWTR4_ADDHLD_2          (0x4UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */
7613  #define FMC_BWTR4_ADDHLD_3          (0x8UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */
7614  
7615  #define FMC_BWTR4_DATAST_Pos        (8U)
7616  #define FMC_BWTR4_DATAST_Msk        (0xFFUL << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */
7617  #define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7618  #define FMC_BWTR4_DATAST_0          (0x01UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */
7619  #define FMC_BWTR4_DATAST_1          (0x02UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */
7620  #define FMC_BWTR4_DATAST_2          (0x04UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */
7621  #define FMC_BWTR4_DATAST_3          (0x08UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */
7622  #define FMC_BWTR4_DATAST_4          (0x10UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */
7623  #define FMC_BWTR4_DATAST_5          (0x20UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */
7624  #define FMC_BWTR4_DATAST_6          (0x40UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */
7625  #define FMC_BWTR4_DATAST_7          (0x80UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */
7626  
7627  #define FMC_BWTR4_BUSTURN_Pos       (16U)
7628  #define FMC_BWTR4_BUSTURN_Msk       (0xFUL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */
7629  #define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7630  #define FMC_BWTR4_BUSTURN_0         (0x1UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */
7631  #define FMC_BWTR4_BUSTURN_1         (0x2UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */
7632  #define FMC_BWTR4_BUSTURN_2         (0x4UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */
7633  #define FMC_BWTR4_BUSTURN_3         (0x8UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */
7634  
7635  #define FMC_BWTR4_ACCMOD_Pos        (28U)
7636  #define FMC_BWTR4_ACCMOD_Msk        (0x3UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */
7637  #define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7638  #define FMC_BWTR4_ACCMOD_0          (0x1UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */
7639  #define FMC_BWTR4_ACCMOD_1          (0x2UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */
7640  
7641  /******************  Bit definition for FMC_PCR register  *******************/
7642  #define FMC_PCR_PWAITEN_Pos         (1U)
7643  #define FMC_PCR_PWAITEN_Msk         (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
7644  #define FMC_PCR_PWAITEN             FMC_PCR_PWAITEN_Msk                        /*!<Wait feature enable bit                   */
7645  #define FMC_PCR_PBKEN_Pos           (2U)
7646  #define FMC_PCR_PBKEN_Msk           (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
7647  #define FMC_PCR_PBKEN               FMC_PCR_PBKEN_Msk                          /*!<PC Card/NAND Flash memory bank enable bit */
7648  #define FMC_PCR_PTYP_Pos            (3U)
7649  #define FMC_PCR_PTYP_Msk            (0x1UL << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */
7650  #define FMC_PCR_PTYP                FMC_PCR_PTYP_Msk                           /*!<Memory type                               */
7651  
7652  #define FMC_PCR_PWID_Pos            (4U)
7653  #define FMC_PCR_PWID_Msk            (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
7654  #define FMC_PCR_PWID                FMC_PCR_PWID_Msk                           /*!<PWID[1:0] bits (NAND Flash databus width) */
7655  #define FMC_PCR_PWID_0              (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
7656  #define FMC_PCR_PWID_1              (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
7657  
7658  #define FMC_PCR_ECCEN_Pos           (6U)
7659  #define FMC_PCR_ECCEN_Msk           (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
7660  #define FMC_PCR_ECCEN               FMC_PCR_ECCEN_Msk                          /*!<ECC computation logic enable bit          */
7661  
7662  #define FMC_PCR_TCLR_Pos            (9U)
7663  #define FMC_PCR_TCLR_Msk            (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
7664  #define FMC_PCR_TCLR                FMC_PCR_TCLR_Msk                           /*!<TCLR[3:0] bits (CLE to RE delay)          */
7665  #define FMC_PCR_TCLR_0              (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
7666  #define FMC_PCR_TCLR_1              (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
7667  #define FMC_PCR_TCLR_2              (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
7668  #define FMC_PCR_TCLR_3              (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
7669  
7670  #define FMC_PCR_TAR_Pos             (13U)
7671  #define FMC_PCR_TAR_Msk             (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
7672  #define FMC_PCR_TAR                 FMC_PCR_TAR_Msk                            /*!<TAR[3:0] bits (ALE to RE delay)           */
7673  #define FMC_PCR_TAR_0               (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
7674  #define FMC_PCR_TAR_1               (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
7675  #define FMC_PCR_TAR_2               (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
7676  #define FMC_PCR_TAR_3               (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
7677  
7678  #define FMC_PCR_ECCPS_Pos           (17U)
7679  #define FMC_PCR_ECCPS_Msk           (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
7680  #define FMC_PCR_ECCPS               FMC_PCR_ECCPS_Msk                          /*!<ECCPS[1:0] bits (ECC page size)           */
7681  #define FMC_PCR_ECCPS_0             (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */
7682  #define FMC_PCR_ECCPS_1             (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */
7683  #define FMC_PCR_ECCPS_2             (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */
7684  
7685  /*******************  Bit definition for FMC_SR register  *******************/
7686  #define FMC_SR_IRS_Pos              (0U)
7687  #define FMC_SR_IRS_Msk              (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
7688  #define FMC_SR_IRS                  FMC_SR_IRS_Msk                             /*!<Interrupt Rising Edge status                */
7689  #define FMC_SR_ILS_Pos              (1U)
7690  #define FMC_SR_ILS_Msk              (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
7691  #define FMC_SR_ILS                  FMC_SR_ILS_Msk                             /*!<Interrupt Level status                      */
7692  #define FMC_SR_IFS_Pos              (2U)
7693  #define FMC_SR_IFS_Msk              (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
7694  #define FMC_SR_IFS                  FMC_SR_IFS_Msk                             /*!<Interrupt Falling Edge status               */
7695  #define FMC_SR_IREN_Pos             (3U)
7696  #define FMC_SR_IREN_Msk             (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
7697  #define FMC_SR_IREN                 FMC_SR_IREN_Msk                            /*!<Interrupt Rising Edge detection Enable bit  */
7698  #define FMC_SR_ILEN_Pos             (4U)
7699  #define FMC_SR_ILEN_Msk             (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
7700  #define FMC_SR_ILEN                 FMC_SR_ILEN_Msk                            /*!<Interrupt Level detection Enable bit        */
7701  #define FMC_SR_IFEN_Pos             (5U)
7702  #define FMC_SR_IFEN_Msk             (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
7703  #define FMC_SR_IFEN                 FMC_SR_IFEN_Msk                            /*!<Interrupt Falling Edge detection Enable bit */
7704  #define FMC_SR_FEMPT_Pos            (6U)
7705  #define FMC_SR_FEMPT_Msk            (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
7706  #define FMC_SR_FEMPT                FMC_SR_FEMPT_Msk                           /*!<FIFO empty                                  */
7707  
7708  /******************  Bit definition for FMC_PMEM register  ******************/
7709  #define FMC_PMEM_MEMSET2_Pos        (0U)
7710  #define FMC_PMEM_MEMSET2_Msk        (0xFFUL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x000000FF */
7711  #define FMC_PMEM_MEMSET2            FMC_PMEM_MEMSET2_Msk                       /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
7712  #define FMC_PMEM_MEMSET2_0          (0x01UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000001 */
7713  #define FMC_PMEM_MEMSET2_1          (0x02UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000002 */
7714  #define FMC_PMEM_MEMSET2_2          (0x04UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000004 */
7715  #define FMC_PMEM_MEMSET2_3          (0x08UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000008 */
7716  #define FMC_PMEM_MEMSET2_4          (0x10UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000010 */
7717  #define FMC_PMEM_MEMSET2_5          (0x20UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000020 */
7718  #define FMC_PMEM_MEMSET2_6          (0x40UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000040 */
7719  #define FMC_PMEM_MEMSET2_7          (0x80UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000080 */
7720  
7721  #define FMC_PMEM_MEMWAIT2_Pos       (8U)
7722  #define FMC_PMEM_MEMWAIT2_Msk       (0xFFUL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x0000FF00 */
7723  #define FMC_PMEM_MEMWAIT2           FMC_PMEM_MEMWAIT2_Msk                      /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
7724  #define FMC_PMEM_MEMWAIT2_0         (0x01UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000100 */
7725  #define FMC_PMEM_MEMWAIT2_1         (0x02UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000200 */
7726  #define FMC_PMEM_MEMWAIT2_2         (0x04UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000400 */
7727  #define FMC_PMEM_MEMWAIT2_3         (0x08UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000800 */
7728  #define FMC_PMEM_MEMWAIT2_4         (0x10UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00001000 */
7729  #define FMC_PMEM_MEMWAIT2_5         (0x20UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00002000 */
7730  #define FMC_PMEM_MEMWAIT2_6         (0x40UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00004000 */
7731  #define FMC_PMEM_MEMWAIT2_7         (0x80UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00008000 */
7732  
7733  #define FMC_PMEM_MEMHOLD2_Pos       (16U)
7734  #define FMC_PMEM_MEMHOLD2_Msk       (0xFFUL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00FF0000 */
7735  #define FMC_PMEM_MEMHOLD2           FMC_PMEM_MEMHOLD2_Msk                      /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
7736  #define FMC_PMEM_MEMHOLD2_0         (0x01UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00010000 */
7737  #define FMC_PMEM_MEMHOLD2_1         (0x02UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00020000 */
7738  #define FMC_PMEM_MEMHOLD2_2         (0x04UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00040000 */
7739  #define FMC_PMEM_MEMHOLD2_3         (0x08UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00080000 */
7740  #define FMC_PMEM_MEMHOLD2_4         (0x10UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00100000 */
7741  #define FMC_PMEM_MEMHOLD2_5         (0x20UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00200000 */
7742  #define FMC_PMEM_MEMHOLD2_6         (0x40UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00400000 */
7743  #define FMC_PMEM_MEMHOLD2_7         (0x80UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00800000 */
7744  
7745  #define FMC_PMEM_MEMHIZ2_Pos        (24U)
7746  #define FMC_PMEM_MEMHIZ2_Msk        (0xFFUL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0xFF000000 */
7747  #define FMC_PMEM_MEMHIZ2            FMC_PMEM_MEMHIZ2_Msk                       /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
7748  #define FMC_PMEM_MEMHIZ2_0          (0x01UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x01000000 */
7749  #define FMC_PMEM_MEMHIZ2_1          (0x02UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x02000000 */
7750  #define FMC_PMEM_MEMHIZ2_2          (0x04UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x04000000 */
7751  #define FMC_PMEM_MEMHIZ2_3          (0x08UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x08000000 */
7752  #define FMC_PMEM_MEMHIZ2_4          (0x10UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x10000000 */
7753  #define FMC_PMEM_MEMHIZ2_5          (0x20UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x20000000 */
7754  #define FMC_PMEM_MEMHIZ2_6          (0x40UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x40000000 */
7755  #define FMC_PMEM_MEMHIZ2_7          (0x80UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x80000000 */
7756  
7757  /******************  Bit definition for FMC_PATT register  ******************/
7758  #define FMC_PATT_ATTSET2_Pos        (0U)
7759  #define FMC_PATT_ATTSET2_Msk        (0xFFUL << FMC_PATT_ATTSET2_Pos)            /*!< 0x000000FF */
7760  #define FMC_PATT_ATTSET2            FMC_PATT_ATTSET2_Msk                       /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
7761  #define FMC_PATT_ATTSET2_0          (0x01UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000001 */
7762  #define FMC_PATT_ATTSET2_1          (0x02UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000002 */
7763  #define FMC_PATT_ATTSET2_2          (0x04UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000004 */
7764  #define FMC_PATT_ATTSET2_3          (0x08UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000008 */
7765  #define FMC_PATT_ATTSET2_4          (0x10UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000010 */
7766  #define FMC_PATT_ATTSET2_5          (0x20UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000020 */
7767  #define FMC_PATT_ATTSET2_6          (0x40UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000040 */
7768  #define FMC_PATT_ATTSET2_7          (0x80UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000080 */
7769  
7770  #define FMC_PATT_ATTWAIT2_Pos       (8U)
7771  #define FMC_PATT_ATTWAIT2_Msk       (0xFFUL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x0000FF00 */
7772  #define FMC_PATT_ATTWAIT2           FMC_PATT_ATTWAIT2_Msk                      /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
7773  #define FMC_PATT_ATTWAIT2_0         (0x01UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000100 */
7774  #define FMC_PATT_ATTWAIT2_1         (0x02UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000200 */
7775  #define FMC_PATT_ATTWAIT2_2         (0x04UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000400 */
7776  #define FMC_PATT_ATTWAIT2_3         (0x08UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000800 */
7777  #define FMC_PATT_ATTWAIT2_4         (0x10UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00001000 */
7778  #define FMC_PATT_ATTWAIT2_5         (0x20UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00002000 */
7779  #define FMC_PATT_ATTWAIT2_6         (0x40UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00004000 */
7780  #define FMC_PATT_ATTWAIT2_7         (0x80UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00008000 */
7781  
7782  #define FMC_PATT_ATTHOLD2_Pos       (16U)
7783  #define FMC_PATT_ATTHOLD2_Msk       (0xFFUL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00FF0000 */
7784  #define FMC_PATT_ATTHOLD2           FMC_PATT_ATTHOLD2_Msk                      /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
7785  #define FMC_PATT_ATTHOLD2_0         (0x01UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00010000 */
7786  #define FMC_PATT_ATTHOLD2_1         (0x02UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00020000 */
7787  #define FMC_PATT_ATTHOLD2_2         (0x04UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00040000 */
7788  #define FMC_PATT_ATTHOLD2_3         (0x08UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00080000 */
7789  #define FMC_PATT_ATTHOLD2_4         (0x10UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00100000 */
7790  #define FMC_PATT_ATTHOLD2_5         (0x20UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00200000 */
7791  #define FMC_PATT_ATTHOLD2_6         (0x40UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00400000 */
7792  #define FMC_PATT_ATTHOLD2_7         (0x80UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00800000 */
7793  
7794  #define FMC_PATT_ATTHIZ2_Pos        (24U)
7795  #define FMC_PATT_ATTHIZ2_Msk        (0xFFUL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0xFF000000 */
7796  #define FMC_PATT_ATTHIZ2            FMC_PATT_ATTHIZ2_Msk                       /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
7797  #define FMC_PATT_ATTHIZ2_0          (0x01UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x01000000 */
7798  #define FMC_PATT_ATTHIZ2_1          (0x02UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x02000000 */
7799  #define FMC_PATT_ATTHIZ2_2          (0x04UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x04000000 */
7800  #define FMC_PATT_ATTHIZ2_3          (0x08UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x08000000 */
7801  #define FMC_PATT_ATTHIZ2_4          (0x10UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x10000000 */
7802  #define FMC_PATT_ATTHIZ2_5          (0x20UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x20000000 */
7803  #define FMC_PATT_ATTHIZ2_6          (0x40UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x40000000 */
7804  #define FMC_PATT_ATTHIZ2_7          (0x80UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x80000000 */
7805  
7806  /******************  Bit definition for FMC_ECCR register  ******************/
7807  #define FMC_ECCR_ECC2_Pos           (0U)
7808  #define FMC_ECCR_ECC2_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC2_Pos)         /*!< 0xFFFFFFFF */
7809  #define FMC_ECCR_ECC2               FMC_ECCR_ECC2_Msk                          /*!<ECC result */
7810  
7811  /******************  Bit definition for FMC_SDCR1 register  ******************/
7812  #define FMC_SDCR1_NC_Pos            (0U)
7813  #define FMC_SDCR1_NC_Msk            (0x3UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */
7814  #define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
7815  #define FMC_SDCR1_NC_0              (0x1UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */
7816  #define FMC_SDCR1_NC_1              (0x2UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */
7817  
7818  #define FMC_SDCR1_NR_Pos            (2U)
7819  #define FMC_SDCR1_NR_Msk            (0x3UL << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */
7820  #define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
7821  #define FMC_SDCR1_NR_0              (0x1UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */
7822  #define FMC_SDCR1_NR_1              (0x2UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */
7823  
7824  #define FMC_SDCR1_MWID_Pos          (4U)
7825  #define FMC_SDCR1_MWID_Msk          (0x3UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */
7826  #define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
7827  #define FMC_SDCR1_MWID_0            (0x1UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */
7828  #define FMC_SDCR1_MWID_1            (0x2UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */
7829  
7830  #define FMC_SDCR1_NB_Pos            (6U)
7831  #define FMC_SDCR1_NB_Msk            (0x1UL << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */
7832  #define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */
7833  
7834  #define FMC_SDCR1_CAS_Pos           (7U)
7835  #define FMC_SDCR1_CAS_Msk           (0x3UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */
7836  #define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
7837  #define FMC_SDCR1_CAS_0             (0x1UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */
7838  #define FMC_SDCR1_CAS_1             (0x2UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */
7839  
7840  #define FMC_SDCR1_WP_Pos            (9U)
7841  #define FMC_SDCR1_WP_Msk            (0x1UL << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */
7842  #define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */
7843  
7844  #define FMC_SDCR1_SDCLK_Pos         (10U)
7845  #define FMC_SDCR1_SDCLK_Msk         (0x3UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */
7846  #define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */
7847  #define FMC_SDCR1_SDCLK_0           (0x1UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */
7848  #define FMC_SDCR1_SDCLK_1           (0x2UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */
7849  
7850  #define FMC_SDCR1_RBURST_Pos        (12U)
7851  #define FMC_SDCR1_RBURST_Msk        (0x1UL << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */
7852  #define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */
7853  
7854  #define FMC_SDCR1_RPIPE_Pos         (13U)
7855  #define FMC_SDCR1_RPIPE_Msk         (0x3UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */
7856  #define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */
7857  #define FMC_SDCR1_RPIPE_0           (0x1UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */
7858  #define FMC_SDCR1_RPIPE_1           (0x2UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */
7859  
7860  /******************  Bit definition for FMC_SDCR2 register  ******************/
7861  #define FMC_SDCR2_NC_Pos            (0U)
7862  #define FMC_SDCR2_NC_Msk            (0x3UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */
7863  #define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
7864  #define FMC_SDCR2_NC_0              (0x1UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */
7865  #define FMC_SDCR2_NC_1              (0x2UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */
7866  
7867  #define FMC_SDCR2_NR_Pos            (2U)
7868  #define FMC_SDCR2_NR_Msk            (0x3UL << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */
7869  #define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
7870  #define FMC_SDCR2_NR_0              (0x1UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */
7871  #define FMC_SDCR2_NR_1              (0x2UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */
7872  
7873  #define FMC_SDCR2_MWID_Pos          (4U)
7874  #define FMC_SDCR2_MWID_Msk          (0x3UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */
7875  #define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
7876  #define FMC_SDCR2_MWID_0            (0x1UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */
7877  #define FMC_SDCR2_MWID_1            (0x2UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */
7878  
7879  #define FMC_SDCR2_NB_Pos            (6U)
7880  #define FMC_SDCR2_NB_Msk            (0x1UL << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */
7881  #define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */
7882  
7883  #define FMC_SDCR2_CAS_Pos           (7U)
7884  #define FMC_SDCR2_CAS_Msk           (0x3UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */
7885  #define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
7886  #define FMC_SDCR2_CAS_0             (0x1UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */
7887  #define FMC_SDCR2_CAS_1             (0x2UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */
7888  
7889  #define FMC_SDCR2_WP_Pos            (9U)
7890  #define FMC_SDCR2_WP_Msk            (0x1UL << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */
7891  #define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */
7892  
7893  #define FMC_SDCR2_SDCLK_Pos         (10U)
7894  #define FMC_SDCR2_SDCLK_Msk         (0x3UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */
7895  #define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */
7896  #define FMC_SDCR2_SDCLK_0           (0x1UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */
7897  #define FMC_SDCR2_SDCLK_1           (0x2UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */
7898  
7899  #define FMC_SDCR2_RBURST_Pos        (12U)
7900  #define FMC_SDCR2_RBURST_Msk        (0x1UL << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */
7901  #define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */
7902  
7903  #define FMC_SDCR2_RPIPE_Pos         (13U)
7904  #define FMC_SDCR2_RPIPE_Msk         (0x3UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */
7905  #define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */
7906  #define FMC_SDCR2_RPIPE_0           (0x1UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */
7907  #define FMC_SDCR2_RPIPE_1           (0x2UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */
7908  
7909  /******************  Bit definition for FMC_SDTR1 register  ******************/
7910  #define FMC_SDTR1_TMRD_Pos          (0U)
7911  #define FMC_SDTR1_TMRD_Msk          (0xFUL << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */
7912  #define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
7913  #define FMC_SDTR1_TMRD_0            (0x1UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */
7914  #define FMC_SDTR1_TMRD_1            (0x2UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */
7915  #define FMC_SDTR1_TMRD_2            (0x4UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */
7916  #define FMC_SDTR1_TMRD_3            (0x8UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */
7917  
7918  #define FMC_SDTR1_TXSR_Pos          (4U)
7919  #define FMC_SDTR1_TXSR_Msk          (0xFUL << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */
7920  #define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
7921  #define FMC_SDTR1_TXSR_0            (0x1UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */
7922  #define FMC_SDTR1_TXSR_1            (0x2UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */
7923  #define FMC_SDTR1_TXSR_2            (0x4UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */
7924  #define FMC_SDTR1_TXSR_3            (0x8UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */
7925  
7926  #define FMC_SDTR1_TRAS_Pos          (8U)
7927  #define FMC_SDTR1_TRAS_Msk          (0xFUL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */
7928  #define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
7929  #define FMC_SDTR1_TRAS_0            (0x1UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */
7930  #define FMC_SDTR1_TRAS_1            (0x2UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */
7931  #define FMC_SDTR1_TRAS_2            (0x4UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */
7932  #define FMC_SDTR1_TRAS_3            (0x8UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */
7933  
7934  #define FMC_SDTR1_TRC_Pos           (12U)
7935  #define FMC_SDTR1_TRC_Msk           (0xFUL << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */
7936  #define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
7937  #define FMC_SDTR1_TRC_0             (0x1UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */
7938  #define FMC_SDTR1_TRC_1             (0x2UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */
7939  #define FMC_SDTR1_TRC_2             (0x4UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */
7940  
7941  #define FMC_SDTR1_TWR_Pos           (16U)
7942  #define FMC_SDTR1_TWR_Msk           (0xFUL << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */
7943  #define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
7944  #define FMC_SDTR1_TWR_0             (0x1UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */
7945  #define FMC_SDTR1_TWR_1             (0x2UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */
7946  #define FMC_SDTR1_TWR_2             (0x4UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */
7947  
7948  #define FMC_SDTR1_TRP_Pos           (20U)
7949  #define FMC_SDTR1_TRP_Msk           (0xFUL << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */
7950  #define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
7951  #define FMC_SDTR1_TRP_0             (0x1UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */
7952  #define FMC_SDTR1_TRP_1             (0x2UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */
7953  #define FMC_SDTR1_TRP_2             (0x4UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */
7954  
7955  #define FMC_SDTR1_TRCD_Pos          (24U)
7956  #define FMC_SDTR1_TRCD_Msk          (0xFUL << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */
7957  #define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
7958  #define FMC_SDTR1_TRCD_0            (0x1UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */
7959  #define FMC_SDTR1_TRCD_1            (0x2UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */
7960  #define FMC_SDTR1_TRCD_2            (0x4UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */
7961  
7962  /******************  Bit definition for FMC_SDTR2 register  ******************/
7963  #define FMC_SDTR2_TMRD_Pos          (0U)
7964  #define FMC_SDTR2_TMRD_Msk          (0xFUL << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */
7965  #define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
7966  #define FMC_SDTR2_TMRD_0            (0x1UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */
7967  #define FMC_SDTR2_TMRD_1            (0x2UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */
7968  #define FMC_SDTR2_TMRD_2            (0x4UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */
7969  #define FMC_SDTR2_TMRD_3            (0x8UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */
7970  
7971  #define FMC_SDTR2_TXSR_Pos          (4U)
7972  #define FMC_SDTR2_TXSR_Msk          (0xFUL << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */
7973  #define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
7974  #define FMC_SDTR2_TXSR_0            (0x1UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */
7975  #define FMC_SDTR2_TXSR_1            (0x2UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */
7976  #define FMC_SDTR2_TXSR_2            (0x4UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */
7977  #define FMC_SDTR2_TXSR_3            (0x8UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */
7978  
7979  #define FMC_SDTR2_TRAS_Pos          (8U)
7980  #define FMC_SDTR2_TRAS_Msk          (0xFUL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */
7981  #define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
7982  #define FMC_SDTR2_TRAS_0            (0x1UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */
7983  #define FMC_SDTR2_TRAS_1            (0x2UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */
7984  #define FMC_SDTR2_TRAS_2            (0x4UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */
7985  #define FMC_SDTR2_TRAS_3            (0x8UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */
7986  
7987  #define FMC_SDTR2_TRC_Pos           (12U)
7988  #define FMC_SDTR2_TRC_Msk           (0xFUL << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */
7989  #define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
7990  #define FMC_SDTR2_TRC_0             (0x1UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */
7991  #define FMC_SDTR2_TRC_1             (0x2UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */
7992  #define FMC_SDTR2_TRC_2             (0x4UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */
7993  
7994  #define FMC_SDTR2_TWR_Pos           (16U)
7995  #define FMC_SDTR2_TWR_Msk           (0xFUL << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */
7996  #define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
7997  #define FMC_SDTR2_TWR_0             (0x1UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */
7998  #define FMC_SDTR2_TWR_1             (0x2UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */
7999  #define FMC_SDTR2_TWR_2             (0x4UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */
8000  
8001  #define FMC_SDTR2_TRP_Pos           (20U)
8002  #define FMC_SDTR2_TRP_Msk           (0xFUL << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */
8003  #define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
8004  #define FMC_SDTR2_TRP_0             (0x1UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */
8005  #define FMC_SDTR2_TRP_1             (0x2UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */
8006  #define FMC_SDTR2_TRP_2             (0x4UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */
8007  
8008  #define FMC_SDTR2_TRCD_Pos          (24U)
8009  #define FMC_SDTR2_TRCD_Msk          (0xFUL << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */
8010  #define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
8011  #define FMC_SDTR2_TRCD_0            (0x1UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */
8012  #define FMC_SDTR2_TRCD_1            (0x2UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */
8013  #define FMC_SDTR2_TRCD_2            (0x4UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */
8014  
8015  /******************  Bit definition for FMC_SDCMR register  ******************/
8016  #define FMC_SDCMR_MODE_Pos          (0U)
8017  #define FMC_SDCMR_MODE_Msk          (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
8018  #define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */
8019  #define FMC_SDCMR_MODE_0            (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
8020  #define FMC_SDCMR_MODE_1            (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
8021  #define FMC_SDCMR_MODE_2            (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
8022  
8023  #define FMC_SDCMR_CTB2_Pos          (3U)
8024  #define FMC_SDCMR_CTB2_Msk          (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
8025  #define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */
8026  
8027  #define FMC_SDCMR_CTB1_Pos          (4U)
8028  #define FMC_SDCMR_CTB1_Msk          (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
8029  #define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */
8030  
8031  #define FMC_SDCMR_NRFS_Pos          (5U)
8032  #define FMC_SDCMR_NRFS_Msk          (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
8033  #define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */
8034  #define FMC_SDCMR_NRFS_0            (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
8035  #define FMC_SDCMR_NRFS_1            (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
8036  #define FMC_SDCMR_NRFS_2            (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
8037  #define FMC_SDCMR_NRFS_3            (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
8038  
8039  #define FMC_SDCMR_MRD_Pos           (9U)
8040  #define FMC_SDCMR_MRD_Msk           (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
8041  #define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */
8042  
8043  /******************  Bit definition for FMC_SDRTR register  ******************/
8044  #define FMC_SDRTR_CRE_Pos           (0U)
8045  #define FMC_SDRTR_CRE_Msk           (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
8046  #define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */
8047  
8048  #define FMC_SDRTR_COUNT_Pos         (1U)
8049  #define FMC_SDRTR_COUNT_Msk         (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
8050  #define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */
8051  
8052  #define FMC_SDRTR_REIE_Pos          (14U)
8053  #define FMC_SDRTR_REIE_Msk          (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
8054  #define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interupt enable */
8055  
8056  /******************  Bit definition for FMC_SDSR register  ******************/
8057  #define FMC_SDSR_RE_Pos             (0U)
8058  #define FMC_SDSR_RE_Msk             (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
8059  #define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */
8060  
8061  #define FMC_SDSR_MODES1_Pos         (1U)
8062  #define FMC_SDSR_MODES1_Msk         (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
8063  #define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */
8064  #define FMC_SDSR_MODES1_0           (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
8065  #define FMC_SDSR_MODES1_1           (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
8066  
8067  #define FMC_SDSR_MODES2_Pos         (3U)
8068  #define FMC_SDSR_MODES2_Msk         (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
8069  #define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */
8070  #define FMC_SDSR_MODES2_0           (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
8071  #define FMC_SDSR_MODES2_1           (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
8072  #define FMC_SDSR_BUSY_Pos           (5U)
8073  #define FMC_SDSR_BUSY_Msk           (0x1UL << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */
8074  #define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */
8075  
8076  /******************************************************************************/
8077  /*                                                                            */
8078  /*                            General Purpose I/O                             */
8079  /*                                                                            */
8080  /******************************************************************************/
8081  /******************  Bits definition for GPIO_MODER register  *****************/
8082  #define GPIO_MODER_MODER0_Pos            (0U)
8083  #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
8084  #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
8085  #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
8086  #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
8087  #define GPIO_MODER_MODER1_Pos            (2U)
8088  #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
8089  #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
8090  #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
8091  #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
8092  #define GPIO_MODER_MODER2_Pos            (4U)
8093  #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
8094  #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
8095  #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
8096  #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
8097  #define GPIO_MODER_MODER3_Pos            (6U)
8098  #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
8099  #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
8100  #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
8101  #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
8102  #define GPIO_MODER_MODER4_Pos            (8U)
8103  #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
8104  #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
8105  #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
8106  #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
8107  #define GPIO_MODER_MODER5_Pos            (10U)
8108  #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
8109  #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
8110  #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
8111  #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
8112  #define GPIO_MODER_MODER6_Pos            (12U)
8113  #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
8114  #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
8115  #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
8116  #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
8117  #define GPIO_MODER_MODER7_Pos            (14U)
8118  #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
8119  #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
8120  #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
8121  #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
8122  #define GPIO_MODER_MODER8_Pos            (16U)
8123  #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
8124  #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
8125  #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
8126  #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
8127  #define GPIO_MODER_MODER9_Pos            (18U)
8128  #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
8129  #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
8130  #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
8131  #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
8132  #define GPIO_MODER_MODER10_Pos           (20U)
8133  #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
8134  #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
8135  #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
8136  #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
8137  #define GPIO_MODER_MODER11_Pos           (22U)
8138  #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
8139  #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
8140  #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
8141  #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
8142  #define GPIO_MODER_MODER12_Pos           (24U)
8143  #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
8144  #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
8145  #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
8146  #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
8147  #define GPIO_MODER_MODER13_Pos           (26U)
8148  #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
8149  #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
8150  #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
8151  #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
8152  #define GPIO_MODER_MODER14_Pos           (28U)
8153  #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
8154  #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
8155  #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
8156  #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
8157  #define GPIO_MODER_MODER15_Pos           (30U)
8158  #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
8159  #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
8160  #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
8161  #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
8162  
8163  /* Legacy defines */
8164  #define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos
8165  #define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk
8166  #define GPIO_MODER_MODE0                 GPIO_MODER_MODER0
8167  #define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0
8168  #define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1
8169  #define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos
8170  #define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk
8171  #define GPIO_MODER_MODE1                 GPIO_MODER_MODER1
8172  #define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0
8173  #define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1
8174  #define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_PoS
8175  #define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk
8176  #define GPIO_MODER_MODE2                 GPIO_MODER_MODER2
8177  #define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0
8178  #define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1
8179  #define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos
8180  #define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk
8181  #define GPIO_MODER_MODE3                 GPIO_MODER_MODER3
8182  #define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0
8183  #define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1
8184  #define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos
8185  #define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk
8186  #define GPIO_MODER_MODE4                 GPIO_MODER_MODER4
8187  #define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0
8188  #define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1
8189  #define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos
8190  #define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk
8191  #define GPIO_MODER_MODE5                 GPIO_MODER_MODER5
8192  #define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0
8193  #define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1
8194  #define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos
8195  #define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk
8196  #define GPIO_MODER_MODE6                 GPIO_MODER_MODER6
8197  #define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0
8198  #define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1
8199  #define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos
8200  #define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk
8201  #define GPIO_MODER_MODE7                 GPIO_MODER_MODER7
8202  #define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0
8203  #define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1
8204  #define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos
8205  #define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk
8206  #define GPIO_MODER_MODE8                 GPIO_MODER_MODER8
8207  #define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0
8208  #define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1
8209  #define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos
8210  #define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk
8211  #define GPIO_MODER_MODE9                 GPIO_MODER_MODER9
8212  #define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0
8213  #define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1
8214  #define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos
8215  #define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk
8216  #define GPIO_MODER_MODE10                GPIO_MODER_MODER10
8217  #define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0
8218  #define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1
8219  #define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos
8220  #define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk
8221  #define GPIO_MODER_MODE11                GPIO_MODER_MODER11
8222  #define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0
8223  #define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1
8224  #define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos
8225  #define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk
8226  #define GPIO_MODER_MODE12                GPIO_MODER_MODER12
8227  #define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0
8228  #define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1
8229  #define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos
8230  #define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk
8231  #define GPIO_MODER_MODE13                GPIO_MODER_MODER13
8232  #define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0
8233  #define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1
8234  #define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos
8235  #define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk
8236  #define GPIO_MODER_MODE14                GPIO_MODER_MODER14
8237  #define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0
8238  #define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1
8239  #define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos
8240  #define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk
8241  #define GPIO_MODER_MODE15                GPIO_MODER_MODER15
8242  #define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0
8243  #define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1
8244  
8245  /******************  Bits definition for GPIO_OTYPER register  ****************/
8246  #define GPIO_OTYPER_OT0_Pos              (0U)
8247  #define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
8248  #define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk
8249  #define GPIO_OTYPER_OT1_Pos              (1U)
8250  #define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
8251  #define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk
8252  #define GPIO_OTYPER_OT2_Pos              (2U)
8253  #define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
8254  #define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk
8255  #define GPIO_OTYPER_OT3_Pos              (3U)
8256  #define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
8257  #define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk
8258  #define GPIO_OTYPER_OT4_Pos              (4U)
8259  #define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
8260  #define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk
8261  #define GPIO_OTYPER_OT5_Pos              (5U)
8262  #define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
8263  #define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk
8264  #define GPIO_OTYPER_OT6_Pos              (6U)
8265  #define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
8266  #define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk
8267  #define GPIO_OTYPER_OT7_Pos              (7U)
8268  #define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
8269  #define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk
8270  #define GPIO_OTYPER_OT8_Pos              (8U)
8271  #define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
8272  #define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk
8273  #define GPIO_OTYPER_OT9_Pos              (9U)
8274  #define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
8275  #define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk
8276  #define GPIO_OTYPER_OT10_Pos             (10U)
8277  #define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
8278  #define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk
8279  #define GPIO_OTYPER_OT11_Pos             (11U)
8280  #define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
8281  #define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk
8282  #define GPIO_OTYPER_OT12_Pos             (12U)
8283  #define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
8284  #define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk
8285  #define GPIO_OTYPER_OT13_Pos             (13U)
8286  #define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
8287  #define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk
8288  #define GPIO_OTYPER_OT14_Pos             (14U)
8289  #define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
8290  #define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk
8291  #define GPIO_OTYPER_OT15_Pos             (15U)
8292  #define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
8293  #define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk
8294  
8295  /* Legacy defines */
8296  #define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
8297  #define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
8298  #define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
8299  #define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
8300  #define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
8301  #define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
8302  #define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
8303  #define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
8304  #define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
8305  #define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
8306  #define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
8307  #define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
8308  #define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
8309  #define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
8310  #define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
8311  #define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
8312  
8313  /******************  Bits definition for GPIO_OSPEEDR register  ***************/
8314  #define GPIO_OSPEEDR_OSPEED0_Pos         (0U)
8315  #define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
8316  #define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk
8317  #define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
8318  #define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
8319  #define GPIO_OSPEEDR_OSPEED1_Pos         (2U)
8320  #define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
8321  #define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk
8322  #define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
8323  #define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
8324  #define GPIO_OSPEEDR_OSPEED2_Pos         (4U)
8325  #define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
8326  #define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk
8327  #define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
8328  #define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
8329  #define GPIO_OSPEEDR_OSPEED3_Pos         (6U)
8330  #define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
8331  #define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk
8332  #define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
8333  #define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
8334  #define GPIO_OSPEEDR_OSPEED4_Pos         (8U)
8335  #define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
8336  #define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk
8337  #define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
8338  #define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
8339  #define GPIO_OSPEEDR_OSPEED5_Pos         (10U)
8340  #define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
8341  #define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk
8342  #define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
8343  #define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
8344  #define GPIO_OSPEEDR_OSPEED6_Pos         (12U)
8345  #define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
8346  #define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk
8347  #define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
8348  #define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
8349  #define GPIO_OSPEEDR_OSPEED7_Pos         (14U)
8350  #define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
8351  #define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk
8352  #define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
8353  #define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
8354  #define GPIO_OSPEEDR_OSPEED8_Pos         (16U)
8355  #define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
8356  #define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk
8357  #define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
8358  #define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
8359  #define GPIO_OSPEEDR_OSPEED9_Pos         (18U)
8360  #define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
8361  #define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk
8362  #define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
8363  #define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
8364  #define GPIO_OSPEEDR_OSPEED10_Pos        (20U)
8365  #define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
8366  #define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk
8367  #define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
8368  #define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
8369  #define GPIO_OSPEEDR_OSPEED11_Pos        (22U)
8370  #define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
8371  #define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk
8372  #define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
8373  #define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
8374  #define GPIO_OSPEEDR_OSPEED12_Pos        (24U)
8375  #define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
8376  #define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk
8377  #define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
8378  #define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
8379  #define GPIO_OSPEEDR_OSPEED13_Pos        (26U)
8380  #define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
8381  #define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk
8382  #define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
8383  #define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
8384  #define GPIO_OSPEEDR_OSPEED14_Pos        (28U)
8385  #define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
8386  #define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk
8387  #define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
8388  #define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
8389  #define GPIO_OSPEEDR_OSPEED15_Pos        (30U)
8390  #define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
8391  #define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk
8392  #define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
8393  #define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
8394  
8395  /* Legacy defines */
8396  #define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
8397  #define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
8398  #define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
8399  #define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
8400  #define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
8401  #define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
8402  #define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
8403  #define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
8404  #define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
8405  #define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
8406  #define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
8407  #define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
8408  #define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
8409  #define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
8410  #define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
8411  #define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
8412  #define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
8413  #define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
8414  #define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
8415  #define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
8416  #define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
8417  #define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
8418  #define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
8419  #define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
8420  #define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
8421  #define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
8422  #define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
8423  #define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
8424  #define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
8425  #define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
8426  #define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
8427  #define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
8428  #define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
8429  #define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
8430  #define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
8431  #define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
8432  #define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
8433  #define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
8434  #define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
8435  #define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
8436  #define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
8437  #define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
8438  #define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
8439  #define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
8440  #define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
8441  #define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
8442  #define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
8443  #define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
8444  
8445  /******************  Bits definition for GPIO_PUPDR register  *****************/
8446  #define GPIO_PUPDR_PUPD0_Pos             (0U)
8447  #define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
8448  #define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk
8449  #define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
8450  #define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
8451  #define GPIO_PUPDR_PUPD1_Pos             (2U)
8452  #define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
8453  #define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk
8454  #define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
8455  #define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
8456  #define GPIO_PUPDR_PUPD2_Pos             (4U)
8457  #define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
8458  #define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk
8459  #define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
8460  #define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
8461  #define GPIO_PUPDR_PUPD3_Pos             (6U)
8462  #define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
8463  #define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk
8464  #define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
8465  #define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
8466  #define GPIO_PUPDR_PUPD4_Pos             (8U)
8467  #define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
8468  #define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk
8469  #define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
8470  #define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
8471  #define GPIO_PUPDR_PUPD5_Pos             (10U)
8472  #define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
8473  #define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk
8474  #define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
8475  #define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
8476  #define GPIO_PUPDR_PUPD6_Pos             (12U)
8477  #define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
8478  #define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk
8479  #define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
8480  #define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
8481  #define GPIO_PUPDR_PUPD7_Pos             (14U)
8482  #define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
8483  #define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk
8484  #define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
8485  #define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
8486  #define GPIO_PUPDR_PUPD8_Pos             (16U)
8487  #define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
8488  #define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk
8489  #define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
8490  #define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
8491  #define GPIO_PUPDR_PUPD9_Pos             (18U)
8492  #define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
8493  #define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk
8494  #define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
8495  #define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
8496  #define GPIO_PUPDR_PUPD10_Pos            (20U)
8497  #define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
8498  #define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk
8499  #define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
8500  #define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
8501  #define GPIO_PUPDR_PUPD11_Pos            (22U)
8502  #define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
8503  #define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk
8504  #define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
8505  #define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
8506  #define GPIO_PUPDR_PUPD12_Pos            (24U)
8507  #define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
8508  #define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk
8509  #define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
8510  #define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
8511  #define GPIO_PUPDR_PUPD13_Pos            (26U)
8512  #define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
8513  #define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk
8514  #define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
8515  #define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
8516  #define GPIO_PUPDR_PUPD14_Pos            (28U)
8517  #define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
8518  #define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk
8519  #define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
8520  #define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
8521  #define GPIO_PUPDR_PUPD15_Pos            (30U)
8522  #define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
8523  #define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk
8524  #define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
8525  #define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
8526  
8527  /* Legacy defines */
8528  #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
8529  #define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
8530  #define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
8531  #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
8532  #define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
8533  #define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
8534  #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
8535  #define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
8536  #define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
8537  #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
8538  #define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
8539  #define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
8540  #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
8541  #define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
8542  #define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
8543  #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
8544  #define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
8545  #define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
8546  #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
8547  #define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
8548  #define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
8549  #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
8550  #define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
8551  #define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
8552  #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
8553  #define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
8554  #define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
8555  #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
8556  #define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
8557  #define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
8558  #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
8559  #define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
8560  #define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
8561  #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
8562  #define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
8563  #define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
8564  #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
8565  #define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
8566  #define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
8567  #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
8568  #define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
8569  #define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
8570  #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
8571  #define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
8572  #define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
8573  #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
8574  #define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
8575  #define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
8576  
8577  /******************  Bits definition for GPIO_IDR register  *******************/
8578  #define GPIO_IDR_ID0_Pos                 (0U)
8579  #define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
8580  #define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk
8581  #define GPIO_IDR_ID1_Pos                 (1U)
8582  #define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
8583  #define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk
8584  #define GPIO_IDR_ID2_Pos                 (2U)
8585  #define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
8586  #define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk
8587  #define GPIO_IDR_ID3_Pos                 (3U)
8588  #define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
8589  #define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk
8590  #define GPIO_IDR_ID4_Pos                 (4U)
8591  #define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
8592  #define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk
8593  #define GPIO_IDR_ID5_Pos                 (5U)
8594  #define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
8595  #define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk
8596  #define GPIO_IDR_ID6_Pos                 (6U)
8597  #define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
8598  #define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk
8599  #define GPIO_IDR_ID7_Pos                 (7U)
8600  #define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
8601  #define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk
8602  #define GPIO_IDR_ID8_Pos                 (8U)
8603  #define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
8604  #define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk
8605  #define GPIO_IDR_ID9_Pos                 (9U)
8606  #define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
8607  #define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk
8608  #define GPIO_IDR_ID10_Pos                (10U)
8609  #define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
8610  #define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk
8611  #define GPIO_IDR_ID11_Pos                (11U)
8612  #define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
8613  #define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk
8614  #define GPIO_IDR_ID12_Pos                (12U)
8615  #define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
8616  #define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk
8617  #define GPIO_IDR_ID13_Pos                (13U)
8618  #define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
8619  #define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk
8620  #define GPIO_IDR_ID14_Pos                (14U)
8621  #define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
8622  #define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk
8623  #define GPIO_IDR_ID15_Pos                (15U)
8624  #define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
8625  #define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk
8626  
8627  /* Legacy defines */
8628  #define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
8629  #define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
8630  #define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
8631  #define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
8632  #define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
8633  #define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
8634  #define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
8635  #define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
8636  #define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
8637  #define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
8638  #define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
8639  #define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
8640  #define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
8641  #define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
8642  #define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
8643  #define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
8644  
8645  /******************  Bits definition for GPIO_ODR register  *******************/
8646  #define GPIO_ODR_OD0_Pos                 (0U)
8647  #define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
8648  #define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk
8649  #define GPIO_ODR_OD1_Pos                 (1U)
8650  #define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
8651  #define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk
8652  #define GPIO_ODR_OD2_Pos                 (2U)
8653  #define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
8654  #define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk
8655  #define GPIO_ODR_OD3_Pos                 (3U)
8656  #define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
8657  #define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk
8658  #define GPIO_ODR_OD4_Pos                 (4U)
8659  #define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
8660  #define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk
8661  #define GPIO_ODR_OD5_Pos                 (5U)
8662  #define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
8663  #define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk
8664  #define GPIO_ODR_OD6_Pos                 (6U)
8665  #define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
8666  #define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk
8667  #define GPIO_ODR_OD7_Pos                 (7U)
8668  #define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
8669  #define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk
8670  #define GPIO_ODR_OD8_Pos                 (8U)
8671  #define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
8672  #define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk
8673  #define GPIO_ODR_OD9_Pos                 (9U)
8674  #define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
8675  #define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk
8676  #define GPIO_ODR_OD10_Pos                (10U)
8677  #define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
8678  #define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk
8679  #define GPIO_ODR_OD11_Pos                (11U)
8680  #define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
8681  #define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk
8682  #define GPIO_ODR_OD12_Pos                (12U)
8683  #define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
8684  #define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk
8685  #define GPIO_ODR_OD13_Pos                (13U)
8686  #define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
8687  #define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk
8688  #define GPIO_ODR_OD14_Pos                (14U)
8689  #define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
8690  #define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk
8691  #define GPIO_ODR_OD15_Pos                (15U)
8692  #define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
8693  #define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk
8694  /* Legacy defines */
8695  #define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
8696  #define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
8697  #define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
8698  #define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
8699  #define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
8700  #define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
8701  #define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
8702  #define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
8703  #define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
8704  #define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
8705  #define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
8706  #define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
8707  #define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
8708  #define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
8709  #define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
8710  #define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
8711  
8712  /******************  Bits definition for GPIO_BSRR register  ******************/
8713  #define GPIO_BSRR_BS0_Pos                (0U)
8714  #define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
8715  #define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk
8716  #define GPIO_BSRR_BS1_Pos                (1U)
8717  #define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
8718  #define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk
8719  #define GPIO_BSRR_BS2_Pos                (2U)
8720  #define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
8721  #define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk
8722  #define GPIO_BSRR_BS3_Pos                (3U)
8723  #define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
8724  #define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk
8725  #define GPIO_BSRR_BS4_Pos                (4U)
8726  #define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
8727  #define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk
8728  #define GPIO_BSRR_BS5_Pos                (5U)
8729  #define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
8730  #define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk
8731  #define GPIO_BSRR_BS6_Pos                (6U)
8732  #define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
8733  #define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk
8734  #define GPIO_BSRR_BS7_Pos                (7U)
8735  #define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
8736  #define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk
8737  #define GPIO_BSRR_BS8_Pos                (8U)
8738  #define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
8739  #define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk
8740  #define GPIO_BSRR_BS9_Pos                (9U)
8741  #define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
8742  #define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk
8743  #define GPIO_BSRR_BS10_Pos               (10U)
8744  #define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
8745  #define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk
8746  #define GPIO_BSRR_BS11_Pos               (11U)
8747  #define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
8748  #define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk
8749  #define GPIO_BSRR_BS12_Pos               (12U)
8750  #define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
8751  #define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk
8752  #define GPIO_BSRR_BS13_Pos               (13U)
8753  #define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
8754  #define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk
8755  #define GPIO_BSRR_BS14_Pos               (14U)
8756  #define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
8757  #define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk
8758  #define GPIO_BSRR_BS15_Pos               (15U)
8759  #define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
8760  #define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk
8761  #define GPIO_BSRR_BR0_Pos                (16U)
8762  #define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
8763  #define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk
8764  #define GPIO_BSRR_BR1_Pos                (17U)
8765  #define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
8766  #define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk
8767  #define GPIO_BSRR_BR2_Pos                (18U)
8768  #define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
8769  #define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk
8770  #define GPIO_BSRR_BR3_Pos                (19U)
8771  #define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
8772  #define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk
8773  #define GPIO_BSRR_BR4_Pos                (20U)
8774  #define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
8775  #define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk
8776  #define GPIO_BSRR_BR5_Pos                (21U)
8777  #define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
8778  #define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk
8779  #define GPIO_BSRR_BR6_Pos                (22U)
8780  #define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
8781  #define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk
8782  #define GPIO_BSRR_BR7_Pos                (23U)
8783  #define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
8784  #define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk
8785  #define GPIO_BSRR_BR8_Pos                (24U)
8786  #define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
8787  #define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk
8788  #define GPIO_BSRR_BR9_Pos                (25U)
8789  #define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
8790  #define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk
8791  #define GPIO_BSRR_BR10_Pos               (26U)
8792  #define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
8793  #define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk
8794  #define GPIO_BSRR_BR11_Pos               (27U)
8795  #define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
8796  #define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk
8797  #define GPIO_BSRR_BR12_Pos               (28U)
8798  #define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
8799  #define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk
8800  #define GPIO_BSRR_BR13_Pos               (29U)
8801  #define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
8802  #define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk
8803  #define GPIO_BSRR_BR14_Pos               (30U)
8804  #define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
8805  #define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk
8806  #define GPIO_BSRR_BR15_Pos               (31U)
8807  #define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
8808  #define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk
8809  
8810  /* Legacy defines */
8811  #define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
8812  #define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
8813  #define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
8814  #define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
8815  #define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
8816  #define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
8817  #define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
8818  #define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
8819  #define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
8820  #define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
8821  #define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
8822  #define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
8823  #define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
8824  #define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
8825  #define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
8826  #define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
8827  #define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
8828  #define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
8829  #define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
8830  #define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
8831  #define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
8832  #define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
8833  #define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
8834  #define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
8835  #define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
8836  #define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
8837  #define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
8838  #define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
8839  #define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
8840  #define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
8841  #define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
8842  #define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
8843  #define GPIO_BRR_BR0                     GPIO_BSRR_BR0
8844  #define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
8845  #define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
8846  #define GPIO_BRR_BR1                     GPIO_BSRR_BR1
8847  #define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
8848  #define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
8849  #define GPIO_BRR_BR2                     GPIO_BSRR_BR2
8850  #define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
8851  #define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
8852  #define GPIO_BRR_BR3                     GPIO_BSRR_BR3
8853  #define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
8854  #define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
8855  #define GPIO_BRR_BR4                     GPIO_BSRR_BR4
8856  #define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
8857  #define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
8858  #define GPIO_BRR_BR5                     GPIO_BSRR_BR5
8859  #define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
8860  #define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
8861  #define GPIO_BRR_BR6                     GPIO_BSRR_BR6
8862  #define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
8863  #define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
8864  #define GPIO_BRR_BR7                     GPIO_BSRR_BR7
8865  #define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
8866  #define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
8867  #define GPIO_BRR_BR8                     GPIO_BSRR_BR8
8868  #define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
8869  #define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
8870  #define GPIO_BRR_BR9                     GPIO_BSRR_BR9
8871  #define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
8872  #define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
8873  #define GPIO_BRR_BR10                    GPIO_BSRR_BR10
8874  #define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
8875  #define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
8876  #define GPIO_BRR_BR11                    GPIO_BSRR_BR11
8877  #define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
8878  #define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
8879  #define GPIO_BRR_BR12                    GPIO_BSRR_BR12
8880  #define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
8881  #define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
8882  #define GPIO_BRR_BR13                    GPIO_BSRR_BR13
8883  #define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
8884  #define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
8885  #define GPIO_BRR_BR14                    GPIO_BSRR_BR14
8886  #define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
8887  #define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
8888  #define GPIO_BRR_BR15                    GPIO_BSRR_BR15
8889  #define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
8890  #define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk
8891  /****************** Bit definition for GPIO_LCKR register *********************/
8892  #define GPIO_LCKR_LCK0_Pos               (0U)
8893  #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
8894  #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
8895  #define GPIO_LCKR_LCK1_Pos               (1U)
8896  #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
8897  #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
8898  #define GPIO_LCKR_LCK2_Pos               (2U)
8899  #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
8900  #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
8901  #define GPIO_LCKR_LCK3_Pos               (3U)
8902  #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
8903  #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
8904  #define GPIO_LCKR_LCK4_Pos               (4U)
8905  #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
8906  #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
8907  #define GPIO_LCKR_LCK5_Pos               (5U)
8908  #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
8909  #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
8910  #define GPIO_LCKR_LCK6_Pos               (6U)
8911  #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
8912  #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
8913  #define GPIO_LCKR_LCK7_Pos               (7U)
8914  #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
8915  #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
8916  #define GPIO_LCKR_LCK8_Pos               (8U)
8917  #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
8918  #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
8919  #define GPIO_LCKR_LCK9_Pos               (9U)
8920  #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
8921  #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
8922  #define GPIO_LCKR_LCK10_Pos              (10U)
8923  #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
8924  #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
8925  #define GPIO_LCKR_LCK11_Pos              (11U)
8926  #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
8927  #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
8928  #define GPIO_LCKR_LCK12_Pos              (12U)
8929  #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
8930  #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
8931  #define GPIO_LCKR_LCK13_Pos              (13U)
8932  #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
8933  #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
8934  #define GPIO_LCKR_LCK14_Pos              (14U)
8935  #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
8936  #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
8937  #define GPIO_LCKR_LCK15_Pos              (15U)
8938  #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
8939  #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
8940  #define GPIO_LCKR_LCKK_Pos               (16U)
8941  #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
8942  #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
8943  /****************** Bit definition for GPIO_AFRL register *********************/
8944  #define GPIO_AFRL_AFSEL0_Pos             (0U)
8945  #define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
8946  #define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk
8947  #define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
8948  #define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
8949  #define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
8950  #define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
8951  #define GPIO_AFRL_AFSEL1_Pos             (4U)
8952  #define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
8953  #define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk
8954  #define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
8955  #define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
8956  #define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
8957  #define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
8958  #define GPIO_AFRL_AFSEL2_Pos             (8U)
8959  #define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
8960  #define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk
8961  #define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
8962  #define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
8963  #define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
8964  #define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
8965  #define GPIO_AFRL_AFSEL3_Pos             (12U)
8966  #define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
8967  #define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk
8968  #define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
8969  #define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
8970  #define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
8971  #define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
8972  #define GPIO_AFRL_AFSEL4_Pos             (16U)
8973  #define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
8974  #define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk
8975  #define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
8976  #define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
8977  #define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
8978  #define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
8979  #define GPIO_AFRL_AFSEL5_Pos             (20U)
8980  #define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
8981  #define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk
8982  #define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
8983  #define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
8984  #define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
8985  #define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
8986  #define GPIO_AFRL_AFSEL6_Pos             (24U)
8987  #define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
8988  #define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk
8989  #define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
8990  #define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
8991  #define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
8992  #define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
8993  #define GPIO_AFRL_AFSEL7_Pos             (28U)
8994  #define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
8995  #define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk
8996  #define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
8997  #define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
8998  #define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
8999  #define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
9000  
9001  /* Legacy defines */
9002  #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
9003  #define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
9004  #define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
9005  #define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
9006  #define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
9007  #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
9008  #define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
9009  #define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
9010  #define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
9011  #define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
9012  #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
9013  #define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
9014  #define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
9015  #define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
9016  #define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
9017  #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
9018  #define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
9019  #define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
9020  #define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
9021  #define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
9022  #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
9023  #define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
9024  #define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
9025  #define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
9026  #define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
9027  #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
9028  #define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
9029  #define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
9030  #define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
9031  #define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
9032  #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
9033  #define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
9034  #define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
9035  #define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
9036  #define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
9037  #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
9038  #define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
9039  #define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
9040  #define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
9041  #define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
9042  
9043  /****************** Bit definition for GPIO_AFRH register *********************/
9044  #define GPIO_AFRH_AFSEL8_Pos             (0U)
9045  #define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
9046  #define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk
9047  #define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
9048  #define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
9049  #define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
9050  #define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
9051  #define GPIO_AFRH_AFSEL9_Pos             (4U)
9052  #define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
9053  #define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk
9054  #define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
9055  #define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
9056  #define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
9057  #define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
9058  #define GPIO_AFRH_AFSEL10_Pos            (8U)
9059  #define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
9060  #define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk
9061  #define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
9062  #define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
9063  #define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
9064  #define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
9065  #define GPIO_AFRH_AFSEL11_Pos            (12U)
9066  #define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
9067  #define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk
9068  #define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
9069  #define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
9070  #define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
9071  #define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
9072  #define GPIO_AFRH_AFSEL12_Pos            (16U)
9073  #define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
9074  #define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk
9075  #define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
9076  #define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
9077  #define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
9078  #define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
9079  #define GPIO_AFRH_AFSEL13_Pos            (20U)
9080  #define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
9081  #define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk
9082  #define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
9083  #define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
9084  #define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
9085  #define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
9086  #define GPIO_AFRH_AFSEL14_Pos            (24U)
9087  #define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
9088  #define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk
9089  #define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
9090  #define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
9091  #define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
9092  #define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
9093  #define GPIO_AFRH_AFSEL15_Pos            (28U)
9094  #define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
9095  #define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk
9096  #define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
9097  #define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
9098  #define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
9099  #define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
9100  
9101  /* Legacy defines */
9102  #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
9103  #define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
9104  #define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
9105  #define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
9106  #define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
9107  #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
9108  #define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
9109  #define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
9110  #define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
9111  #define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
9112  #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
9113  #define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
9114  #define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
9115  #define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
9116  #define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
9117  #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
9118  #define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
9119  #define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
9120  #define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
9121  #define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
9122  #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
9123  #define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
9124  #define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
9125  #define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
9126  #define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
9127  #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
9128  #define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
9129  #define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
9130  #define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
9131  #define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
9132  #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
9133  #define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
9134  #define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
9135  #define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
9136  #define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
9137  #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
9138  #define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
9139  #define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
9140  #define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
9141  #define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
9142  
9143  
9144  /******************************************************************************/
9145  /*                                                                            */
9146  /*                      Inter-integrated Circuit Interface                    */
9147  /*                                                                            */
9148  /******************************************************************************/
9149  /*******************  Bit definition for I2C_CR1 register  ********************/
9150  #define I2C_CR1_PE_Pos            (0U)
9151  #define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
9152  #define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
9153  #define I2C_CR1_SMBUS_Pos         (1U)
9154  #define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
9155  #define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
9156  #define I2C_CR1_SMBTYPE_Pos       (3U)
9157  #define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
9158  #define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
9159  #define I2C_CR1_ENARP_Pos         (4U)
9160  #define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
9161  #define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
9162  #define I2C_CR1_ENPEC_Pos         (5U)
9163  #define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
9164  #define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
9165  #define I2C_CR1_ENGC_Pos          (6U)
9166  #define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
9167  #define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
9168  #define I2C_CR1_NOSTRETCH_Pos     (7U)
9169  #define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
9170  #define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
9171  #define I2C_CR1_START_Pos         (8U)
9172  #define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
9173  #define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
9174  #define I2C_CR1_STOP_Pos          (9U)
9175  #define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
9176  #define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
9177  #define I2C_CR1_ACK_Pos           (10U)
9178  #define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
9179  #define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
9180  #define I2C_CR1_POS_Pos           (11U)
9181  #define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
9182  #define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
9183  #define I2C_CR1_PEC_Pos           (12U)
9184  #define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
9185  #define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
9186  #define I2C_CR1_ALERT_Pos         (13U)
9187  #define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
9188  #define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
9189  #define I2C_CR1_SWRST_Pos         (15U)
9190  #define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
9191  #define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
9192  
9193  /*******************  Bit definition for I2C_CR2 register  ********************/
9194  #define I2C_CR2_FREQ_Pos          (0U)
9195  #define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
9196  #define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
9197  #define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
9198  #define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
9199  #define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
9200  #define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
9201  #define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
9202  #define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
9203  
9204  #define I2C_CR2_ITERREN_Pos       (8U)
9205  #define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
9206  #define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
9207  #define I2C_CR2_ITEVTEN_Pos       (9U)
9208  #define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
9209  #define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
9210  #define I2C_CR2_ITBUFEN_Pos       (10U)
9211  #define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
9212  #define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
9213  #define I2C_CR2_DMAEN_Pos         (11U)
9214  #define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
9215  #define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
9216  #define I2C_CR2_LAST_Pos          (12U)
9217  #define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
9218  #define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
9219  
9220  /*******************  Bit definition for I2C_OAR1 register  *******************/
9221  #define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
9222  #define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
9223  
9224  #define I2C_OAR1_ADD0_Pos         (0U)
9225  #define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
9226  #define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
9227  #define I2C_OAR1_ADD1_Pos         (1U)
9228  #define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
9229  #define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
9230  #define I2C_OAR1_ADD2_Pos         (2U)
9231  #define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
9232  #define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
9233  #define I2C_OAR1_ADD3_Pos         (3U)
9234  #define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
9235  #define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
9236  #define I2C_OAR1_ADD4_Pos         (4U)
9237  #define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
9238  #define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
9239  #define I2C_OAR1_ADD5_Pos         (5U)
9240  #define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
9241  #define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
9242  #define I2C_OAR1_ADD6_Pos         (6U)
9243  #define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
9244  #define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
9245  #define I2C_OAR1_ADD7_Pos         (7U)
9246  #define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
9247  #define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
9248  #define I2C_OAR1_ADD8_Pos         (8U)
9249  #define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
9250  #define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
9251  #define I2C_OAR1_ADD9_Pos         (9U)
9252  #define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
9253  #define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
9254  
9255  #define I2C_OAR1_ADDMODE_Pos      (15U)
9256  #define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
9257  #define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
9258  
9259  /*******************  Bit definition for I2C_OAR2 register  *******************/
9260  #define I2C_OAR2_ENDUAL_Pos       (0U)
9261  #define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
9262  #define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
9263  #define I2C_OAR2_ADD2_Pos         (1U)
9264  #define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
9265  #define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
9266  
9267  /********************  Bit definition for I2C_DR register  ********************/
9268  #define I2C_DR_DR_Pos             (0U)
9269  #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
9270  #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
9271  
9272  /*******************  Bit definition for I2C_SR1 register  ********************/
9273  #define I2C_SR1_SB_Pos            (0U)
9274  #define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
9275  #define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
9276  #define I2C_SR1_ADDR_Pos          (1U)
9277  #define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
9278  #define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
9279  #define I2C_SR1_BTF_Pos           (2U)
9280  #define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
9281  #define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
9282  #define I2C_SR1_ADD10_Pos         (3U)
9283  #define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
9284  #define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
9285  #define I2C_SR1_STOPF_Pos         (4U)
9286  #define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
9287  #define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
9288  #define I2C_SR1_RXNE_Pos          (6U)
9289  #define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
9290  #define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
9291  #define I2C_SR1_TXE_Pos           (7U)
9292  #define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
9293  #define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
9294  #define I2C_SR1_BERR_Pos          (8U)
9295  #define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
9296  #define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
9297  #define I2C_SR1_ARLO_Pos          (9U)
9298  #define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
9299  #define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
9300  #define I2C_SR1_AF_Pos            (10U)
9301  #define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
9302  #define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
9303  #define I2C_SR1_OVR_Pos           (11U)
9304  #define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
9305  #define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
9306  #define I2C_SR1_PECERR_Pos        (12U)
9307  #define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
9308  #define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
9309  #define I2C_SR1_TIMEOUT_Pos       (14U)
9310  #define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
9311  #define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
9312  #define I2C_SR1_SMBALERT_Pos      (15U)
9313  #define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
9314  #define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
9315  
9316  /*******************  Bit definition for I2C_SR2 register  ********************/
9317  #define I2C_SR2_MSL_Pos           (0U)
9318  #define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
9319  #define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
9320  #define I2C_SR2_BUSY_Pos          (1U)
9321  #define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
9322  #define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
9323  #define I2C_SR2_TRA_Pos           (2U)
9324  #define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
9325  #define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
9326  #define I2C_SR2_GENCALL_Pos       (4U)
9327  #define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
9328  #define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
9329  #define I2C_SR2_SMBDEFAULT_Pos    (5U)
9330  #define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
9331  #define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
9332  #define I2C_SR2_SMBHOST_Pos       (6U)
9333  #define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
9334  #define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
9335  #define I2C_SR2_DUALF_Pos         (7U)
9336  #define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
9337  #define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
9338  #define I2C_SR2_PEC_Pos           (8U)
9339  #define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
9340  #define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
9341  
9342  /*******************  Bit definition for I2C_CCR register  ********************/
9343  #define I2C_CCR_CCR_Pos           (0U)
9344  #define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
9345  #define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
9346  #define I2C_CCR_DUTY_Pos          (14U)
9347  #define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
9348  #define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
9349  #define I2C_CCR_FS_Pos            (15U)
9350  #define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
9351  #define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
9352  
9353  /******************  Bit definition for I2C_TRISE register  *******************/
9354  #define I2C_TRISE_TRISE_Pos       (0U)
9355  #define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
9356  #define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
9357  
9358  /******************  Bit definition for I2C_FLTR register  *******************/
9359  #define I2C_FLTR_DNF_Pos          (0U)
9360  #define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */
9361  #define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */
9362  #define I2C_FLTR_ANOFF_Pos        (4U)
9363  #define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */
9364  #define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */
9365  
9366  /******************************************************************************/
9367  /*                                                                            */
9368  /*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
9369  /*                                                                            */
9370  /******************************************************************************/
9371  /*******************  Bit definition for I2C_CR1 register  *******************/
9372  #define FMPI2C_CR1_PE_Pos               (0U)
9373  #define FMPI2C_CR1_PE_Msk               (0x1UL << FMPI2C_CR1_PE_Pos)            /*!< 0x00000001 */
9374  #define FMPI2C_CR1_PE                   FMPI2C_CR1_PE_Msk                      /*!< Peripheral enable                   */
9375  #define FMPI2C_CR1_TXIE_Pos             (1U)
9376  #define FMPI2C_CR1_TXIE_Msk             (0x1UL << FMPI2C_CR1_TXIE_Pos)          /*!< 0x00000002 */
9377  #define FMPI2C_CR1_TXIE                 FMPI2C_CR1_TXIE_Msk                    /*!< TX interrupt enable                 */
9378  #define FMPI2C_CR1_RXIE_Pos             (2U)
9379  #define FMPI2C_CR1_RXIE_Msk             (0x1UL << FMPI2C_CR1_RXIE_Pos)          /*!< 0x00000004 */
9380  #define FMPI2C_CR1_RXIE                 FMPI2C_CR1_RXIE_Msk                    /*!< RX interrupt enable                 */
9381  #define FMPI2C_CR1_ADDRIE_Pos           (3U)
9382  #define FMPI2C_CR1_ADDRIE_Msk           (0x1UL << FMPI2C_CR1_ADDRIE_Pos)        /*!< 0x00000008 */
9383  #define FMPI2C_CR1_ADDRIE               FMPI2C_CR1_ADDRIE_Msk                  /*!< Address match interrupt enable      */
9384  #define FMPI2C_CR1_NACKIE_Pos           (4U)
9385  #define FMPI2C_CR1_NACKIE_Msk           (0x1UL << FMPI2C_CR1_NACKIE_Pos)        /*!< 0x00000010 */
9386  #define FMPI2C_CR1_NACKIE               FMPI2C_CR1_NACKIE_Msk                  /*!< NACK received interrupt enable      */
9387  #define FMPI2C_CR1_STOPIE_Pos           (5U)
9388  #define FMPI2C_CR1_STOPIE_Msk           (0x1UL << FMPI2C_CR1_STOPIE_Pos)        /*!< 0x00000020 */
9389  #define FMPI2C_CR1_STOPIE               FMPI2C_CR1_STOPIE_Msk                  /*!< STOP detection interrupt enable     */
9390  #define FMPI2C_CR1_TCIE_Pos             (6U)
9391  #define FMPI2C_CR1_TCIE_Msk             (0x1UL << FMPI2C_CR1_TCIE_Pos)          /*!< 0x00000040 */
9392  #define FMPI2C_CR1_TCIE                 FMPI2C_CR1_TCIE_Msk                    /*!< Transfer complete interrupt enable  */
9393  #define FMPI2C_CR1_ERRIE_Pos            (7U)
9394  #define FMPI2C_CR1_ERRIE_Msk            (0x1UL << FMPI2C_CR1_ERRIE_Pos)         /*!< 0x00000080 */
9395  #define FMPI2C_CR1_ERRIE                FMPI2C_CR1_ERRIE_Msk                   /*!< Errors interrupt enable             */
9396  #define FMPI2C_CR1_DNF_Pos              (8U)
9397  #define FMPI2C_CR1_DNF_Msk              (0xFUL << FMPI2C_CR1_DNF_Pos)           /*!< 0x00000F00 */
9398  #define FMPI2C_CR1_DNF                  FMPI2C_CR1_DNF_Msk                     /*!< Digital noise filter                */
9399  #define FMPI2C_CR1_ANFOFF_Pos           (12U)
9400  #define FMPI2C_CR1_ANFOFF_Msk           (0x1UL << FMPI2C_CR1_ANFOFF_Pos)        /*!< 0x00001000 */
9401  #define FMPI2C_CR1_ANFOFF               FMPI2C_CR1_ANFOFF_Msk                  /*!< Analog noise filter OFF             */
9402  #define FMPI2C_CR1_TXDMAEN_Pos          (14U)
9403  #define FMPI2C_CR1_TXDMAEN_Msk          (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)       /*!< 0x00004000 */
9404  #define FMPI2C_CR1_TXDMAEN              FMPI2C_CR1_TXDMAEN_Msk                 /*!< DMA transmission requests enable    */
9405  #define FMPI2C_CR1_RXDMAEN_Pos          (15U)
9406  #define FMPI2C_CR1_RXDMAEN_Msk          (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)       /*!< 0x00008000 */
9407  #define FMPI2C_CR1_RXDMAEN              FMPI2C_CR1_RXDMAEN_Msk                 /*!< DMA reception requests enable       */
9408  #define FMPI2C_CR1_SBC_Pos              (16U)
9409  #define FMPI2C_CR1_SBC_Msk              (0x1UL << FMPI2C_CR1_SBC_Pos)           /*!< 0x00010000 */
9410  #define FMPI2C_CR1_SBC                  FMPI2C_CR1_SBC_Msk                     /*!< Slave byte control                  */
9411  #define FMPI2C_CR1_NOSTRETCH_Pos        (17U)
9412  #define FMPI2C_CR1_NOSTRETCH_Msk        (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)     /*!< 0x00020000 */
9413  #define FMPI2C_CR1_NOSTRETCH            FMPI2C_CR1_NOSTRETCH_Msk               /*!< Clock stretching disable            */
9414  #define FMPI2C_CR1_GCEN_Pos             (19U)
9415  #define FMPI2C_CR1_GCEN_Msk             (0x1UL << FMPI2C_CR1_GCEN_Pos)          /*!< 0x00080000 */
9416  #define FMPI2C_CR1_GCEN                 FMPI2C_CR1_GCEN_Msk                    /*!< General call enable                 */
9417  #define FMPI2C_CR1_SMBHEN_Pos           (20U)
9418  #define FMPI2C_CR1_SMBHEN_Msk           (0x1UL << FMPI2C_CR1_SMBHEN_Pos)        /*!< 0x00100000 */
9419  #define FMPI2C_CR1_SMBHEN               FMPI2C_CR1_SMBHEN_Msk                  /*!< SMBus host address enable           */
9420  #define FMPI2C_CR1_SMBDEN_Pos           (21U)
9421  #define FMPI2C_CR1_SMBDEN_Msk           (0x1UL << FMPI2C_CR1_SMBDEN_Pos)        /*!< 0x00200000 */
9422  #define FMPI2C_CR1_SMBDEN               FMPI2C_CR1_SMBDEN_Msk                  /*!< SMBus device default address enable */
9423  #define FMPI2C_CR1_ALERTEN_Pos          (22U)
9424  #define FMPI2C_CR1_ALERTEN_Msk          (0x1UL << FMPI2C_CR1_ALERTEN_Pos)       /*!< 0x00400000 */
9425  #define FMPI2C_CR1_ALERTEN              FMPI2C_CR1_ALERTEN_Msk                 /*!< SMBus alert enable                  */
9426  #define FMPI2C_CR1_PECEN_Pos            (23U)
9427  #define FMPI2C_CR1_PECEN_Msk            (0x1UL << FMPI2C_CR1_PECEN_Pos)         /*!< 0x00800000 */
9428  #define FMPI2C_CR1_PECEN                FMPI2C_CR1_PECEN_Msk                   /*!< PEC enable                          */
9429  
9430  /* Legacy Defines */
9431  #define FMPI2C_CR1_DFN_Pos              FMPI2C_CR1_DNF_Pos
9432  #define FMPI2C_CR1_DFN_Msk              FMPI2C_CR1_DNF_Msk
9433  #define FMPI2C_CR1_DFN                  FMPI2C_CR1_DNF
9434  /******************  Bit definition for I2C_CR2 register  ********************/
9435  #define FMPI2C_CR2_SADD_Pos             (0U)
9436  #define FMPI2C_CR2_SADD_Msk             (0x3FFUL << FMPI2C_CR2_SADD_Pos)        /*!< 0x000003FF */
9437  #define FMPI2C_CR2_SADD                 FMPI2C_CR2_SADD_Msk                    /*!< Slave address (master mode)                             */
9438  #define FMPI2C_CR2_RD_WRN_Pos           (10U)
9439  #define FMPI2C_CR2_RD_WRN_Msk           (0x1UL << FMPI2C_CR2_RD_WRN_Pos)        /*!< 0x00000400 */
9440  #define FMPI2C_CR2_RD_WRN               FMPI2C_CR2_RD_WRN_Msk                  /*!< Transfer direction (master mode)                        */
9441  #define FMPI2C_CR2_ADD10_Pos            (11U)
9442  #define FMPI2C_CR2_ADD10_Msk            (0x1UL << FMPI2C_CR2_ADD10_Pos)         /*!< 0x00000800 */
9443  #define FMPI2C_CR2_ADD10                FMPI2C_CR2_ADD10_Msk                   /*!< 10-bit addressing mode (master mode)                    */
9444  #define FMPI2C_CR2_HEAD10R_Pos          (12U)
9445  #define FMPI2C_CR2_HEAD10R_Msk          (0x1UL << FMPI2C_CR2_HEAD10R_Pos)       /*!< 0x00001000 */
9446  #define FMPI2C_CR2_HEAD10R              FMPI2C_CR2_HEAD10R_Msk                 /*!< 10-bit address header only read direction (master mode) */
9447  #define FMPI2C_CR2_START_Pos            (13U)
9448  #define FMPI2C_CR2_START_Msk            (0x1UL << FMPI2C_CR2_START_Pos)         /*!< 0x00002000 */
9449  #define FMPI2C_CR2_START                FMPI2C_CR2_START_Msk                   /*!< START generation                                        */
9450  #define FMPI2C_CR2_STOP_Pos             (14U)
9451  #define FMPI2C_CR2_STOP_Msk             (0x1UL << FMPI2C_CR2_STOP_Pos)          /*!< 0x00004000 */
9452  #define FMPI2C_CR2_STOP                 FMPI2C_CR2_STOP_Msk                    /*!< STOP generation (master mode)                           */
9453  #define FMPI2C_CR2_NACK_Pos             (15U)
9454  #define FMPI2C_CR2_NACK_Msk             (0x1UL << FMPI2C_CR2_NACK_Pos)          /*!< 0x00008000 */
9455  #define FMPI2C_CR2_NACK                 FMPI2C_CR2_NACK_Msk                    /*!< NACK generation (slave mode)                            */
9456  #define FMPI2C_CR2_NBYTES_Pos           (16U)
9457  #define FMPI2C_CR2_NBYTES_Msk           (0xFFUL << FMPI2C_CR2_NBYTES_Pos)       /*!< 0x00FF0000 */
9458  #define FMPI2C_CR2_NBYTES               FMPI2C_CR2_NBYTES_Msk                  /*!< Number of bytes                                         */
9459  #define FMPI2C_CR2_RELOAD_Pos           (24U)
9460  #define FMPI2C_CR2_RELOAD_Msk           (0x1UL << FMPI2C_CR2_RELOAD_Pos)        /*!< 0x01000000 */
9461  #define FMPI2C_CR2_RELOAD               FMPI2C_CR2_RELOAD_Msk                  /*!< NBYTES reload mode                                      */
9462  #define FMPI2C_CR2_AUTOEND_Pos          (25U)
9463  #define FMPI2C_CR2_AUTOEND_Msk          (0x1UL << FMPI2C_CR2_AUTOEND_Pos)       /*!< 0x02000000 */
9464  #define FMPI2C_CR2_AUTOEND              FMPI2C_CR2_AUTOEND_Msk                 /*!< Automatic end mode (master mode)                        */
9465  #define FMPI2C_CR2_PECBYTE_Pos          (26U)
9466  #define FMPI2C_CR2_PECBYTE_Msk          (0x1UL << FMPI2C_CR2_PECBYTE_Pos)       /*!< 0x04000000 */
9467  #define FMPI2C_CR2_PECBYTE              FMPI2C_CR2_PECBYTE_Msk                 /*!< Packet error checking byte                              */
9468  
9469  /*******************  Bit definition for I2C_OAR1 register  ******************/
9470  #define FMPI2C_OAR1_OA1_Pos             (0U)
9471  #define FMPI2C_OAR1_OA1_Msk             (0x3FFUL << FMPI2C_OAR1_OA1_Pos)        /*!< 0x000003FF */
9472  #define FMPI2C_OAR1_OA1                 FMPI2C_OAR1_OA1_Msk                    /*!< Interface own address 1   */
9473  #define FMPI2C_OAR1_OA1MODE_Pos         (10U)
9474  #define FMPI2C_OAR1_OA1MODE_Msk         (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)      /*!< 0x00000400 */
9475  #define FMPI2C_OAR1_OA1MODE             FMPI2C_OAR1_OA1MODE_Msk                /*!< Own address 1 10-bit mode */
9476  #define FMPI2C_OAR1_OA1EN_Pos           (15U)
9477  #define FMPI2C_OAR1_OA1EN_Msk           (0x1UL << FMPI2C_OAR1_OA1EN_Pos)        /*!< 0x00008000 */
9478  #define FMPI2C_OAR1_OA1EN               FMPI2C_OAR1_OA1EN_Msk                  /*!< Own address 1 enable      */
9479  
9480  /*******************  Bit definition for I2C_OAR2 register  ******************/
9481  #define FMPI2C_OAR2_OA2_Pos             (1U)
9482  #define FMPI2C_OAR2_OA2_Msk             (0x7FUL << FMPI2C_OAR2_OA2_Pos)         /*!< 0x000000FE */
9483  #define FMPI2C_OAR2_OA2                 FMPI2C_OAR2_OA2_Msk                    /*!< Interface own address 2 */
9484  #define FMPI2C_OAR2_OA2MSK_Pos          (8U)
9485  #define FMPI2C_OAR2_OA2MSK_Msk          (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)       /*!< 0x00000700 */
9486  #define FMPI2C_OAR2_OA2MSK              FMPI2C_OAR2_OA2MSK_Msk                 /*!< Own address 2 masks     */
9487  #define FMPI2C_OAR2_OA2EN_Pos           (15U)
9488  #define FMPI2C_OAR2_OA2EN_Msk           (0x1UL << FMPI2C_OAR2_OA2EN_Pos)        /*!< 0x00008000 */
9489  #define FMPI2C_OAR2_OA2EN               FMPI2C_OAR2_OA2EN_Msk                  /*!< Own address 2 enable    */
9490  
9491  /*******************  Bit definition for I2C_TIMINGR register *******************/
9492  #define FMPI2C_TIMINGR_SCLL_Pos         (0U)
9493  #define FMPI2C_TIMINGR_SCLL_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)     /*!< 0x000000FF */
9494  #define FMPI2C_TIMINGR_SCLL             FMPI2C_TIMINGR_SCLL_Msk                /*!< SCL low period (master mode)  */
9495  #define FMPI2C_TIMINGR_SCLH_Pos         (8U)
9496  #define FMPI2C_TIMINGR_SCLH_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)     /*!< 0x0000FF00 */
9497  #define FMPI2C_TIMINGR_SCLH             FMPI2C_TIMINGR_SCLH_Msk                /*!< SCL high period (master mode) */
9498  #define FMPI2C_TIMINGR_SDADEL_Pos       (16U)
9499  #define FMPI2C_TIMINGR_SDADEL_Msk       (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)    /*!< 0x000F0000 */
9500  #define FMPI2C_TIMINGR_SDADEL           FMPI2C_TIMINGR_SDADEL_Msk              /*!< Data hold time                */
9501  #define FMPI2C_TIMINGR_SCLDEL_Pos       (20U)
9502  #define FMPI2C_TIMINGR_SCLDEL_Msk       (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)    /*!< 0x00F00000 */
9503  #define FMPI2C_TIMINGR_SCLDEL           FMPI2C_TIMINGR_SCLDEL_Msk              /*!< Data setup time               */
9504  #define FMPI2C_TIMINGR_PRESC_Pos        (28U)
9505  #define FMPI2C_TIMINGR_PRESC_Msk        (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)     /*!< 0xF0000000 */
9506  #define FMPI2C_TIMINGR_PRESC            FMPI2C_TIMINGR_PRESC_Msk               /*!< Timings prescaler             */
9507  
9508  /******************* Bit definition for I2C_TIMEOUTR register *******************/
9509  #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
9510  #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
9511  #define FMPI2C_TIMEOUTR_TIMEOUTA        FMPI2C_TIMEOUTR_TIMEOUTA_Msk           /*!< Bus timeout A                 */
9512  #define FMPI2C_TIMEOUTR_TIDLE_Pos       (12U)
9513  #define FMPI2C_TIMEOUTR_TIDLE_Msk       (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)    /*!< 0x00001000 */
9514  #define FMPI2C_TIMEOUTR_TIDLE           FMPI2C_TIMEOUTR_TIDLE_Msk              /*!< Idle clock timeout detection  */
9515  #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
9516  #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
9517  #define FMPI2C_TIMEOUTR_TIMOUTEN        FMPI2C_TIMEOUTR_TIMOUTEN_Msk           /*!< Clock timeout enable          */
9518  #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
9519  #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
9520  #define FMPI2C_TIMEOUTR_TIMEOUTB        FMPI2C_TIMEOUTR_TIMEOUTB_Msk           /*!< Bus timeout B                 */
9521  #define FMPI2C_TIMEOUTR_TEXTEN_Pos      (31U)
9522  #define FMPI2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)   /*!< 0x80000000 */
9523  #define FMPI2C_TIMEOUTR_TEXTEN          FMPI2C_TIMEOUTR_TEXTEN_Msk             /*!< Extended clock timeout enable */
9524  
9525  /******************  Bit definition for I2C_ISR register  *********************/
9526  #define FMPI2C_ISR_TXE_Pos              (0U)
9527  #define FMPI2C_ISR_TXE_Msk              (0x1UL << FMPI2C_ISR_TXE_Pos)           /*!< 0x00000001 */
9528  #define FMPI2C_ISR_TXE                  FMPI2C_ISR_TXE_Msk                     /*!< Transmit data register empty     */
9529  #define FMPI2C_ISR_TXIS_Pos             (1U)
9530  #define FMPI2C_ISR_TXIS_Msk             (0x1UL << FMPI2C_ISR_TXIS_Pos)          /*!< 0x00000002 */
9531  #define FMPI2C_ISR_TXIS                 FMPI2C_ISR_TXIS_Msk                    /*!< Transmit interrupt status        */
9532  #define FMPI2C_ISR_RXNE_Pos             (2U)
9533  #define FMPI2C_ISR_RXNE_Msk             (0x1UL << FMPI2C_ISR_RXNE_Pos)          /*!< 0x00000004 */
9534  #define FMPI2C_ISR_RXNE                 FMPI2C_ISR_RXNE_Msk                    /*!< Receive data register not empty  */
9535  #define FMPI2C_ISR_ADDR_Pos             (3U)
9536  #define FMPI2C_ISR_ADDR_Msk             (0x1UL << FMPI2C_ISR_ADDR_Pos)          /*!< 0x00000008 */
9537  #define FMPI2C_ISR_ADDR                 FMPI2C_ISR_ADDR_Msk                    /*!< Address matched (slave mode)     */
9538  #define FMPI2C_ISR_NACKF_Pos            (4U)
9539  #define FMPI2C_ISR_NACKF_Msk            (0x1UL << FMPI2C_ISR_NACKF_Pos)         /*!< 0x00000010 */
9540  #define FMPI2C_ISR_NACKF                FMPI2C_ISR_NACKF_Msk                   /*!< NACK received flag               */
9541  #define FMPI2C_ISR_STOPF_Pos            (5U)
9542  #define FMPI2C_ISR_STOPF_Msk            (0x1UL << FMPI2C_ISR_STOPF_Pos)         /*!< 0x00000020 */
9543  #define FMPI2C_ISR_STOPF                FMPI2C_ISR_STOPF_Msk                   /*!< STOP detection flag              */
9544  #define FMPI2C_ISR_TC_Pos               (6U)
9545  #define FMPI2C_ISR_TC_Msk               (0x1UL << FMPI2C_ISR_TC_Pos)            /*!< 0x00000040 */
9546  #define FMPI2C_ISR_TC                   FMPI2C_ISR_TC_Msk                      /*!< Transfer complete (master mode)  */
9547  #define FMPI2C_ISR_TCR_Pos              (7U)
9548  #define FMPI2C_ISR_TCR_Msk              (0x1UL << FMPI2C_ISR_TCR_Pos)           /*!< 0x00000080 */
9549  #define FMPI2C_ISR_TCR                  FMPI2C_ISR_TCR_Msk                     /*!< Transfer complete reload         */
9550  #define FMPI2C_ISR_BERR_Pos             (8U)
9551  #define FMPI2C_ISR_BERR_Msk             (0x1UL << FMPI2C_ISR_BERR_Pos)          /*!< 0x00000100 */
9552  #define FMPI2C_ISR_BERR                 FMPI2C_ISR_BERR_Msk                    /*!< Bus error                        */
9553  #define FMPI2C_ISR_ARLO_Pos             (9U)
9554  #define FMPI2C_ISR_ARLO_Msk             (0x1UL << FMPI2C_ISR_ARLO_Pos)          /*!< 0x00000200 */
9555  #define FMPI2C_ISR_ARLO                 FMPI2C_ISR_ARLO_Msk                    /*!< Arbitration lost                 */
9556  #define FMPI2C_ISR_OVR_Pos              (10U)
9557  #define FMPI2C_ISR_OVR_Msk              (0x1UL << FMPI2C_ISR_OVR_Pos)           /*!< 0x00000400 */
9558  #define FMPI2C_ISR_OVR                  FMPI2C_ISR_OVR_Msk                     /*!< Overrun/Underrun                 */
9559  #define FMPI2C_ISR_PECERR_Pos           (11U)
9560  #define FMPI2C_ISR_PECERR_Msk           (0x1UL << FMPI2C_ISR_PECERR_Pos)        /*!< 0x00000800 */
9561  #define FMPI2C_ISR_PECERR               FMPI2C_ISR_PECERR_Msk                  /*!< PEC error in reception           */
9562  #define FMPI2C_ISR_TIMEOUT_Pos          (12U)
9563  #define FMPI2C_ISR_TIMEOUT_Msk          (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)       /*!< 0x00001000 */
9564  #define FMPI2C_ISR_TIMEOUT              FMPI2C_ISR_TIMEOUT_Msk                 /*!< Timeout or Tlow detection flag   */
9565  #define FMPI2C_ISR_ALERT_Pos            (13U)
9566  #define FMPI2C_ISR_ALERT_Msk            (0x1UL << FMPI2C_ISR_ALERT_Pos)         /*!< 0x00002000 */
9567  #define FMPI2C_ISR_ALERT                FMPI2C_ISR_ALERT_Msk                   /*!< SMBus alert                      */
9568  #define FMPI2C_ISR_BUSY_Pos             (15U)
9569  #define FMPI2C_ISR_BUSY_Msk             (0x1UL << FMPI2C_ISR_BUSY_Pos)          /*!< 0x00008000 */
9570  #define FMPI2C_ISR_BUSY                 FMPI2C_ISR_BUSY_Msk                    /*!< Bus busy                         */
9571  #define FMPI2C_ISR_DIR_Pos              (16U)
9572  #define FMPI2C_ISR_DIR_Msk              (0x1UL << FMPI2C_ISR_DIR_Pos)           /*!< 0x00010000 */
9573  #define FMPI2C_ISR_DIR                  FMPI2C_ISR_DIR_Msk                     /*!< Transfer direction (slave mode)  */
9574  #define FMPI2C_ISR_ADDCODE_Pos          (17U)
9575  #define FMPI2C_ISR_ADDCODE_Msk          (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)      /*!< 0x00FE0000 */
9576  #define FMPI2C_ISR_ADDCODE              FMPI2C_ISR_ADDCODE_Msk                 /*!< Address match code (slave mode)  */
9577  
9578  /******************  Bit definition for I2C_ICR register  *********************/
9579  #define FMPI2C_ICR_ADDRCF_Pos           (3U)
9580  #define FMPI2C_ICR_ADDRCF_Msk           (0x1UL << FMPI2C_ICR_ADDRCF_Pos)        /*!< 0x00000008 */
9581  #define FMPI2C_ICR_ADDRCF               FMPI2C_ICR_ADDRCF_Msk                  /*!< Address matched clear flag  */
9582  #define FMPI2C_ICR_NACKCF_Pos           (4U)
9583  #define FMPI2C_ICR_NACKCF_Msk           (0x1UL << FMPI2C_ICR_NACKCF_Pos)        /*!< 0x00000010 */
9584  #define FMPI2C_ICR_NACKCF               FMPI2C_ICR_NACKCF_Msk                  /*!< NACK clear flag             */
9585  #define FMPI2C_ICR_STOPCF_Pos           (5U)
9586  #define FMPI2C_ICR_STOPCF_Msk           (0x1UL << FMPI2C_ICR_STOPCF_Pos)        /*!< 0x00000020 */
9587  #define FMPI2C_ICR_STOPCF               FMPI2C_ICR_STOPCF_Msk                  /*!< STOP detection clear flag   */
9588  #define FMPI2C_ICR_BERRCF_Pos           (8U)
9589  #define FMPI2C_ICR_BERRCF_Msk           (0x1UL << FMPI2C_ICR_BERRCF_Pos)        /*!< 0x00000100 */
9590  #define FMPI2C_ICR_BERRCF               FMPI2C_ICR_BERRCF_Msk                  /*!< Bus error clear flag        */
9591  #define FMPI2C_ICR_ARLOCF_Pos           (9U)
9592  #define FMPI2C_ICR_ARLOCF_Msk           (0x1UL << FMPI2C_ICR_ARLOCF_Pos)        /*!< 0x00000200 */
9593  #define FMPI2C_ICR_ARLOCF               FMPI2C_ICR_ARLOCF_Msk                  /*!< Arbitration lost clear flag */
9594  #define FMPI2C_ICR_OVRCF_Pos            (10U)
9595  #define FMPI2C_ICR_OVRCF_Msk            (0x1UL << FMPI2C_ICR_OVRCF_Pos)         /*!< 0x00000400 */
9596  #define FMPI2C_ICR_OVRCF                FMPI2C_ICR_OVRCF_Msk                   /*!< Overrun/Underrun clear flag */
9597  #define FMPI2C_ICR_PECCF_Pos            (11U)
9598  #define FMPI2C_ICR_PECCF_Msk            (0x1UL << FMPI2C_ICR_PECCF_Pos)         /*!< 0x00000800 */
9599  #define FMPI2C_ICR_PECCF                FMPI2C_ICR_PECCF_Msk                   /*!< PAC error clear flag        */
9600  #define FMPI2C_ICR_TIMOUTCF_Pos         (12U)
9601  #define FMPI2C_ICR_TIMOUTCF_Msk         (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)      /*!< 0x00001000 */
9602  #define FMPI2C_ICR_TIMOUTCF             FMPI2C_ICR_TIMOUTCF_Msk                /*!< Timeout clear flag          */
9603  #define FMPI2C_ICR_ALERTCF_Pos          (13U)
9604  #define FMPI2C_ICR_ALERTCF_Msk          (0x1UL << FMPI2C_ICR_ALERTCF_Pos)       /*!< 0x00002000 */
9605  #define FMPI2C_ICR_ALERTCF              FMPI2C_ICR_ALERTCF_Msk                 /*!< Alert clear flag            */
9606  
9607  /******************  Bit definition for I2C_PECR register  *********************/
9608  #define FMPI2C_PECR_PEC_Pos             (0U)
9609  #define FMPI2C_PECR_PEC_Msk             (0xFFUL << FMPI2C_PECR_PEC_Pos)         /*!< 0x000000FF */
9610  #define FMPI2C_PECR_PEC                 FMPI2C_PECR_PEC_Msk                    /*!< PEC register */
9611  
9612  /******************  Bit definition for I2C_RXDR register  *********************/
9613  #define FMPI2C_RXDR_RXDATA_Pos          (0U)
9614  #define FMPI2C_RXDR_RXDATA_Msk          (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)      /*!< 0x000000FF */
9615  #define FMPI2C_RXDR_RXDATA              FMPI2C_RXDR_RXDATA_Msk                 /*!< 8-bit receive data */
9616  
9617  /******************  Bit definition for I2C_TXDR register  *********************/
9618  #define FMPI2C_TXDR_TXDATA_Pos          (0U)
9619  #define FMPI2C_TXDR_TXDATA_Msk          (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)      /*!< 0x000000FF */
9620  #define FMPI2C_TXDR_TXDATA              FMPI2C_TXDR_TXDATA_Msk                 /*!< 8-bit transmit data */
9621  
9622  
9623  
9624  /******************************************************************************/
9625  /*                                                                            */
9626  /*                           Independent WATCHDOG                             */
9627  /*                                                                            */
9628  /******************************************************************************/
9629  /*******************  Bit definition for IWDG_KR register  ********************/
9630  #define IWDG_KR_KEY_Pos     (0U)
9631  #define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
9632  #define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
9633  
9634  /*******************  Bit definition for IWDG_PR register  ********************/
9635  #define IWDG_PR_PR_Pos      (0U)
9636  #define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
9637  #define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
9638  #define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
9639  #define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
9640  #define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
9641  
9642  /*******************  Bit definition for IWDG_RLR register  *******************/
9643  #define IWDG_RLR_RL_Pos     (0U)
9644  #define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
9645  #define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
9646  
9647  /*******************  Bit definition for IWDG_SR register  ********************/
9648  #define IWDG_SR_PVU_Pos     (0U)
9649  #define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
9650  #define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
9651  #define IWDG_SR_RVU_Pos     (1U)
9652  #define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
9653  #define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
9654  
9655  
9656  
9657  /******************************************************************************/
9658  /*                                                                            */
9659  /*                             Power Control                                  */
9660  /*                                                                            */
9661  /******************************************************************************/
9662  /********************  Bit definition for PWR_CR register  ********************/
9663  #define PWR_CR_LPDS_Pos        (0U)
9664  #define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
9665  #define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
9666  #define PWR_CR_PDDS_Pos        (1U)
9667  #define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
9668  #define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
9669  #define PWR_CR_CWUF_Pos        (2U)
9670  #define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
9671  #define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
9672  #define PWR_CR_CSBF_Pos        (3U)
9673  #define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
9674  #define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
9675  #define PWR_CR_PVDE_Pos        (4U)
9676  #define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
9677  #define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
9678  
9679  #define PWR_CR_PLS_Pos         (5U)
9680  #define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
9681  #define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
9682  #define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
9683  #define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
9684  #define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
9685  
9686  /*!< PVD level configuration */
9687  #define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
9688  #define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
9689  #define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
9690  #define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
9691  #define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
9692  #define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
9693  #define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
9694  #define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
9695  #define PWR_CR_DBP_Pos         (8U)
9696  #define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
9697  #define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
9698  #define PWR_CR_FPDS_Pos        (9U)
9699  #define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
9700  #define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
9701  #define PWR_CR_LPLVDS_Pos      (10U)
9702  #define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */
9703  #define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
9704  #define PWR_CR_MRLVDS_Pos      (11U)
9705  #define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */
9706  #define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */
9707  #define PWR_CR_ADCDC1_Pos      (13U)
9708  #define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */
9709  #define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */
9710  #define PWR_CR_VOS_Pos         (14U)
9711  #define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */
9712  #define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
9713  #define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */
9714  #define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */
9715  #define PWR_CR_ODEN_Pos        (16U)
9716  #define PWR_CR_ODEN_Msk        (0x1UL << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */
9717  #define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */
9718  #define PWR_CR_ODSWEN_Pos      (17U)
9719  #define PWR_CR_ODSWEN_Msk      (0x1UL << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */
9720  #define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */
9721  #define PWR_CR_UDEN_Pos        (18U)
9722  #define PWR_CR_UDEN_Msk        (0x3UL << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */
9723  #define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */
9724  #define PWR_CR_UDEN_0          (0x1UL << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */
9725  #define PWR_CR_UDEN_1          (0x2UL << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */
9726  #define PWR_CR_FMSSR_Pos       (20U)
9727  #define PWR_CR_FMSSR_Msk       (0x1UL << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */
9728  #define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */
9729  #define PWR_CR_FISSR_Pos       (21U)
9730  #define PWR_CR_FISSR_Msk       (0x1UL << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */
9731  #define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */
9732  
9733  /* Legacy define */
9734  #define  PWR_CR_PMODE                        PWR_CR_VOS
9735  #define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
9736  #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
9737  
9738  /*******************  Bit definition for PWR_CSR register  ********************/
9739  #define PWR_CSR_WUF_Pos        (0U)
9740  #define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
9741  #define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
9742  #define PWR_CSR_SBF_Pos        (1U)
9743  #define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
9744  #define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
9745  #define PWR_CSR_PVDO_Pos       (2U)
9746  #define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
9747  #define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
9748  #define PWR_CSR_BRR_Pos        (3U)
9749  #define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
9750  #define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
9751  #define PWR_CSR_EWUP2_Pos      (7U)
9752  #define PWR_CSR_EWUP2_Msk      (0x1UL << PWR_CSR_EWUP2_Pos)                     /*!< 0x00000080 */
9753  #define PWR_CSR_EWUP2          PWR_CSR_EWUP2_Msk                               /*!< Enable WKUP pin 2                                */
9754  #define PWR_CSR_EWUP1_Pos      (8U)
9755  #define PWR_CSR_EWUP1_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000100 */
9756  #define PWR_CSR_EWUP1          PWR_CSR_EWUP1_Msk                               /*!< Enable WKUP pin 1                                */
9757  #define PWR_CSR_BRE_Pos        (9U)
9758  #define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
9759  #define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
9760  #define PWR_CSR_VOSRDY_Pos     (14U)
9761  #define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
9762  #define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
9763  #define PWR_CSR_ODRDY_Pos      (16U)
9764  #define PWR_CSR_ODRDY_Msk      (0x1UL << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */
9765  #define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */
9766  #define PWR_CSR_ODSWRDY_Pos    (17U)
9767  #define PWR_CSR_ODSWRDY_Msk    (0x1UL << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */
9768  #define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */
9769  #define PWR_CSR_UDRDY_Pos      (18U)
9770  #define PWR_CSR_UDRDY_Msk      (0x3UL << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */
9771  #define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */
9772  /* Legacy define */
9773  #define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY
9774  
9775  /* Legacy define */
9776  #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
9777  
9778  /******************************************************************************/
9779  /*                                                                            */
9780  /*                                    QUADSPI                                 */
9781  /*                                                                            */
9782  /******************************************************************************/
9783  /*****************  Bit definition for QUADSPI_CR register  *******************/
9784  #define QUADSPI_CR_EN_Pos                (0U)
9785  #define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */
9786  #define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */
9787  #define QUADSPI_CR_ABORT_Pos             (1U)
9788  #define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */
9789  #define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */
9790  #define QUADSPI_CR_DMAEN_Pos             (2U)
9791  #define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */
9792  #define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */
9793  #define QUADSPI_CR_TCEN_Pos              (3U)
9794  #define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */
9795  #define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */
9796  #define QUADSPI_CR_SSHIFT_Pos            (4U)
9797  #define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */
9798  #define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */
9799  #define QUADSPI_CR_DFM_Pos               (6U)
9800  #define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */
9801  #define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */
9802  #define QUADSPI_CR_FSEL_Pos              (7U)
9803  #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */
9804  #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */
9805  #define QUADSPI_CR_FTHRES_Pos            (8U)
9806  #define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
9807  #define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */
9808  #define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
9809  #define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
9810  #define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
9811  #define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
9812  #define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */
9813  #define QUADSPI_CR_TEIE_Pos              (16U)
9814  #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */
9815  #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */
9816  #define QUADSPI_CR_TCIE_Pos              (17U)
9817  #define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */
9818  #define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
9819  #define QUADSPI_CR_FTIE_Pos              (18U)
9820  #define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */
9821  #define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */
9822  #define QUADSPI_CR_SMIE_Pos              (19U)
9823  #define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */
9824  #define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */
9825  #define QUADSPI_CR_TOIE_Pos              (20U)
9826  #define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */
9827  #define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */
9828  #define QUADSPI_CR_APMS_Pos              (22U)
9829  #define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */
9830  #define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */
9831  #define QUADSPI_CR_PMM_Pos               (23U)
9832  #define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */
9833  #define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */
9834  #define QUADSPI_CR_PRESCALER_Pos         (24U)
9835  #define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */
9836  #define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */
9837  #define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */
9838  #define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */
9839  #define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */
9840  #define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */
9841  #define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */
9842  #define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */
9843  #define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */
9844  #define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */
9845  
9846  /*****************  Bit definition for QUADSPI_DCR register  ******************/
9847  #define QUADSPI_DCR_CKMODE_Pos           (0U)
9848  #define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */
9849  #define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */
9850  #define QUADSPI_DCR_CSHT_Pos             (8U)
9851  #define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */
9852  #define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
9853  #define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */
9854  #define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */
9855  #define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */
9856  #define QUADSPI_DCR_FSIZE_Pos            (16U)
9857  #define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */
9858  #define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */
9859  #define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */
9860  #define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */
9861  #define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */
9862  #define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */
9863  #define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */
9864  
9865  /******************  Bit definition for QUADSPI_SR register  *******************/
9866  #define QUADSPI_SR_TEF_Pos               (0U)
9867  #define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */
9868  #define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */
9869  #define QUADSPI_SR_TCF_Pos               (1U)
9870  #define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */
9871  #define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
9872  #define QUADSPI_SR_FTF_Pos               (2U)
9873  #define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */
9874  #define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */
9875  #define QUADSPI_SR_SMF_Pos               (3U)
9876  #define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */
9877  #define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */
9878  #define QUADSPI_SR_TOF_Pos               (4U)
9879  #define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */
9880  #define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */
9881  #define QUADSPI_SR_BUSY_Pos              (5U)
9882  #define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */
9883  #define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */
9884  #define QUADSPI_SR_FLEVEL_Pos            (8U)
9885  #define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */
9886  #define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */
9887  #define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */
9888  #define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */
9889  #define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */
9890  #define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */
9891  #define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */
9892  #define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */
9893  
9894  /******************  Bit definition for QUADSPI_FCR register  ******************/
9895  #define QUADSPI_FCR_CTEF_Pos             (0U)
9896  #define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */
9897  #define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */
9898  #define QUADSPI_FCR_CTCF_Pos             (1U)
9899  #define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */
9900  #define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
9901  #define QUADSPI_FCR_CSMF_Pos             (3U)
9902  #define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */
9903  #define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */
9904  #define QUADSPI_FCR_CTOF_Pos             (4U)
9905  #define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */
9906  #define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */
9907  
9908  /******************  Bit definition for QUADSPI_DLR register  ******************/
9909  #define QUADSPI_DLR_DL_Pos               (0U)
9910  #define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */
9911  #define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
9912  
9913  /******************  Bit definition for QUADSPI_CCR register  ******************/
9914  #define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
9915  #define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
9916  #define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */
9917  #define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
9918  #define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
9919  #define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
9920  #define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
9921  #define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
9922  #define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
9923  #define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
9924  #define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
9925  #define QUADSPI_CCR_IMODE_Pos            (8U)
9926  #define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */
9927  #define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */
9928  #define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */
9929  #define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */
9930  #define QUADSPI_CCR_ADMODE_Pos           (10U)
9931  #define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */
9932  #define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */
9933  #define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */
9934  #define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */
9935  #define QUADSPI_CCR_ADSIZE_Pos           (12U)
9936  #define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */
9937  #define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */
9938  #define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */
9939  #define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */
9940  #define QUADSPI_CCR_ABMODE_Pos           (14U)
9941  #define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */
9942  #define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */
9943  #define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */
9944  #define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */
9945  #define QUADSPI_CCR_ABSIZE_Pos           (16U)
9946  #define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */
9947  #define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */
9948  #define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */
9949  #define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */
9950  #define QUADSPI_CCR_DCYC_Pos             (18U)
9951  #define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */
9952  #define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */
9953  #define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */
9954  #define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */
9955  #define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */
9956  #define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */
9957  #define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */
9958  #define QUADSPI_CCR_DMODE_Pos            (24U)
9959  #define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */
9960  #define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */
9961  #define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */
9962  #define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */
9963  #define QUADSPI_CCR_FMODE_Pos            (26U)
9964  #define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */
9965  #define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */
9966  #define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */
9967  #define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */
9968  #define QUADSPI_CCR_SIOO_Pos             (28U)
9969  #define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */
9970  #define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */
9971  #define QUADSPI_CCR_DHHC_Pos             (30U)
9972  #define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */
9973  #define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */
9974  #define QUADSPI_CCR_DDRM_Pos             (31U)
9975  #define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */
9976  #define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */
9977  /******************  Bit definition for QUADSPI_AR register  *******************/
9978  #define QUADSPI_AR_ADDRESS_Pos           (0U)
9979  #define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
9980  #define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */
9981  
9982  /******************  Bit definition for QUADSPI_ABR register  ******************/
9983  #define QUADSPI_ABR_ALTERNATE_Pos        (0U)
9984  #define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
9985  #define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */
9986  
9987  /******************  Bit definition for QUADSPI_DR register  *******************/
9988  #define QUADSPI_DR_DATA_Pos              (0U)
9989  #define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */
9990  #define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */
9991  
9992  /******************  Bit definition for QUADSPI_PSMKR register  ****************/
9993  #define QUADSPI_PSMKR_MASK_Pos           (0U)
9994  #define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
9995  #define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */
9996  
9997  /******************  Bit definition for QUADSPI_PSMAR register  ****************/
9998  #define QUADSPI_PSMAR_MATCH_Pos          (0U)
9999  #define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
10000  #define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */
10001  
10002  /******************  Bit definition for QUADSPI_PIR register  *****************/
10003  #define QUADSPI_PIR_INTERVAL_Pos         (0U)
10004  #define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
10005  #define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */
10006  
10007  /******************  Bit definition for QUADSPI_LPTR register  *****************/
10008  #define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
10009  #define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
10010  #define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */
10011  
10012  /******************************************************************************/
10013  /*                                                                            */
10014  /*                         Reset and Clock Control                            */
10015  /*                                                                            */
10016  /******************************************************************************/
10017  /********************  Bit definition for RCC_CR register  ********************/
10018  #define RCC_CR_HSION_Pos                   (0U)
10019  #define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
10020  #define RCC_CR_HSION                       RCC_CR_HSION_Msk
10021  #define RCC_CR_HSIRDY_Pos                  (1U)
10022  #define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
10023  #define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk
10024  
10025  #define RCC_CR_HSITRIM_Pos                 (3U)
10026  #define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
10027  #define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk
10028  #define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
10029  #define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
10030  #define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
10031  #define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
10032  #define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
10033  
10034  #define RCC_CR_HSICAL_Pos                  (8U)
10035  #define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
10036  #define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk
10037  #define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
10038  #define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
10039  #define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
10040  #define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
10041  #define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
10042  #define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
10043  #define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
10044  #define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
10045  
10046  #define RCC_CR_HSEON_Pos                   (16U)
10047  #define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
10048  #define RCC_CR_HSEON                       RCC_CR_HSEON_Msk
10049  #define RCC_CR_HSERDY_Pos                  (17U)
10050  #define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
10051  #define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk
10052  #define RCC_CR_HSEBYP_Pos                  (18U)
10053  #define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
10054  #define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk
10055  #define RCC_CR_CSSON_Pos                   (19U)
10056  #define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
10057  #define RCC_CR_CSSON                       RCC_CR_CSSON_Msk
10058  #define RCC_CR_PLLON_Pos                   (24U)
10059  #define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
10060  #define RCC_CR_PLLON                       RCC_CR_PLLON_Msk
10061  #define RCC_CR_PLLRDY_Pos                  (25U)
10062  #define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
10063  #define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk
10064  /*
10065   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10066   */
10067  #define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */
10068  
10069  #define RCC_CR_PLLI2SON_Pos                (26U)
10070  #define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
10071  #define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk
10072  #define RCC_CR_PLLI2SRDY_Pos               (27U)
10073  #define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
10074  #define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk
10075  /*
10076   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10077   */
10078  #define RCC_PLLSAI_SUPPORT                                                     /*!< Support PLLSAI oscillator */
10079  
10080  #define RCC_CR_PLLSAION_Pos                (28U)
10081  #define RCC_CR_PLLSAION_Msk                (0x1UL << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */
10082  #define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk
10083  #define RCC_CR_PLLSAIRDY_Pos               (29U)
10084  #define RCC_CR_PLLSAIRDY_Msk               (0x1UL << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */
10085  #define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk
10086  
10087  /********************  Bit definition for RCC_PLLCFGR register  ***************/
10088  #define RCC_PLLCFGR_PLLM_Pos               (0U)
10089  #define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
10090  #define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk
10091  #define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
10092  #define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
10093  #define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
10094  #define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
10095  #define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
10096  #define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
10097  
10098  #define RCC_PLLCFGR_PLLN_Pos               (6U)
10099  #define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
10100  #define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk
10101  #define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
10102  #define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
10103  #define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
10104  #define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
10105  #define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
10106  #define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
10107  #define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
10108  #define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
10109  #define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
10110  
10111  #define RCC_PLLCFGR_PLLP_Pos               (16U)
10112  #define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
10113  #define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk
10114  #define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
10115  #define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
10116  
10117  #define RCC_PLLCFGR_PLLSRC_Pos             (22U)
10118  #define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
10119  #define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk
10120  #define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)
10121  #define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
10122  #define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk
10123  #define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U
10124  
10125  #define RCC_PLLCFGR_PLLQ_Pos               (24U)
10126  #define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
10127  #define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk
10128  #define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
10129  #define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
10130  #define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
10131  #define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
10132  /*
10133   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10134   */
10135  #define RCC_PLLR_SYSCLK_SUPPORT            /*!< Support PLLR as system clock */
10136  #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT     /*!< Support PLLR clock as I2S clock source */
10137  
10138  #define RCC_PLLCFGR_PLLR_Pos               (28U)
10139  #define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */
10140  #define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk
10141  #define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */
10142  #define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */
10143  #define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */
10144  
10145  /********************  Bit definition for RCC_CFGR register  ******************/
10146  /*!< SW configuration */
10147  #define RCC_CFGR_SW_Pos                    (0U)
10148  #define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
10149  #define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
10150  #define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
10151  #define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
10152  
10153  #define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
10154  #define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
10155  #define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
10156  #define RCC_CFGR_SW_PLLR                   0x00000003U                         /*!< PLL/PLLR selected as system clock */
10157  
10158  /*!< SWS configuration */
10159  #define RCC_CFGR_SWS_Pos                   (2U)
10160  #define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
10161  #define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
10162  #define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
10163  #define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
10164  
10165  #define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
10166  #define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
10167  #define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
10168  #define RCC_CFGR_SWS_PLLR                  0x0000000CU                         /*!< PLL/PLLR used as system clock       */
10169  
10170  /*!< HPRE configuration */
10171  #define RCC_CFGR_HPRE_Pos                  (4U)
10172  #define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
10173  #define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
10174  #define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
10175  #define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
10176  #define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
10177  #define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
10178  
10179  #define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
10180  #define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
10181  #define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
10182  #define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
10183  #define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
10184  #define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
10185  #define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
10186  #define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
10187  #define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
10188  
10189  /*!< PPRE1 configuration */
10190  #define RCC_CFGR_PPRE1_Pos                 (10U)
10191  #define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
10192  #define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
10193  #define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
10194  #define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
10195  #define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
10196  
10197  #define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
10198  #define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
10199  #define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
10200  #define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
10201  #define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
10202  
10203  /*!< PPRE2 configuration */
10204  #define RCC_CFGR_PPRE2_Pos                 (13U)
10205  #define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
10206  #define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
10207  #define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
10208  #define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
10209  #define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
10210  
10211  #define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
10212  #define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
10213  #define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
10214  #define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
10215  #define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
10216  
10217  /*!< RTCPRE configuration */
10218  #define RCC_CFGR_RTCPRE_Pos                (16U)
10219  #define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
10220  #define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk
10221  #define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
10222  #define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
10223  #define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
10224  #define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
10225  #define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
10226  
10227  /*!< MCO1 configuration */
10228  #define RCC_CFGR_MCO1_Pos                  (21U)
10229  #define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
10230  #define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk
10231  #define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
10232  #define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
10233  
10234  
10235  #define RCC_CFGR_MCO1PRE_Pos               (24U)
10236  #define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
10237  #define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk
10238  #define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
10239  #define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
10240  #define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
10241  
10242  #define RCC_CFGR_MCO2PRE_Pos               (27U)
10243  #define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
10244  #define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk
10245  #define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
10246  #define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
10247  #define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
10248  
10249  #define RCC_CFGR_MCO2_Pos                  (30U)
10250  #define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
10251  #define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk
10252  #define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
10253  #define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
10254  
10255  /********************  Bit definition for RCC_CIR register  *******************/
10256  #define RCC_CIR_LSIRDYF_Pos                (0U)
10257  #define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
10258  #define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk
10259  #define RCC_CIR_LSERDYF_Pos                (1U)
10260  #define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
10261  #define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk
10262  #define RCC_CIR_HSIRDYF_Pos                (2U)
10263  #define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
10264  #define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk
10265  #define RCC_CIR_HSERDYF_Pos                (3U)
10266  #define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
10267  #define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk
10268  #define RCC_CIR_PLLRDYF_Pos                (4U)
10269  #define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
10270  #define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk
10271  #define RCC_CIR_PLLI2SRDYF_Pos             (5U)
10272  #define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
10273  #define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk
10274  
10275  #define RCC_CIR_PLLSAIRDYF_Pos             (6U)
10276  #define RCC_CIR_PLLSAIRDYF_Msk             (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */
10277  #define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk
10278  #define RCC_CIR_CSSF_Pos                   (7U)
10279  #define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
10280  #define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk
10281  #define RCC_CIR_LSIRDYIE_Pos               (8U)
10282  #define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
10283  #define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk
10284  #define RCC_CIR_LSERDYIE_Pos               (9U)
10285  #define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
10286  #define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk
10287  #define RCC_CIR_HSIRDYIE_Pos               (10U)
10288  #define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
10289  #define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk
10290  #define RCC_CIR_HSERDYIE_Pos               (11U)
10291  #define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
10292  #define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk
10293  #define RCC_CIR_PLLRDYIE_Pos               (12U)
10294  #define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
10295  #define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk
10296  #define RCC_CIR_PLLI2SRDYIE_Pos            (13U)
10297  #define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
10298  #define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk
10299  
10300  #define RCC_CIR_PLLSAIRDYIE_Pos            (14U)
10301  #define RCC_CIR_PLLSAIRDYIE_Msk            (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */
10302  #define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk
10303  #define RCC_CIR_LSIRDYC_Pos                (16U)
10304  #define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
10305  #define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk
10306  #define RCC_CIR_LSERDYC_Pos                (17U)
10307  #define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
10308  #define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk
10309  #define RCC_CIR_HSIRDYC_Pos                (18U)
10310  #define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
10311  #define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk
10312  #define RCC_CIR_HSERDYC_Pos                (19U)
10313  #define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
10314  #define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk
10315  #define RCC_CIR_PLLRDYC_Pos                (20U)
10316  #define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
10317  #define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk
10318  #define RCC_CIR_PLLI2SRDYC_Pos             (21U)
10319  #define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
10320  #define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk
10321  #define RCC_CIR_PLLSAIRDYC_Pos             (22U)
10322  #define RCC_CIR_PLLSAIRDYC_Msk             (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */
10323  #define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk
10324  
10325  #define RCC_CIR_CSSC_Pos                   (23U)
10326  #define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
10327  #define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk
10328  
10329  /********************  Bit definition for RCC_AHB1RSTR register  **************/
10330  #define RCC_AHB1RSTR_GPIOARST_Pos          (0U)
10331  #define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
10332  #define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk
10333  #define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)
10334  #define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
10335  #define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk
10336  #define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)
10337  #define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
10338  #define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk
10339  #define RCC_AHB1RSTR_GPIODRST_Pos          (3U)
10340  #define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
10341  #define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk
10342  #define RCC_AHB1RSTR_GPIOERST_Pos          (4U)
10343  #define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
10344  #define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk
10345  #define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)
10346  #define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
10347  #define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk
10348  #define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)
10349  #define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
10350  #define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk
10351  #define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)
10352  #define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
10353  #define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk
10354  #define RCC_AHB1RSTR_CRCRST_Pos            (12U)
10355  #define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
10356  #define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk
10357  #define RCC_AHB1RSTR_DMA1RST_Pos           (21U)
10358  #define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
10359  #define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk
10360  #define RCC_AHB1RSTR_DMA2RST_Pos           (22U)
10361  #define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
10362  #define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk
10363  #define RCC_AHB1RSTR_OTGHRST_Pos           (29U)
10364  #define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
10365  #define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk
10366  
10367  /********************  Bit definition for RCC_AHB2RSTR register  **************/
10368  #define RCC_AHB2RSTR_DCMIRST_Pos           (0U)
10369  #define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
10370  #define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk
10371  #define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)
10372  #define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
10373  #define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk
10374  /********************  Bit definition for RCC_AHB3RSTR register  **************/
10375  #define RCC_AHB3RSTR_FMCRST_Pos            (0U)
10376  #define RCC_AHB3RSTR_FMCRST_Msk            (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */
10377  #define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk
10378  #define RCC_AHB3RSTR_QSPIRST_Pos           (1U)
10379  #define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */
10380  #define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk
10381  
10382  
10383  /********************  Bit definition for RCC_APB1RSTR register  **************/
10384  #define RCC_APB1RSTR_TIM2RST_Pos           (0U)
10385  #define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
10386  #define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk
10387  #define RCC_APB1RSTR_TIM3RST_Pos           (1U)
10388  #define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
10389  #define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk
10390  #define RCC_APB1RSTR_TIM4RST_Pos           (2U)
10391  #define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
10392  #define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk
10393  #define RCC_APB1RSTR_TIM5RST_Pos           (3U)
10394  #define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
10395  #define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk
10396  #define RCC_APB1RSTR_TIM6RST_Pos           (4U)
10397  #define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
10398  #define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk
10399  #define RCC_APB1RSTR_TIM7RST_Pos           (5U)
10400  #define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
10401  #define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk
10402  #define RCC_APB1RSTR_TIM12RST_Pos          (6U)
10403  #define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
10404  #define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk
10405  #define RCC_APB1RSTR_TIM13RST_Pos          (7U)
10406  #define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
10407  #define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk
10408  #define RCC_APB1RSTR_TIM14RST_Pos          (8U)
10409  #define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
10410  #define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk
10411  #define RCC_APB1RSTR_WWDGRST_Pos           (11U)
10412  #define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
10413  #define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk
10414  #define RCC_APB1RSTR_SPI2RST_Pos           (14U)
10415  #define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
10416  #define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk
10417  #define RCC_APB1RSTR_SPI3RST_Pos           (15U)
10418  #define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
10419  #define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk
10420  #define RCC_APB1RSTR_SPDIFRXRST_Pos        (16U)
10421  #define RCC_APB1RSTR_SPDIFRXRST_Msk        (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
10422  #define RCC_APB1RSTR_SPDIFRXRST            RCC_APB1RSTR_SPDIFRXRST_Msk
10423  #define RCC_APB1RSTR_USART2RST_Pos         (17U)
10424  #define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
10425  #define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk
10426  #define RCC_APB1RSTR_USART3RST_Pos         (18U)
10427  #define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
10428  #define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk
10429  #define RCC_APB1RSTR_UART4RST_Pos          (19U)
10430  #define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
10431  #define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk
10432  #define RCC_APB1RSTR_UART5RST_Pos          (20U)
10433  #define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
10434  #define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk
10435  #define RCC_APB1RSTR_I2C1RST_Pos           (21U)
10436  #define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
10437  #define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk
10438  #define RCC_APB1RSTR_I2C2RST_Pos           (22U)
10439  #define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
10440  #define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk
10441  #define RCC_APB1RSTR_I2C3RST_Pos           (23U)
10442  #define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
10443  #define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk
10444  #define RCC_APB1RSTR_FMPI2C1RST_Pos        (24U)
10445  #define RCC_APB1RSTR_FMPI2C1RST_Msk        (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
10446  #define RCC_APB1RSTR_FMPI2C1RST            RCC_APB1RSTR_FMPI2C1RST_Msk
10447  #define RCC_APB1RSTR_CAN1RST_Pos           (25U)
10448  #define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
10449  #define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk
10450  #define RCC_APB1RSTR_CAN2RST_Pos           (26U)
10451  #define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
10452  #define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk
10453  #define RCC_APB1RSTR_CECRST_Pos            (27U)
10454  #define RCC_APB1RSTR_CECRST_Msk            (0x1UL << RCC_APB1RSTR_CECRST_Pos)   /*!< 0x08000000 */
10455  #define RCC_APB1RSTR_CECRST                RCC_APB1RSTR_CECRST_Msk
10456  #define RCC_APB1RSTR_PWRRST_Pos            (28U)
10457  #define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
10458  #define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk
10459  #define RCC_APB1RSTR_DACRST_Pos            (29U)
10460  #define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
10461  #define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk
10462  
10463  /********************  Bit definition for RCC_APB2RSTR register  **************/
10464  #define RCC_APB2RSTR_TIM1RST_Pos           (0U)
10465  #define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
10466  #define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk
10467  #define RCC_APB2RSTR_TIM8RST_Pos           (1U)
10468  #define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
10469  #define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk
10470  #define RCC_APB2RSTR_USART1RST_Pos         (4U)
10471  #define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
10472  #define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk
10473  #define RCC_APB2RSTR_USART6RST_Pos         (5U)
10474  #define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
10475  #define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk
10476  #define RCC_APB2RSTR_ADCRST_Pos            (8U)
10477  #define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
10478  #define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk
10479  #define RCC_APB2RSTR_SDIORST_Pos           (11U)
10480  #define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
10481  #define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk
10482  #define RCC_APB2RSTR_SPI1RST_Pos           (12U)
10483  #define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
10484  #define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk
10485  #define RCC_APB2RSTR_SPI4RST_Pos           (13U)
10486  #define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */
10487  #define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk
10488  #define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)
10489  #define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
10490  #define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk
10491  #define RCC_APB2RSTR_TIM9RST_Pos           (16U)
10492  #define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
10493  #define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk
10494  #define RCC_APB2RSTR_TIM10RST_Pos          (17U)
10495  #define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
10496  #define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk
10497  #define RCC_APB2RSTR_TIM11RST_Pos          (18U)
10498  #define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
10499  #define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk
10500  #define RCC_APB2RSTR_SAI1RST_Pos           (22U)
10501  #define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */
10502  #define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk
10503  #define RCC_APB2RSTR_SAI2RST_Pos           (23U)
10504  #define RCC_APB2RSTR_SAI2RST_Msk           (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)  /*!< 0x00800000 */
10505  #define RCC_APB2RSTR_SAI2RST               RCC_APB2RSTR_SAI2RST_Msk
10506  
10507  /* Old SPI1RST bit definition, maintained for legacy purpose */
10508  #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
10509  
10510  /********************  Bit definition for RCC_AHB1ENR register  ***************/
10511  #define RCC_AHB1ENR_GPIOAEN_Pos            (0U)
10512  #define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
10513  #define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk
10514  #define RCC_AHB1ENR_GPIOBEN_Pos            (1U)
10515  #define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
10516  #define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk
10517  #define RCC_AHB1ENR_GPIOCEN_Pos            (2U)
10518  #define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
10519  #define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk
10520  #define RCC_AHB1ENR_GPIODEN_Pos            (3U)
10521  #define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
10522  #define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk
10523  #define RCC_AHB1ENR_GPIOEEN_Pos            (4U)
10524  #define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
10525  #define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk
10526  #define RCC_AHB1ENR_GPIOFEN_Pos            (5U)
10527  #define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
10528  #define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk
10529  #define RCC_AHB1ENR_GPIOGEN_Pos            (6U)
10530  #define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
10531  #define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk
10532  #define RCC_AHB1ENR_GPIOHEN_Pos            (7U)
10533  #define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
10534  #define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk
10535  #define RCC_AHB1ENR_CRCEN_Pos              (12U)
10536  #define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
10537  #define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk
10538  #define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)
10539  #define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
10540  #define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk
10541  #define RCC_AHB1ENR_DMA1EN_Pos             (21U)
10542  #define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
10543  #define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk
10544  #define RCC_AHB1ENR_DMA2EN_Pos             (22U)
10545  #define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
10546  #define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk
10547  #define RCC_AHB1ENR_OTGHSEN_Pos            (29U)
10548  #define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
10549  #define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk
10550  #define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)
10551  #define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
10552  #define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk
10553  /********************  Bit definition for RCC_AHB2ENR register  ***************/
10554  /*
10555   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10556   */
10557  #define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */
10558  
10559  #define RCC_AHB2ENR_DCMIEN_Pos             (0U)
10560  #define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
10561  #define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk
10562  #define RCC_AHB2ENR_OTGFSEN_Pos            (7U)
10563  #define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
10564  #define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk
10565  
10566  /********************  Bit definition for RCC_AHB3ENR register  ***************/
10567  /*
10568   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10569   */
10570  #define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */
10571  
10572  #define RCC_AHB3ENR_FMCEN_Pos              (0U)
10573  #define RCC_AHB3ENR_FMCEN_Msk              (0x1UL << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */
10574  #define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk
10575  #define RCC_AHB3ENR_QSPIEN_Pos             (1U)
10576  #define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */
10577  #define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk
10578  
10579  /********************  Bit definition for RCC_APB1ENR register  ***************/
10580  #define RCC_APB1ENR_TIM2EN_Pos             (0U)
10581  #define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
10582  #define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk
10583  #define RCC_APB1ENR_TIM3EN_Pos             (1U)
10584  #define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
10585  #define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk
10586  #define RCC_APB1ENR_TIM4EN_Pos             (2U)
10587  #define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
10588  #define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk
10589  #define RCC_APB1ENR_TIM5EN_Pos             (3U)
10590  #define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
10591  #define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk
10592  #define RCC_APB1ENR_TIM6EN_Pos             (4U)
10593  #define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
10594  #define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk
10595  #define RCC_APB1ENR_TIM7EN_Pos             (5U)
10596  #define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
10597  #define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk
10598  #define RCC_APB1ENR_TIM12EN_Pos            (6U)
10599  #define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
10600  #define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk
10601  #define RCC_APB1ENR_TIM13EN_Pos            (7U)
10602  #define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
10603  #define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk
10604  #define RCC_APB1ENR_TIM14EN_Pos            (8U)
10605  #define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
10606  #define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk
10607  #define RCC_APB1ENR_WWDGEN_Pos             (11U)
10608  #define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
10609  #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk
10610  #define RCC_APB1ENR_SPI2EN_Pos             (14U)
10611  #define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
10612  #define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk
10613  #define RCC_APB1ENR_SPI3EN_Pos             (15U)
10614  #define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
10615  #define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk
10616  #define RCC_APB1ENR_SPDIFRXEN_Pos          (16U)
10617  #define RCC_APB1ENR_SPDIFRXEN_Msk          (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
10618  #define RCC_APB1ENR_SPDIFRXEN              RCC_APB1ENR_SPDIFRXEN_Msk
10619  #define RCC_APB1ENR_USART2EN_Pos           (17U)
10620  #define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
10621  #define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk
10622  #define RCC_APB1ENR_USART3EN_Pos           (18U)
10623  #define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
10624  #define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk
10625  #define RCC_APB1ENR_UART4EN_Pos            (19U)
10626  #define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
10627  #define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk
10628  #define RCC_APB1ENR_UART5EN_Pos            (20U)
10629  #define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
10630  #define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk
10631  #define RCC_APB1ENR_I2C1EN_Pos             (21U)
10632  #define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
10633  #define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk
10634  #define RCC_APB1ENR_I2C2EN_Pos             (22U)
10635  #define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
10636  #define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk
10637  #define RCC_APB1ENR_I2C3EN_Pos             (23U)
10638  #define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
10639  #define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk
10640  #define RCC_APB1ENR_FMPI2C1EN_Pos          (24U)
10641  #define RCC_APB1ENR_FMPI2C1EN_Msk          (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
10642  #define RCC_APB1ENR_FMPI2C1EN              RCC_APB1ENR_FMPI2C1EN_Msk
10643  #define RCC_APB1ENR_CAN1EN_Pos             (25U)
10644  #define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
10645  #define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk
10646  #define RCC_APB1ENR_CAN2EN_Pos             (26U)
10647  #define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
10648  #define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk
10649  #define RCC_APB1ENR_CECEN_Pos              (27U)
10650  #define RCC_APB1ENR_CECEN_Msk              (0x1UL << RCC_APB1ENR_CECEN_Pos)     /*!< 0x08000000 */
10651  #define RCC_APB1ENR_CECEN                  RCC_APB1ENR_CECEN_Msk
10652  #define RCC_APB1ENR_PWREN_Pos              (28U)
10653  #define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
10654  #define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk
10655  #define RCC_APB1ENR_DACEN_Pos              (29U)
10656  #define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
10657  #define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk
10658  
10659  /********************  Bit definition for RCC_APB2ENR register  ***************/
10660  #define RCC_APB2ENR_TIM1EN_Pos             (0U)
10661  #define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
10662  #define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk
10663  #define RCC_APB2ENR_TIM8EN_Pos             (1U)
10664  #define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
10665  #define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk
10666  #define RCC_APB2ENR_USART1EN_Pos           (4U)
10667  #define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
10668  #define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk
10669  #define RCC_APB2ENR_USART6EN_Pos           (5U)
10670  #define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
10671  #define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk
10672  #define RCC_APB2ENR_ADC1EN_Pos             (8U)
10673  #define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
10674  #define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk
10675  #define RCC_APB2ENR_ADC2EN_Pos             (9U)
10676  #define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
10677  #define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk
10678  #define RCC_APB2ENR_ADC3EN_Pos             (10U)
10679  #define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
10680  #define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk
10681  #define RCC_APB2ENR_SDIOEN_Pos             (11U)
10682  #define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
10683  #define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk
10684  #define RCC_APB2ENR_SPI1EN_Pos             (12U)
10685  #define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
10686  #define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk
10687  #define RCC_APB2ENR_SPI4EN_Pos             (13U)
10688  #define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */
10689  #define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk
10690  #define RCC_APB2ENR_SYSCFGEN_Pos           (14U)
10691  #define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
10692  #define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk
10693  #define RCC_APB2ENR_TIM9EN_Pos             (16U)
10694  #define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
10695  #define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk
10696  #define RCC_APB2ENR_TIM10EN_Pos            (17U)
10697  #define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
10698  #define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk
10699  #define RCC_APB2ENR_TIM11EN_Pos            (18U)
10700  #define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
10701  #define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk
10702  #define RCC_APB2ENR_SAI1EN_Pos             (22U)
10703  #define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */
10704  #define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk
10705  #define RCC_APB2ENR_SAI2EN_Pos             (23U)
10706  #define RCC_APB2ENR_SAI2EN_Msk             (0x1UL << RCC_APB2ENR_SAI2EN_Pos)    /*!< 0x00800000 */
10707  #define RCC_APB2ENR_SAI2EN                 RCC_APB2ENR_SAI2EN_Msk
10708  
10709  /********************  Bit definition for RCC_AHB1LPENR register  *************/
10710  #define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)
10711  #define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
10712  #define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk
10713  #define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)
10714  #define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
10715  #define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk
10716  #define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)
10717  #define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
10718  #define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk
10719  #define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)
10720  #define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
10721  #define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk
10722  #define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)
10723  #define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
10724  #define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk
10725  #define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)
10726  #define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
10727  #define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk
10728  #define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)
10729  #define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
10730  #define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk
10731  #define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)
10732  #define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
10733  #define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk
10734  #define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)
10735  #define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
10736  #define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk
10737  #define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)
10738  #define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
10739  #define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk
10740  #define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)
10741  #define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
10742  #define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk
10743  #define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)
10744  #define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
10745  #define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk
10746  #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)
10747  #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
10748  #define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10749  #define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)
10750  #define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
10751  #define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk
10752  #define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)
10753  #define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
10754  #define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk
10755  
10756  #define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)
10757  #define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
10758  #define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk
10759  #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)
10760  #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
10761  #define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10762  
10763  /********************  Bit definition for RCC_AHB2LPENR register  *************/
10764  #define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)
10765  #define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
10766  #define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk
10767  #define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)
10768  #define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
10769  #define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk
10770  
10771  /********************  Bit definition for RCC_AHB3LPENR register  *************/
10772  #define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)
10773  #define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
10774  #define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk
10775  #define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)
10776  #define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
10777  #define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk
10778  
10779  /********************  Bit definition for RCC_APB1LPENR register  *************/
10780  #define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)
10781  #define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
10782  #define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk
10783  #define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)
10784  #define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
10785  #define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk
10786  #define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)
10787  #define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
10788  #define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk
10789  #define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)
10790  #define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
10791  #define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk
10792  #define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)
10793  #define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
10794  #define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk
10795  #define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)
10796  #define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
10797  #define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk
10798  #define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)
10799  #define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
10800  #define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk
10801  #define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)
10802  #define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
10803  #define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk
10804  #define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)
10805  #define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
10806  #define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk
10807  #define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)
10808  #define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
10809  #define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk
10810  #define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)
10811  #define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
10812  #define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk
10813  #define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)
10814  #define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
10815  #define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk
10816  #define RCC_APB1LPENR_SPDIFRXLPEN_Pos      (16U)
10817  #define RCC_APB1LPENR_SPDIFRXLPEN_Msk      (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
10818  #define RCC_APB1LPENR_SPDIFRXLPEN          RCC_APB1LPENR_SPDIFRXLPEN_Msk
10819  #define RCC_APB1LPENR_USART2LPEN_Pos       (17U)
10820  #define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
10821  #define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk
10822  #define RCC_APB1LPENR_USART3LPEN_Pos       (18U)
10823  #define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
10824  #define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk
10825  #define RCC_APB1LPENR_UART4LPEN_Pos        (19U)
10826  #define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
10827  #define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk
10828  #define RCC_APB1LPENR_UART5LPEN_Pos        (20U)
10829  #define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
10830  #define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk
10831  #define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)
10832  #define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
10833  #define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk
10834  #define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)
10835  #define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
10836  #define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk
10837  #define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)
10838  #define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
10839  #define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk
10840  #define RCC_APB1LPENR_FMPI2C1LPEN_Pos      (24U)
10841  #define RCC_APB1LPENR_FMPI2C1LPEN_Msk      (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
10842  #define RCC_APB1LPENR_FMPI2C1LPEN          RCC_APB1LPENR_FMPI2C1LPEN_Msk
10843  #define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)
10844  #define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
10845  #define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk
10846  #define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)
10847  #define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
10848  #define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk
10849  #define RCC_APB1LPENR_CECLPEN_Pos          (27U)
10850  #define RCC_APB1LPENR_CECLPEN_Msk          (0x1UL << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
10851  #define RCC_APB1LPENR_CECLPEN              RCC_APB1LPENR_CECLPEN_Msk
10852  #define RCC_APB1LPENR_PWRLPEN_Pos          (28U)
10853  #define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
10854  #define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk
10855  #define RCC_APB1LPENR_DACLPEN_Pos          (29U)
10856  #define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
10857  #define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk
10858  
10859  /********************  Bit definition for RCC_APB2LPENR register  *************/
10860  #define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)
10861  #define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
10862  #define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk
10863  #define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)
10864  #define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
10865  #define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk
10866  #define RCC_APB2LPENR_USART1LPEN_Pos       (4U)
10867  #define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
10868  #define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk
10869  #define RCC_APB2LPENR_USART6LPEN_Pos       (5U)
10870  #define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
10871  #define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk
10872  #define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)
10873  #define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
10874  #define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk
10875  #define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)
10876  #define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
10877  #define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk
10878  #define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)
10879  #define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
10880  #define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk
10881  #define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)
10882  #define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
10883  #define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk
10884  #define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)
10885  #define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
10886  #define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk
10887  #define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)
10888  #define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
10889  #define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk
10890  #define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)
10891  #define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
10892  #define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk
10893  #define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)
10894  #define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
10895  #define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk
10896  #define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)
10897  #define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
10898  #define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk
10899  #define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)
10900  #define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
10901  #define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk
10902  #define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)
10903  #define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
10904  #define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk
10905  #define RCC_APB2LPENR_SAI2LPEN_Pos         (23U)
10906  #define RCC_APB2LPENR_SAI2LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
10907  #define RCC_APB2LPENR_SAI2LPEN             RCC_APB2LPENR_SAI2LPEN_Msk
10908  
10909  /********************  Bit definition for RCC_BDCR register  ******************/
10910  #define RCC_BDCR_LSEON_Pos                 (0U)
10911  #define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
10912  #define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk
10913  #define RCC_BDCR_LSERDY_Pos                (1U)
10914  #define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
10915  #define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk
10916  #define RCC_BDCR_LSEBYP_Pos                (2U)
10917  #define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
10918  #define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk
10919  #define RCC_BDCR_LSEMOD_Pos                (3U)
10920  #define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */
10921  #define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk
10922  
10923  #define RCC_BDCR_RTCSEL_Pos                (8U)
10924  #define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
10925  #define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk
10926  #define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
10927  #define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
10928  
10929  #define RCC_BDCR_RTCEN_Pos                 (15U)
10930  #define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
10931  #define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk
10932  #define RCC_BDCR_BDRST_Pos                 (16U)
10933  #define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
10934  #define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk
10935  
10936  /********************  Bit definition for RCC_CSR register  *******************/
10937  #define RCC_CSR_LSION_Pos                  (0U)
10938  #define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
10939  #define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
10940  #define RCC_CSR_LSIRDY_Pos                 (1U)
10941  #define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
10942  #define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
10943  #define RCC_CSR_RMVF_Pos                   (24U)
10944  #define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
10945  #define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk
10946  #define RCC_CSR_BORRSTF_Pos                (25U)
10947  #define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
10948  #define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk
10949  #define RCC_CSR_PINRSTF_Pos                (26U)
10950  #define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
10951  #define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
10952  #define RCC_CSR_PORRSTF_Pos                (27U)
10953  #define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
10954  #define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk
10955  #define RCC_CSR_SFTRSTF_Pos                (28U)
10956  #define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
10957  #define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk
10958  #define RCC_CSR_IWDGRSTF_Pos               (29U)
10959  #define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
10960  #define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
10961  #define RCC_CSR_WWDGRSTF_Pos               (30U)
10962  #define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
10963  #define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk
10964  #define RCC_CSR_LPWRRSTF_Pos               (31U)
10965  #define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
10966  #define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
10967  /* Legacy defines */
10968  #define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
10969  #define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
10970  
10971  /********************  Bit definition for RCC_SSCGR register  *****************/
10972  #define RCC_SSCGR_MODPER_Pos               (0U)
10973  #define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
10974  #define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk
10975  #define RCC_SSCGR_INCSTEP_Pos              (13U)
10976  #define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
10977  #define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk
10978  #define RCC_SSCGR_SPREADSEL_Pos            (30U)
10979  #define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
10980  #define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk
10981  #define RCC_SSCGR_SSCGEN_Pos               (31U)
10982  #define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
10983  #define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk
10984  
10985  /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
10986  #define RCC_PLLI2SCFGR_PLLI2SM_Pos         (0U)
10987  #define RCC_PLLI2SCFGR_PLLI2SM_Msk         (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
10988  #define RCC_PLLI2SCFGR_PLLI2SM             RCC_PLLI2SCFGR_PLLI2SM_Msk
10989  #define RCC_PLLI2SCFGR_PLLI2SM_0           (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
10990  #define RCC_PLLI2SCFGR_PLLI2SM_1           (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
10991  #define RCC_PLLI2SCFGR_PLLI2SM_2           (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
10992  #define RCC_PLLI2SCFGR_PLLI2SM_3           (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
10993  #define RCC_PLLI2SCFGR_PLLI2SM_4           (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
10994  #define RCC_PLLI2SCFGR_PLLI2SM_5           (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
10995  
10996  #define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)
10997  #define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
10998  #define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk
10999  #define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
11000  #define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
11001  #define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
11002  #define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
11003  #define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
11004  #define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
11005  #define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
11006  #define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
11007  #define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
11008  
11009  #define RCC_PLLI2SCFGR_PLLI2SP_Pos         (16U)
11010  #define RCC_PLLI2SCFGR_PLLI2SP_Msk         (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
11011  #define RCC_PLLI2SCFGR_PLLI2SP             RCC_PLLI2SCFGR_PLLI2SP_Msk
11012  #define RCC_PLLI2SCFGR_PLLI2SP_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
11013  #define RCC_PLLI2SCFGR_PLLI2SP_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
11014  #define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)
11015  #define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
11016  #define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk
11017  #define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
11018  #define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
11019  #define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
11020  #define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
11021  #define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)
11022  #define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
11023  #define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk
11024  #define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
11025  #define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
11026  #define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
11027  
11028  /********************  Bit definition for RCC_PLLSAICFGR register  ************/
11029  #define RCC_PLLSAICFGR_PLLSAIM_Pos         (0U)
11030  #define RCC_PLLSAICFGR_PLLSAIM_Msk         (0x3FUL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x0000003F */
11031  #define RCC_PLLSAICFGR_PLLSAIM             RCC_PLLSAICFGR_PLLSAIM_Msk
11032  #define RCC_PLLSAICFGR_PLLSAIM_0           (0x01UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000001 */
11033  #define RCC_PLLSAICFGR_PLLSAIM_1           (0x02UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000002 */
11034  #define RCC_PLLSAICFGR_PLLSAIM_2           (0x04UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000004 */
11035  #define RCC_PLLSAICFGR_PLLSAIM_3           (0x08UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000008 */
11036  #define RCC_PLLSAICFGR_PLLSAIM_4           (0x10UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000010 */
11037  #define RCC_PLLSAICFGR_PLLSAIM_5           (0x20UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000020 */
11038  #define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)
11039  #define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
11040  #define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk
11041  #define RCC_PLLSAICFGR_PLLSAIN_0           (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
11042  #define RCC_PLLSAICFGR_PLLSAIN_1           (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
11043  #define RCC_PLLSAICFGR_PLLSAIN_2           (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
11044  #define RCC_PLLSAICFGR_PLLSAIN_3           (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
11045  #define RCC_PLLSAICFGR_PLLSAIN_4           (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
11046  #define RCC_PLLSAICFGR_PLLSAIN_5           (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
11047  #define RCC_PLLSAICFGR_PLLSAIN_6           (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
11048  #define RCC_PLLSAICFGR_PLLSAIN_7           (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
11049  #define RCC_PLLSAICFGR_PLLSAIN_8           (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
11050  
11051  #define RCC_PLLSAICFGR_PLLSAIP_Pos         (16U)
11052  #define RCC_PLLSAICFGR_PLLSAIP_Msk         (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
11053  #define RCC_PLLSAICFGR_PLLSAIP             RCC_PLLSAICFGR_PLLSAIP_Msk
11054  #define RCC_PLLSAICFGR_PLLSAIP_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
11055  #define RCC_PLLSAICFGR_PLLSAIP_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
11056  
11057  #define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)
11058  #define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
11059  #define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk
11060  #define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
11061  #define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
11062  #define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
11063  #define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
11064  
11065  
11066  /********************  Bit definition for RCC_DCKCFGR register  ***************/
11067  #define RCC_DCKCFGR_PLLI2SDIVQ_Pos        (0U)
11068  #define RCC_DCKCFGR_PLLI2SDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
11069  #define RCC_DCKCFGR_PLLI2SDIVQ            RCC_DCKCFGR_PLLI2SDIVQ_Msk
11070  #define RCC_DCKCFGR_PLLI2SDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
11071  #define RCC_DCKCFGR_PLLI2SDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
11072  #define RCC_DCKCFGR_PLLI2SDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
11073  #define RCC_DCKCFGR_PLLI2SDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
11074  #define RCC_DCKCFGR_PLLI2SDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
11075  
11076  #define RCC_DCKCFGR_PLLSAIDIVQ_Pos        (8U)
11077  #define RCC_DCKCFGR_PLLSAIDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
11078  #define RCC_DCKCFGR_PLLSAIDIVQ            RCC_DCKCFGR_PLLSAIDIVQ_Msk
11079  #define RCC_DCKCFGR_PLLSAIDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
11080  #define RCC_DCKCFGR_PLLSAIDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
11081  #define RCC_DCKCFGR_PLLSAIDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
11082  #define RCC_DCKCFGR_PLLSAIDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
11083  #define RCC_DCKCFGR_PLLSAIDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
11084  #define RCC_DCKCFGR_SAI1SRC_Pos            (20U)
11085  #define RCC_DCKCFGR_SAI1SRC_Msk            (0x3UL << RCC_DCKCFGR_SAI1SRC_Pos)   /*!< 0x00300000 */
11086  #define RCC_DCKCFGR_SAI1SRC                RCC_DCKCFGR_SAI1SRC_Msk
11087  #define RCC_DCKCFGR_SAI1SRC_0              (0x1UL << RCC_DCKCFGR_SAI1SRC_Pos)   /*!< 0x00100000 */
11088  #define RCC_DCKCFGR_SAI1SRC_1              (0x2UL << RCC_DCKCFGR_SAI1SRC_Pos)   /*!< 0x00200000 */
11089  #define RCC_DCKCFGR_SAI2SRC_Pos            (22U)
11090  #define RCC_DCKCFGR_SAI2SRC_Msk            (0x3UL << RCC_DCKCFGR_SAI2SRC_Pos)   /*!< 0x00C00000 */
11091  #define RCC_DCKCFGR_SAI2SRC                RCC_DCKCFGR_SAI2SRC_Msk
11092  #define RCC_DCKCFGR_SAI2SRC_0              (0x1UL << RCC_DCKCFGR_SAI2SRC_Pos)   /*!< 0x00400000 */
11093  #define RCC_DCKCFGR_SAI2SRC_1              (0x2UL << RCC_DCKCFGR_SAI2SRC_Pos)   /*!< 0x00800000 */
11094  
11095  #define RCC_DCKCFGR_TIMPRE_Pos             (24U)
11096  #define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */
11097  #define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk
11098  #define RCC_DCKCFGR_I2S1SRC_Pos            (25U)
11099  #define RCC_DCKCFGR_I2S1SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x06000000 */
11100  #define RCC_DCKCFGR_I2S1SRC                RCC_DCKCFGR_I2S1SRC_Msk
11101  #define RCC_DCKCFGR_I2S1SRC_0              (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x02000000 */
11102  #define RCC_DCKCFGR_I2S1SRC_1              (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x04000000 */
11103  
11104  #define RCC_DCKCFGR_I2S2SRC_Pos            (27U)
11105  #define RCC_DCKCFGR_I2S2SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x18000000 */
11106  #define RCC_DCKCFGR_I2S2SRC                RCC_DCKCFGR_I2S2SRC_Msk
11107  #define RCC_DCKCFGR_I2S2SRC_0              (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x08000000 */
11108  #define RCC_DCKCFGR_I2S2SRC_1              (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x10000000 */
11109  
11110  /********************  Bit definition for RCC_CKGATENR register  ***************/
11111  #define RCC_CKGATENR_AHB2APB1_CKEN_Pos     (0U)
11112  #define RCC_CKGATENR_AHB2APB1_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
11113  #define RCC_CKGATENR_AHB2APB1_CKEN         RCC_CKGATENR_AHB2APB1_CKEN_Msk
11114  #define RCC_CKGATENR_AHB2APB2_CKEN_Pos     (1U)
11115  #define RCC_CKGATENR_AHB2APB2_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
11116  #define RCC_CKGATENR_AHB2APB2_CKEN         RCC_CKGATENR_AHB2APB2_CKEN_Msk
11117  #define RCC_CKGATENR_CM4DBG_CKEN_Pos       (2U)
11118  #define RCC_CKGATENR_CM4DBG_CKEN_Msk       (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
11119  #define RCC_CKGATENR_CM4DBG_CKEN           RCC_CKGATENR_CM4DBG_CKEN_Msk
11120  #define RCC_CKGATENR_SPARE_CKEN_Pos        (3U)
11121  #define RCC_CKGATENR_SPARE_CKEN_Msk        (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
11122  #define RCC_CKGATENR_SPARE_CKEN            RCC_CKGATENR_SPARE_CKEN_Msk
11123  #define RCC_CKGATENR_SRAM_CKEN_Pos         (4U)
11124  #define RCC_CKGATENR_SRAM_CKEN_Msk         (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
11125  #define RCC_CKGATENR_SRAM_CKEN             RCC_CKGATENR_SRAM_CKEN_Msk
11126  #define RCC_CKGATENR_FLITF_CKEN_Pos        (5U)
11127  #define RCC_CKGATENR_FLITF_CKEN_Msk        (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
11128  #define RCC_CKGATENR_FLITF_CKEN            RCC_CKGATENR_FLITF_CKEN_Msk
11129  #define RCC_CKGATENR_RCC_CKEN_Pos          (6U)
11130  #define RCC_CKGATENR_RCC_CKEN_Msk          (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
11131  #define RCC_CKGATENR_RCC_CKEN              RCC_CKGATENR_RCC_CKEN_Msk
11132  
11133  /********************  Bit definition for RCC_DCKCFGR2 register  ***************/
11134  #define RCC_DCKCFGR2_FMPI2C1SEL_Pos        (22U)
11135  #define RCC_DCKCFGR2_FMPI2C1SEL_Msk        (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
11136  #define RCC_DCKCFGR2_FMPI2C1SEL            RCC_DCKCFGR2_FMPI2C1SEL_Msk
11137  #define RCC_DCKCFGR2_FMPI2C1SEL_0          (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
11138  #define RCC_DCKCFGR2_FMPI2C1SEL_1          (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
11139  #define RCC_DCKCFGR2_CECSEL_Pos            (26U)
11140  #define RCC_DCKCFGR2_CECSEL_Msk            (0x1UL << RCC_DCKCFGR2_CECSEL_Pos)   /*!< 0x04000000 */
11141  #define RCC_DCKCFGR2_CECSEL                RCC_DCKCFGR2_CECSEL_Msk
11142  #define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)
11143  #define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
11144  #define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk
11145  #define RCC_DCKCFGR2_SDIOSEL_Pos           (28U)
11146  #define RCC_DCKCFGR2_SDIOSEL_Msk           (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)  /*!< 0x10000000 */
11147  #define RCC_DCKCFGR2_SDIOSEL               RCC_DCKCFGR2_SDIOSEL_Msk
11148  #define RCC_DCKCFGR2_SPDIFRXSEL_Pos        (29U)
11149  #define RCC_DCKCFGR2_SPDIFRXSEL_Msk        (0x1UL << RCC_DCKCFGR2_SPDIFRXSEL_Pos) /*!< 0x20000000 */
11150  #define RCC_DCKCFGR2_SPDIFRXSEL            RCC_DCKCFGR2_SPDIFRXSEL_Msk
11151  
11152  
11153  /******************************************************************************/
11154  /*                                                                            */
11155  /*                           Real-Time Clock (RTC)                            */
11156  /*                                                                            */
11157  /******************************************************************************/
11158  /*
11159   * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)
11160   */
11161  #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
11162  #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
11163  /********************  Bits definition for RTC_TR register  *******************/
11164  #define RTC_TR_PM_Pos                 (22U)
11165  #define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
11166  #define RTC_TR_PM                     RTC_TR_PM_Msk
11167  #define RTC_TR_HT_Pos                 (20U)
11168  #define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
11169  #define RTC_TR_HT                     RTC_TR_HT_Msk
11170  #define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
11171  #define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
11172  #define RTC_TR_HU_Pos                 (16U)
11173  #define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
11174  #define RTC_TR_HU                     RTC_TR_HU_Msk
11175  #define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
11176  #define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
11177  #define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
11178  #define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
11179  #define RTC_TR_MNT_Pos                (12U)
11180  #define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
11181  #define RTC_TR_MNT                    RTC_TR_MNT_Msk
11182  #define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
11183  #define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
11184  #define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
11185  #define RTC_TR_MNU_Pos                (8U)
11186  #define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
11187  #define RTC_TR_MNU                    RTC_TR_MNU_Msk
11188  #define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
11189  #define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
11190  #define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
11191  #define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
11192  #define RTC_TR_ST_Pos                 (4U)
11193  #define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
11194  #define RTC_TR_ST                     RTC_TR_ST_Msk
11195  #define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
11196  #define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
11197  #define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
11198  #define RTC_TR_SU_Pos                 (0U)
11199  #define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
11200  #define RTC_TR_SU                     RTC_TR_SU_Msk
11201  #define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
11202  #define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
11203  #define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
11204  #define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
11205  
11206  /********************  Bits definition for RTC_DR register  *******************/
11207  #define RTC_DR_YT_Pos                 (20U)
11208  #define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
11209  #define RTC_DR_YT                     RTC_DR_YT_Msk
11210  #define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
11211  #define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
11212  #define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
11213  #define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
11214  #define RTC_DR_YU_Pos                 (16U)
11215  #define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
11216  #define RTC_DR_YU                     RTC_DR_YU_Msk
11217  #define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
11218  #define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
11219  #define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
11220  #define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
11221  #define RTC_DR_WDU_Pos                (13U)
11222  #define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
11223  #define RTC_DR_WDU                    RTC_DR_WDU_Msk
11224  #define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
11225  #define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
11226  #define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
11227  #define RTC_DR_MT_Pos                 (12U)
11228  #define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
11229  #define RTC_DR_MT                     RTC_DR_MT_Msk
11230  #define RTC_DR_MU_Pos                 (8U)
11231  #define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
11232  #define RTC_DR_MU                     RTC_DR_MU_Msk
11233  #define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
11234  #define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
11235  #define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
11236  #define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
11237  #define RTC_DR_DT_Pos                 (4U)
11238  #define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
11239  #define RTC_DR_DT                     RTC_DR_DT_Msk
11240  #define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
11241  #define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
11242  #define RTC_DR_DU_Pos                 (0U)
11243  #define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
11244  #define RTC_DR_DU                     RTC_DR_DU_Msk
11245  #define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
11246  #define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
11247  #define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
11248  #define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
11249  
11250  /********************  Bits definition for RTC_CR register  *******************/
11251  #define RTC_CR_COE_Pos                (23U)
11252  #define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
11253  #define RTC_CR_COE                    RTC_CR_COE_Msk
11254  #define RTC_CR_OSEL_Pos               (21U)
11255  #define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
11256  #define RTC_CR_OSEL                   RTC_CR_OSEL_Msk
11257  #define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
11258  #define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
11259  #define RTC_CR_POL_Pos                (20U)
11260  #define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
11261  #define RTC_CR_POL                    RTC_CR_POL_Msk
11262  #define RTC_CR_COSEL_Pos              (19U)
11263  #define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
11264  #define RTC_CR_COSEL                  RTC_CR_COSEL_Msk
11265  #define RTC_CR_BKP_Pos                 (18U)
11266  #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
11267  #define RTC_CR_BKP                     RTC_CR_BKP_Msk
11268  #define RTC_CR_SUB1H_Pos              (17U)
11269  #define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
11270  #define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk
11271  #define RTC_CR_ADD1H_Pos              (16U)
11272  #define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
11273  #define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk
11274  #define RTC_CR_TSIE_Pos               (15U)
11275  #define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
11276  #define RTC_CR_TSIE                   RTC_CR_TSIE_Msk
11277  #define RTC_CR_WUTIE_Pos              (14U)
11278  #define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
11279  #define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk
11280  #define RTC_CR_ALRBIE_Pos             (13U)
11281  #define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
11282  #define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk
11283  #define RTC_CR_ALRAIE_Pos             (12U)
11284  #define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
11285  #define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk
11286  #define RTC_CR_TSE_Pos                (11U)
11287  #define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
11288  #define RTC_CR_TSE                    RTC_CR_TSE_Msk
11289  #define RTC_CR_WUTE_Pos               (10U)
11290  #define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
11291  #define RTC_CR_WUTE                   RTC_CR_WUTE_Msk
11292  #define RTC_CR_ALRBE_Pos              (9U)
11293  #define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
11294  #define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk
11295  #define RTC_CR_ALRAE_Pos              (8U)
11296  #define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
11297  #define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk
11298  #define RTC_CR_DCE_Pos                (7U)
11299  #define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
11300  #define RTC_CR_DCE                    RTC_CR_DCE_Msk
11301  #define RTC_CR_FMT_Pos                (6U)
11302  #define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
11303  #define RTC_CR_FMT                    RTC_CR_FMT_Msk
11304  #define RTC_CR_BYPSHAD_Pos            (5U)
11305  #define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
11306  #define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk
11307  #define RTC_CR_REFCKON_Pos            (4U)
11308  #define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
11309  #define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk
11310  #define RTC_CR_TSEDGE_Pos             (3U)
11311  #define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
11312  #define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk
11313  #define RTC_CR_WUCKSEL_Pos            (0U)
11314  #define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
11315  #define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk
11316  #define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
11317  #define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
11318  #define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
11319  
11320  /* Legacy defines */
11321  #define RTC_CR_BCK                     RTC_CR_BKP
11322  
11323  /********************  Bits definition for RTC_ISR register  ******************/
11324  #define RTC_ISR_RECALPF_Pos           (16U)
11325  #define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
11326  #define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk
11327  #define RTC_ISR_TAMP1F_Pos            (13U)
11328  #define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
11329  #define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk
11330  #define RTC_ISR_TAMP2F_Pos            (14U)
11331  #define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
11332  #define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk
11333  #define RTC_ISR_TSOVF_Pos             (12U)
11334  #define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
11335  #define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk
11336  #define RTC_ISR_TSF_Pos               (11U)
11337  #define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
11338  #define RTC_ISR_TSF                   RTC_ISR_TSF_Msk
11339  #define RTC_ISR_WUTF_Pos              (10U)
11340  #define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
11341  #define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk
11342  #define RTC_ISR_ALRBF_Pos             (9U)
11343  #define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
11344  #define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk
11345  #define RTC_ISR_ALRAF_Pos             (8U)
11346  #define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
11347  #define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk
11348  #define RTC_ISR_INIT_Pos              (7U)
11349  #define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
11350  #define RTC_ISR_INIT                  RTC_ISR_INIT_Msk
11351  #define RTC_ISR_INITF_Pos             (6U)
11352  #define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
11353  #define RTC_ISR_INITF                 RTC_ISR_INITF_Msk
11354  #define RTC_ISR_RSF_Pos               (5U)
11355  #define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
11356  #define RTC_ISR_RSF                   RTC_ISR_RSF_Msk
11357  #define RTC_ISR_INITS_Pos             (4U)
11358  #define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
11359  #define RTC_ISR_INITS                 RTC_ISR_INITS_Msk
11360  #define RTC_ISR_SHPF_Pos              (3U)
11361  #define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
11362  #define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk
11363  #define RTC_ISR_WUTWF_Pos             (2U)
11364  #define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
11365  #define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk
11366  #define RTC_ISR_ALRBWF_Pos            (1U)
11367  #define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
11368  #define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk
11369  #define RTC_ISR_ALRAWF_Pos            (0U)
11370  #define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
11371  #define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk
11372  
11373  /********************  Bits definition for RTC_PRER register  *****************/
11374  #define RTC_PRER_PREDIV_A_Pos         (16U)
11375  #define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
11376  #define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk
11377  #define RTC_PRER_PREDIV_S_Pos         (0U)
11378  #define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
11379  #define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk
11380  
11381  /********************  Bits definition for RTC_WUTR register  *****************/
11382  #define RTC_WUTR_WUT_Pos              (0U)
11383  #define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
11384  #define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk
11385  
11386  /********************  Bits definition for RTC_CALIBR register  ***************/
11387  #define RTC_CALIBR_DCS_Pos            (7U)
11388  #define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
11389  #define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk
11390  #define RTC_CALIBR_DC_Pos             (0U)
11391  #define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
11392  #define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk
11393  
11394  /********************  Bits definition for RTC_ALRMAR register  ***************/
11395  #define RTC_ALRMAR_MSK4_Pos           (31U)
11396  #define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
11397  #define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk
11398  #define RTC_ALRMAR_WDSEL_Pos          (30U)
11399  #define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
11400  #define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk
11401  #define RTC_ALRMAR_DT_Pos             (28U)
11402  #define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
11403  #define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk
11404  #define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
11405  #define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
11406  #define RTC_ALRMAR_DU_Pos             (24U)
11407  #define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
11408  #define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk
11409  #define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
11410  #define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
11411  #define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
11412  #define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
11413  #define RTC_ALRMAR_MSK3_Pos           (23U)
11414  #define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
11415  #define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk
11416  #define RTC_ALRMAR_PM_Pos             (22U)
11417  #define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
11418  #define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk
11419  #define RTC_ALRMAR_HT_Pos             (20U)
11420  #define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
11421  #define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk
11422  #define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
11423  #define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
11424  #define RTC_ALRMAR_HU_Pos             (16U)
11425  #define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
11426  #define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk
11427  #define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
11428  #define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
11429  #define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
11430  #define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
11431  #define RTC_ALRMAR_MSK2_Pos           (15U)
11432  #define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
11433  #define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk
11434  #define RTC_ALRMAR_MNT_Pos            (12U)
11435  #define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
11436  #define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk
11437  #define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
11438  #define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
11439  #define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
11440  #define RTC_ALRMAR_MNU_Pos            (8U)
11441  #define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
11442  #define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk
11443  #define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
11444  #define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
11445  #define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
11446  #define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
11447  #define RTC_ALRMAR_MSK1_Pos           (7U)
11448  #define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
11449  #define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk
11450  #define RTC_ALRMAR_ST_Pos             (4U)
11451  #define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
11452  #define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk
11453  #define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
11454  #define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
11455  #define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
11456  #define RTC_ALRMAR_SU_Pos             (0U)
11457  #define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
11458  #define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk
11459  #define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
11460  #define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
11461  #define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
11462  #define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
11463  
11464  /********************  Bits definition for RTC_ALRMBR register  ***************/
11465  #define RTC_ALRMBR_MSK4_Pos           (31U)
11466  #define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
11467  #define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk
11468  #define RTC_ALRMBR_WDSEL_Pos          (30U)
11469  #define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
11470  #define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk
11471  #define RTC_ALRMBR_DT_Pos             (28U)
11472  #define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
11473  #define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk
11474  #define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
11475  #define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
11476  #define RTC_ALRMBR_DU_Pos             (24U)
11477  #define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
11478  #define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk
11479  #define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
11480  #define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
11481  #define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
11482  #define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
11483  #define RTC_ALRMBR_MSK3_Pos           (23U)
11484  #define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
11485  #define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk
11486  #define RTC_ALRMBR_PM_Pos             (22U)
11487  #define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
11488  #define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk
11489  #define RTC_ALRMBR_HT_Pos             (20U)
11490  #define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
11491  #define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk
11492  #define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
11493  #define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
11494  #define RTC_ALRMBR_HU_Pos             (16U)
11495  #define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
11496  #define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk
11497  #define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
11498  #define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
11499  #define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
11500  #define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
11501  #define RTC_ALRMBR_MSK2_Pos           (15U)
11502  #define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
11503  #define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk
11504  #define RTC_ALRMBR_MNT_Pos            (12U)
11505  #define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
11506  #define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk
11507  #define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
11508  #define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
11509  #define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
11510  #define RTC_ALRMBR_MNU_Pos            (8U)
11511  #define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
11512  #define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk
11513  #define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
11514  #define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
11515  #define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
11516  #define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
11517  #define RTC_ALRMBR_MSK1_Pos           (7U)
11518  #define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
11519  #define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk
11520  #define RTC_ALRMBR_ST_Pos             (4U)
11521  #define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
11522  #define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk
11523  #define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
11524  #define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
11525  #define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
11526  #define RTC_ALRMBR_SU_Pos             (0U)
11527  #define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
11528  #define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk
11529  #define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
11530  #define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
11531  #define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
11532  #define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
11533  
11534  /********************  Bits definition for RTC_WPR register  ******************/
11535  #define RTC_WPR_KEY_Pos               (0U)
11536  #define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
11537  #define RTC_WPR_KEY                   RTC_WPR_KEY_Msk
11538  
11539  /********************  Bits definition for RTC_SSR register  ******************/
11540  #define RTC_SSR_SS_Pos                (0U)
11541  #define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
11542  #define RTC_SSR_SS                    RTC_SSR_SS_Msk
11543  
11544  /********************  Bits definition for RTC_SHIFTR register  ***************/
11545  #define RTC_SHIFTR_SUBFS_Pos          (0U)
11546  #define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
11547  #define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk
11548  #define RTC_SHIFTR_ADD1S_Pos          (31U)
11549  #define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
11550  #define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk
11551  
11552  /********************  Bits definition for RTC_TSTR register  *****************/
11553  #define RTC_TSTR_PM_Pos               (22U)
11554  #define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
11555  #define RTC_TSTR_PM                   RTC_TSTR_PM_Msk
11556  #define RTC_TSTR_HT_Pos               (20U)
11557  #define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
11558  #define RTC_TSTR_HT                   RTC_TSTR_HT_Msk
11559  #define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
11560  #define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
11561  #define RTC_TSTR_HU_Pos               (16U)
11562  #define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
11563  #define RTC_TSTR_HU                   RTC_TSTR_HU_Msk
11564  #define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
11565  #define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
11566  #define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
11567  #define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
11568  #define RTC_TSTR_MNT_Pos              (12U)
11569  #define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
11570  #define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk
11571  #define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
11572  #define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
11573  #define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
11574  #define RTC_TSTR_MNU_Pos              (8U)
11575  #define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
11576  #define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk
11577  #define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
11578  #define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
11579  #define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
11580  #define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
11581  #define RTC_TSTR_ST_Pos               (4U)
11582  #define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
11583  #define RTC_TSTR_ST                   RTC_TSTR_ST_Msk
11584  #define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
11585  #define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
11586  #define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
11587  #define RTC_TSTR_SU_Pos               (0U)
11588  #define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
11589  #define RTC_TSTR_SU                   RTC_TSTR_SU_Msk
11590  #define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
11591  #define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
11592  #define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
11593  #define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
11594  
11595  /********************  Bits definition for RTC_TSDR register  *****************/
11596  #define RTC_TSDR_WDU_Pos              (13U)
11597  #define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
11598  #define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk
11599  #define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
11600  #define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
11601  #define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
11602  #define RTC_TSDR_MT_Pos               (12U)
11603  #define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
11604  #define RTC_TSDR_MT                   RTC_TSDR_MT_Msk
11605  #define RTC_TSDR_MU_Pos               (8U)
11606  #define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
11607  #define RTC_TSDR_MU                   RTC_TSDR_MU_Msk
11608  #define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
11609  #define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
11610  #define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
11611  #define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
11612  #define RTC_TSDR_DT_Pos               (4U)
11613  #define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
11614  #define RTC_TSDR_DT                   RTC_TSDR_DT_Msk
11615  #define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
11616  #define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
11617  #define RTC_TSDR_DU_Pos               (0U)
11618  #define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
11619  #define RTC_TSDR_DU                   RTC_TSDR_DU_Msk
11620  #define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
11621  #define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
11622  #define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
11623  #define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
11624  
11625  /********************  Bits definition for RTC_TSSSR register  ****************/
11626  #define RTC_TSSSR_SS_Pos              (0U)
11627  #define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
11628  #define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk
11629  
11630  /********************  Bits definition for RTC_CAL register  *****************/
11631  #define RTC_CALR_CALP_Pos             (15U)
11632  #define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
11633  #define RTC_CALR_CALP                 RTC_CALR_CALP_Msk
11634  #define RTC_CALR_CALW8_Pos            (14U)
11635  #define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
11636  #define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk
11637  #define RTC_CALR_CALW16_Pos           (13U)
11638  #define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
11639  #define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk
11640  #define RTC_CALR_CALM_Pos             (0U)
11641  #define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
11642  #define RTC_CALR_CALM                 RTC_CALR_CALM_Msk
11643  #define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
11644  #define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
11645  #define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
11646  #define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
11647  #define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
11648  #define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
11649  #define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
11650  #define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
11651  #define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
11652  
11653  /********************  Bits definition for RTC_TAFCR register  ****************/
11654  #define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)
11655  #define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
11656  #define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk
11657  #define RTC_TAFCR_TSINSEL_Pos         (17U)
11658  #define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
11659  #define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk
11660  #define RTC_TAFCR_TAMP1INSEL_Pos      (16U)
11661  #define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
11662  #define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk
11663  #define RTC_TAFCR_TAMPPUDIS_Pos       (15U)
11664  #define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
11665  #define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk
11666  #define RTC_TAFCR_TAMPPRCH_Pos        (13U)
11667  #define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
11668  #define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk
11669  #define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
11670  #define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
11671  #define RTC_TAFCR_TAMPFLT_Pos         (11U)
11672  #define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
11673  #define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk
11674  #define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
11675  #define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
11676  #define RTC_TAFCR_TAMPFREQ_Pos        (8U)
11677  #define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
11678  #define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk
11679  #define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
11680  #define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
11681  #define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
11682  #define RTC_TAFCR_TAMPTS_Pos          (7U)
11683  #define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
11684  #define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk
11685  #define RTC_TAFCR_TAMP2TRG_Pos        (4U)
11686  #define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
11687  #define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk
11688  #define RTC_TAFCR_TAMP2E_Pos          (3U)
11689  #define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
11690  #define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk
11691  #define RTC_TAFCR_TAMPIE_Pos          (2U)
11692  #define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
11693  #define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk
11694  #define RTC_TAFCR_TAMP1TRG_Pos        (1U)
11695  #define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
11696  #define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk
11697  #define RTC_TAFCR_TAMP1E_Pos          (0U)
11698  #define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
11699  #define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk
11700  
11701  /* Legacy defines */
11702  #define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
11703  
11704  /********************  Bits definition for RTC_ALRMASSR register  *************/
11705  #define RTC_ALRMASSR_MASKSS_Pos       (24U)
11706  #define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
11707  #define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk
11708  #define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
11709  #define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
11710  #define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
11711  #define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
11712  #define RTC_ALRMASSR_SS_Pos           (0U)
11713  #define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
11714  #define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk
11715  
11716  /********************  Bits definition for RTC_ALRMBSSR register  *************/
11717  #define RTC_ALRMBSSR_MASKSS_Pos       (24U)
11718  #define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
11719  #define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk
11720  #define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
11721  #define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
11722  #define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
11723  #define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
11724  #define RTC_ALRMBSSR_SS_Pos           (0U)
11725  #define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
11726  #define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk
11727  
11728  /********************  Bits definition for RTC_BKP0R register  ****************/
11729  #define RTC_BKP0R_Pos                 (0U)
11730  #define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
11731  #define RTC_BKP0R                     RTC_BKP0R_Msk
11732  
11733  /********************  Bits definition for RTC_BKP1R register  ****************/
11734  #define RTC_BKP1R_Pos                 (0U)
11735  #define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
11736  #define RTC_BKP1R                     RTC_BKP1R_Msk
11737  
11738  /********************  Bits definition for RTC_BKP2R register  ****************/
11739  #define RTC_BKP2R_Pos                 (0U)
11740  #define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
11741  #define RTC_BKP2R                     RTC_BKP2R_Msk
11742  
11743  /********************  Bits definition for RTC_BKP3R register  ****************/
11744  #define RTC_BKP3R_Pos                 (0U)
11745  #define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
11746  #define RTC_BKP3R                     RTC_BKP3R_Msk
11747  
11748  /********************  Bits definition for RTC_BKP4R register  ****************/
11749  #define RTC_BKP4R_Pos                 (0U)
11750  #define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
11751  #define RTC_BKP4R                     RTC_BKP4R_Msk
11752  
11753  /********************  Bits definition for RTC_BKP5R register  ****************/
11754  #define RTC_BKP5R_Pos                 (0U)
11755  #define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
11756  #define RTC_BKP5R                     RTC_BKP5R_Msk
11757  
11758  /********************  Bits definition for RTC_BKP6R register  ****************/
11759  #define RTC_BKP6R_Pos                 (0U)
11760  #define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
11761  #define RTC_BKP6R                     RTC_BKP6R_Msk
11762  
11763  /********************  Bits definition for RTC_BKP7R register  ****************/
11764  #define RTC_BKP7R_Pos                 (0U)
11765  #define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
11766  #define RTC_BKP7R                     RTC_BKP7R_Msk
11767  
11768  /********************  Bits definition for RTC_BKP8R register  ****************/
11769  #define RTC_BKP8R_Pos                 (0U)
11770  #define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
11771  #define RTC_BKP8R                     RTC_BKP8R_Msk
11772  
11773  /********************  Bits definition for RTC_BKP9R register  ****************/
11774  #define RTC_BKP9R_Pos                 (0U)
11775  #define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
11776  #define RTC_BKP9R                     RTC_BKP9R_Msk
11777  
11778  /********************  Bits definition for RTC_BKP10R register  ***************/
11779  #define RTC_BKP10R_Pos                (0U)
11780  #define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
11781  #define RTC_BKP10R                    RTC_BKP10R_Msk
11782  
11783  /********************  Bits definition for RTC_BKP11R register  ***************/
11784  #define RTC_BKP11R_Pos                (0U)
11785  #define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
11786  #define RTC_BKP11R                    RTC_BKP11R_Msk
11787  
11788  /********************  Bits definition for RTC_BKP12R register  ***************/
11789  #define RTC_BKP12R_Pos                (0U)
11790  #define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
11791  #define RTC_BKP12R                    RTC_BKP12R_Msk
11792  
11793  /********************  Bits definition for RTC_BKP13R register  ***************/
11794  #define RTC_BKP13R_Pos                (0U)
11795  #define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
11796  #define RTC_BKP13R                    RTC_BKP13R_Msk
11797  
11798  /********************  Bits definition for RTC_BKP14R register  ***************/
11799  #define RTC_BKP14R_Pos                (0U)
11800  #define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
11801  #define RTC_BKP14R                    RTC_BKP14R_Msk
11802  
11803  /********************  Bits definition for RTC_BKP15R register  ***************/
11804  #define RTC_BKP15R_Pos                (0U)
11805  #define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
11806  #define RTC_BKP15R                    RTC_BKP15R_Msk
11807  
11808  /********************  Bits definition for RTC_BKP16R register  ***************/
11809  #define RTC_BKP16R_Pos                (0U)
11810  #define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
11811  #define RTC_BKP16R                    RTC_BKP16R_Msk
11812  
11813  /********************  Bits definition for RTC_BKP17R register  ***************/
11814  #define RTC_BKP17R_Pos                (0U)
11815  #define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
11816  #define RTC_BKP17R                    RTC_BKP17R_Msk
11817  
11818  /********************  Bits definition for RTC_BKP18R register  ***************/
11819  #define RTC_BKP18R_Pos                (0U)
11820  #define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
11821  #define RTC_BKP18R                    RTC_BKP18R_Msk
11822  
11823  /********************  Bits definition for RTC_BKP19R register  ***************/
11824  #define RTC_BKP19R_Pos                (0U)
11825  #define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
11826  #define RTC_BKP19R                    RTC_BKP19R_Msk
11827  
11828  /******************** Number of backup registers ******************************/
11829  #define RTC_BKP_NUMBER                       0x000000014U
11830  
11831  /******************************************************************************/
11832  /*                                                                            */
11833  /*                          Serial Audio Interface                            */
11834  /*                                                                            */
11835  /******************************************************************************/
11836  /********************  Bit definition for SAI_GCR register  *******************/
11837  #define SAI_GCR_SYNCIN_Pos         (0U)
11838  #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
11839  #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
11840  #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
11841  #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
11842  
11843  #define SAI_GCR_SYNCOUT_Pos        (4U)
11844  #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
11845  #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
11846  #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
11847  #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
11848  
11849  /*******************  Bit definition for SAI_xCR1 register  *******************/
11850  #define SAI_xCR1_MODE_Pos          (0U)
11851  #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
11852  #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
11853  #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
11854  #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
11855  
11856  #define SAI_xCR1_PRTCFG_Pos        (2U)
11857  #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
11858  #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
11859  #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
11860  #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
11861  
11862  #define SAI_xCR1_DS_Pos            (5U)
11863  #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
11864  #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
11865  #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
11866  #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
11867  #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
11868  
11869  #define SAI_xCR1_LSBFIRST_Pos      (8U)
11870  #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
11871  #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
11872  #define SAI_xCR1_CKSTR_Pos         (9U)
11873  #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
11874  #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
11875  
11876  #define SAI_xCR1_SYNCEN_Pos        (10U)
11877  #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
11878  #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
11879  #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
11880  #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
11881  
11882  #define SAI_xCR1_MONO_Pos          (12U)
11883  #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
11884  #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
11885  #define SAI_xCR1_OUTDRIV_Pos       (13U)
11886  #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
11887  #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
11888  #define SAI_xCR1_SAIEN_Pos         (16U)
11889  #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
11890  #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
11891  #define SAI_xCR1_DMAEN_Pos         (17U)
11892  #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
11893  #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
11894  #define SAI_xCR1_NODIV_Pos         (19U)
11895  #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
11896  #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
11897  
11898  #define SAI_xCR1_MCKDIV_Pos        (20U)
11899  #define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
11900  #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
11901  #define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */
11902  #define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */
11903  #define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */
11904  #define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */
11905  
11906  /*******************  Bit definition for SAI_xCR2 register  *******************/
11907  #define SAI_xCR2_FTH_Pos           (0U)
11908  #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
11909  #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
11910  #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
11911  #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
11912  #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
11913  
11914  #define SAI_xCR2_FFLUSH_Pos        (3U)
11915  #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
11916  #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
11917  #define SAI_xCR2_TRIS_Pos          (4U)
11918  #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
11919  #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
11920  #define SAI_xCR2_MUTE_Pos          (5U)
11921  #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
11922  #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
11923  #define SAI_xCR2_MUTEVAL_Pos       (6U)
11924  #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
11925  #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
11926  
11927  #define SAI_xCR2_MUTECNT_Pos       (7U)
11928  #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
11929  #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
11930  #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
11931  #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
11932  #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
11933  #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
11934  #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
11935  #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
11936  
11937  #define SAI_xCR2_CPL_Pos           (13U)
11938  #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
11939  #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
11940  
11941  #define SAI_xCR2_COMP_Pos          (14U)
11942  #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
11943  #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
11944  #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
11945  #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
11946  
11947  /******************  Bit definition for SAI_xFRCR register  *******************/
11948  #define SAI_xFRCR_FRL_Pos          (0U)
11949  #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
11950  #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
11951  #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
11952  #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
11953  #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
11954  #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
11955  #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
11956  #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
11957  #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
11958  #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
11959  
11960  #define SAI_xFRCR_FSALL_Pos        (8U)
11961  #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
11962  #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
11963  #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
11964  #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
11965  #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
11966  #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
11967  #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
11968  #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
11969  #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
11970  
11971  #define SAI_xFRCR_FSDEF_Pos        (16U)
11972  #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
11973  #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
11974  #define SAI_xFRCR_FSPOL_Pos        (17U)
11975  #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
11976  #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
11977  #define SAI_xFRCR_FSOFF_Pos        (18U)
11978  #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
11979  #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
11980  /* Legacy defines */
11981  #define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
11982  
11983  /******************  Bit definition for SAI_xSLOTR register  *******************/
11984  #define SAI_xSLOTR_FBOFF_Pos       (0U)
11985  #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
11986  #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
11987  #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
11988  #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
11989  #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
11990  #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
11991  #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
11992  
11993  #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
11994  #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
11995  #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
11996  #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
11997  #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
11998  
11999  #define SAI_xSLOTR_NBSLOT_Pos      (8U)
12000  #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
12001  #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
12002  #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
12003  #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
12004  #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
12005  #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
12006  
12007  #define SAI_xSLOTR_SLOTEN_Pos      (16U)
12008  #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
12009  #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
12010  
12011  /*******************  Bit definition for SAI_xIMR register  *******************/
12012  #define SAI_xIMR_OVRUDRIE_Pos      (0U)
12013  #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
12014  #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
12015  #define SAI_xIMR_MUTEDETIE_Pos     (1U)
12016  #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
12017  #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
12018  #define SAI_xIMR_WCKCFGIE_Pos      (2U)
12019  #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
12020  #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
12021  #define SAI_xIMR_FREQIE_Pos        (3U)
12022  #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
12023  #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
12024  #define SAI_xIMR_CNRDYIE_Pos       (4U)
12025  #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
12026  #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
12027  #define SAI_xIMR_AFSDETIE_Pos      (5U)
12028  #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
12029  #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
12030  #define SAI_xIMR_LFSDETIE_Pos      (6U)
12031  #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
12032  #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
12033  
12034  /********************  Bit definition for SAI_xSR register  *******************/
12035  #define SAI_xSR_OVRUDR_Pos         (0U)
12036  #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
12037  #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
12038  #define SAI_xSR_MUTEDET_Pos        (1U)
12039  #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
12040  #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
12041  #define SAI_xSR_WCKCFG_Pos         (2U)
12042  #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
12043  #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
12044  #define SAI_xSR_FREQ_Pos           (3U)
12045  #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
12046  #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
12047  #define SAI_xSR_CNRDY_Pos          (4U)
12048  #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
12049  #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
12050  #define SAI_xSR_AFSDET_Pos         (5U)
12051  #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
12052  #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
12053  #define SAI_xSR_LFSDET_Pos         (6U)
12054  #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
12055  #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
12056  
12057  #define SAI_xSR_FLVL_Pos           (16U)
12058  #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
12059  #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
12060  #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
12061  #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
12062  #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
12063  
12064  /******************  Bit definition for SAI_xCLRFR register  ******************/
12065  #define SAI_xCLRFR_COVRUDR_Pos     (0U)
12066  #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
12067  #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
12068  #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
12069  #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
12070  #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
12071  #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
12072  #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
12073  #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
12074  #define SAI_xCLRFR_CFREQ_Pos       (3U)
12075  #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
12076  #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
12077  #define SAI_xCLRFR_CCNRDY_Pos      (4U)
12078  #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
12079  #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
12080  #define SAI_xCLRFR_CAFSDET_Pos     (5U)
12081  #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
12082  #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
12083  #define SAI_xCLRFR_CLFSDET_Pos     (6U)
12084  #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
12085  #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
12086  
12087  /******************  Bit definition for SAI_xDR register  ******************/
12088  #define SAI_xDR_DATA_Pos           (0U)
12089  #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
12090  #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
12091  
12092  /******************************************************************************/
12093  /*                                                                            */
12094  /*                              SPDIF-RX Interface                            */
12095  /*                                                                            */
12096  /******************************************************************************/
12097  /********************  Bit definition for SPDIFRX_CR register  *******************/
12098  #define SPDIFRX_CR_SPDIFEN_Pos      (0U)
12099  #define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)           /*!< 0x00000003 */
12100  #define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
12101  #define SPDIFRX_CR_RXDMAEN_Pos      (2U)
12102  #define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)           /*!< 0x00000004 */
12103  #define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
12104  #define SPDIFRX_CR_RXSTEO_Pos       (3U)
12105  #define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)            /*!< 0x00000008 */
12106  #define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
12107  #define SPDIFRX_CR_DRFMT_Pos        (4U)
12108  #define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)             /*!< 0x00000030 */
12109  #define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
12110  #define SPDIFRX_CR_PMSK_Pos         (6U)
12111  #define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)              /*!< 0x00000040 */
12112  #define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
12113  #define SPDIFRX_CR_VMSK_Pos         (7U)
12114  #define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)              /*!< 0x00000080 */
12115  #define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
12116  #define SPDIFRX_CR_CUMSK_Pos        (8U)
12117  #define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)             /*!< 0x00000100 */
12118  #define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
12119  #define SPDIFRX_CR_PTMSK_Pos        (9U)
12120  #define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)             /*!< 0x00000200 */
12121  #define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
12122  #define SPDIFRX_CR_CBDMAEN_Pos      (10U)
12123  #define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)           /*!< 0x00000400 */
12124  #define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
12125  #define SPDIFRX_CR_CHSEL_Pos        (11U)
12126  #define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)             /*!< 0x00000800 */
12127  #define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
12128  #define SPDIFRX_CR_NBTR_Pos         (12U)
12129  #define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)              /*!< 0x00003000 */
12130  #define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
12131  #define SPDIFRX_CR_WFA_Pos          (14U)
12132  #define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)               /*!< 0x00004000 */
12133  #define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
12134  #define SPDIFRX_CR_INSEL_Pos        (16U)
12135  #define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)             /*!< 0x00070000 */
12136  #define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIFRX input selection */
12137  
12138  /*******************  Bit definition for SPDIFRX_IMR register  *******************/
12139  #define SPDIFRX_IMR_RXNEIE_Pos      (0U)
12140  #define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)           /*!< 0x00000001 */
12141  #define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
12142  #define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
12143  #define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)          /*!< 0x00000002 */
12144  #define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
12145  #define SPDIFRX_IMR_PERRIE_Pos      (2U)
12146  #define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)           /*!< 0x00000004 */
12147  #define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
12148  #define SPDIFRX_IMR_OVRIE_Pos       (3U)
12149  #define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)            /*!< 0x00000008 */
12150  #define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
12151  #define SPDIFRX_IMR_SBLKIE_Pos      (4U)
12152  #define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)           /*!< 0x00000010 */
12153  #define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
12154  #define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
12155  #define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)          /*!< 0x00000020 */
12156  #define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
12157  #define SPDIFRX_IMR_IFEIE_Pos       (6U)
12158  #define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)            /*!< 0x00000040 */
12159  #define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
12160  
12161  /*******************  Bit definition for SPDIFRX_SR register  *******************/
12162  #define SPDIFRX_SR_RXNE_Pos         (0U)
12163  #define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)              /*!< 0x00000001 */
12164  #define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
12165  #define SPDIFRX_SR_CSRNE_Pos        (1U)
12166  #define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)             /*!< 0x00000002 */
12167  #define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
12168  #define SPDIFRX_SR_PERR_Pos         (2U)
12169  #define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)              /*!< 0x00000004 */
12170  #define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
12171  #define SPDIFRX_SR_OVR_Pos          (3U)
12172  #define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)               /*!< 0x00000008 */
12173  #define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
12174  #define SPDIFRX_SR_SBD_Pos          (4U)
12175  #define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)               /*!< 0x00000010 */
12176  #define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
12177  #define SPDIFRX_SR_SYNCD_Pos        (5U)
12178  #define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)             /*!< 0x00000020 */
12179  #define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
12180  #define SPDIFRX_SR_FERR_Pos         (6U)
12181  #define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)              /*!< 0x00000040 */
12182  #define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
12183  #define SPDIFRX_SR_SERR_Pos         (7U)
12184  #define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)              /*!< 0x00000080 */
12185  #define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
12186  #define SPDIFRX_SR_TERR_Pos         (8U)
12187  #define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)              /*!< 0x00000100 */
12188  #define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
12189  #define SPDIFRX_SR_WIDTH5_Pos       (16U)
12190  #define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)         /*!< 0x7FFF0000 */
12191  #define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with SPDIFRX_clk        */
12192  
12193  /*******************  Bit definition for SPDIFRX_IFCR register  *******************/
12194  #define SPDIFRX_IFCR_PERRCF_Pos     (2U)
12195  #define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)          /*!< 0x00000004 */
12196  #define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
12197  #define SPDIFRX_IFCR_OVRCF_Pos      (3U)
12198  #define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)           /*!< 0x00000008 */
12199  #define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
12200  #define SPDIFRX_IFCR_SBDCF_Pos      (4U)
12201  #define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)           /*!< 0x00000010 */
12202  #define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
12203  #define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
12204  #define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)         /*!< 0x00000020 */
12205  #define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
12206  
12207  /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
12208  #define SPDIFRX_DR0_DR_Pos          (0U)
12209  #define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)          /*!< 0x00FFFFFF */
12210  #define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
12211  #define SPDIFRX_DR0_PE_Pos          (24U)
12212  #define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)               /*!< 0x01000000 */
12213  #define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
12214  #define SPDIFRX_DR0_V_Pos           (25U)
12215  #define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)                /*!< 0x02000000 */
12216  #define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
12217  #define SPDIFRX_DR0_U_Pos           (26U)
12218  #define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)                /*!< 0x04000000 */
12219  #define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
12220  #define SPDIFRX_DR0_C_Pos           (27U)
12221  #define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)                /*!< 0x08000000 */
12222  #define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
12223  #define SPDIFRX_DR0_PT_Pos          (28U)
12224  #define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)               /*!< 0x30000000 */
12225  #define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
12226  
12227  /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
12228  #define SPDIFRX_DR1_DR_Pos          (8U)
12229  #define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)          /*!< 0xFFFFFF00 */
12230  #define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
12231  #define SPDIFRX_DR1_PT_Pos          (4U)
12232  #define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)               /*!< 0x00000030 */
12233  #define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
12234  #define SPDIFRX_DR1_C_Pos           (3U)
12235  #define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)                /*!< 0x00000008 */
12236  #define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
12237  #define SPDIFRX_DR1_U_Pos           (2U)
12238  #define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)                /*!< 0x00000004 */
12239  #define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
12240  #define SPDIFRX_DR1_V_Pos           (1U)
12241  #define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)                /*!< 0x00000002 */
12242  #define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
12243  #define SPDIFRX_DR1_PE_Pos          (0U)
12244  #define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)               /*!< 0x00000001 */
12245  #define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
12246  
12247  /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
12248  #define SPDIFRX_DR1_DRNL1_Pos       (16U)
12249  #define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)         /*!< 0xFFFF0000 */
12250  #define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
12251  #define SPDIFRX_DR1_DRNL2_Pos       (0U)
12252  #define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)         /*!< 0x0000FFFF */
12253  #define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
12254  
12255  /*******************  Bit definition for SPDIFRX_CSR register   *******************/
12256  #define SPDIFRX_CSR_USR_Pos         (0U)
12257  #define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)           /*!< 0x0000FFFF */
12258  #define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
12259  #define SPDIFRX_CSR_CS_Pos          (16U)
12260  #define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)              /*!< 0x00FF0000 */
12261  #define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
12262  #define SPDIFRX_CSR_SOB_Pos         (24U)
12263  #define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)              /*!< 0x01000000 */
12264  #define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
12265  
12266  /*******************  Bit definition for SPDIFRX_DIR register    *******************/
12267  #define SPDIFRX_DIR_THI_Pos         (0U)
12268  #define SPDIFRX_DIR_THI_Msk         (0x13FFUL << SPDIFRX_DIR_THI_Pos)           /*!< 0x000013FF */
12269  #define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
12270  #define SPDIFRX_DIR_TLO_Pos         (16U)
12271  #define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)           /*!< 0x1FFF0000 */
12272  #define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
12273  
12274  
12275  /******************************************************************************/
12276  /*                                                                            */
12277  /*                          SD host Interface                                 */
12278  /*                                                                            */
12279  /******************************************************************************/
12280  /******************  Bit definition for SDIO_POWER register  ******************/
12281  #define SDIO_POWER_PWRCTRL_Pos         (0U)
12282  #define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
12283  #define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
12284  #define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
12285  #define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
12286  
12287  /******************  Bit definition for SDIO_CLKCR register  ******************/
12288  #define SDIO_CLKCR_CLKDIV_Pos          (0U)
12289  #define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
12290  #define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
12291  #define SDIO_CLKCR_CLKEN_Pos           (8U)
12292  #define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
12293  #define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
12294  #define SDIO_CLKCR_PWRSAV_Pos          (9U)
12295  #define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
12296  #define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
12297  #define SDIO_CLKCR_BYPASS_Pos          (10U)
12298  #define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
12299  #define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
12300  
12301  #define SDIO_CLKCR_WIDBUS_Pos          (11U)
12302  #define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
12303  #define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
12304  #define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
12305  #define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
12306  
12307  #define SDIO_CLKCR_NEGEDGE_Pos         (13U)
12308  #define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
12309  #define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
12310  #define SDIO_CLKCR_HWFC_EN_Pos         (14U)
12311  #define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
12312  #define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
12313  
12314  /*******************  Bit definition for SDIO_ARG register  *******************/
12315  #define SDIO_ARG_CMDARG_Pos            (0U)
12316  #define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
12317  #define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
12318  
12319  /*******************  Bit definition for SDIO_CMD register  *******************/
12320  #define SDIO_CMD_CMDINDEX_Pos          (0U)
12321  #define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
12322  #define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
12323  
12324  #define SDIO_CMD_WAITRESP_Pos          (6U)
12325  #define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
12326  #define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
12327  #define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
12328  #define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
12329  
12330  #define SDIO_CMD_WAITINT_Pos           (8U)
12331  #define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
12332  #define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
12333  #define SDIO_CMD_WAITPEND_Pos          (9U)
12334  #define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
12335  #define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
12336  #define SDIO_CMD_CPSMEN_Pos            (10U)
12337  #define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
12338  #define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
12339  #define SDIO_CMD_SDIOSUSPEND_Pos       (11U)
12340  #define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
12341  #define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
12342  
12343  /*****************  Bit definition for SDIO_RESPCMD register  *****************/
12344  #define SDIO_RESPCMD_RESPCMD_Pos       (0U)
12345  #define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
12346  #define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
12347  
12348  /******************  Bit definition for SDIO_RESP0 register  ******************/
12349  #define SDIO_RESP0_CARDSTATUS0_Pos     (0U)
12350  #define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
12351  #define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
12352  
12353  /******************  Bit definition for SDIO_RESP1 register  ******************/
12354  #define SDIO_RESP1_CARDSTATUS1_Pos     (0U)
12355  #define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
12356  #define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
12357  
12358  /******************  Bit definition for SDIO_RESP2 register  ******************/
12359  #define SDIO_RESP2_CARDSTATUS2_Pos     (0U)
12360  #define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
12361  #define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
12362  
12363  /******************  Bit definition for SDIO_RESP3 register  ******************/
12364  #define SDIO_RESP3_CARDSTATUS3_Pos     (0U)
12365  #define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
12366  #define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
12367  
12368  /******************  Bit definition for SDIO_RESP4 register  ******************/
12369  #define SDIO_RESP4_CARDSTATUS4_Pos     (0U)
12370  #define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
12371  #define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
12372  
12373  /******************  Bit definition for SDIO_DTIMER register  *****************/
12374  #define SDIO_DTIMER_DATATIME_Pos       (0U)
12375  #define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
12376  #define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
12377  
12378  /******************  Bit definition for SDIO_DLEN register  *******************/
12379  #define SDIO_DLEN_DATALENGTH_Pos       (0U)
12380  #define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
12381  #define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
12382  
12383  /******************  Bit definition for SDIO_DCTRL register  ******************/
12384  #define SDIO_DCTRL_DTEN_Pos            (0U)
12385  #define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
12386  #define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
12387  #define SDIO_DCTRL_DTDIR_Pos           (1U)
12388  #define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
12389  #define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
12390  #define SDIO_DCTRL_DTMODE_Pos          (2U)
12391  #define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
12392  #define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
12393  #define SDIO_DCTRL_DMAEN_Pos           (3U)
12394  #define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
12395  #define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
12396  
12397  #define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)
12398  #define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
12399  #define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
12400  #define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
12401  #define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
12402  #define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
12403  #define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
12404  
12405  #define SDIO_DCTRL_RWSTART_Pos         (8U)
12406  #define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
12407  #define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
12408  #define SDIO_DCTRL_RWSTOP_Pos          (9U)
12409  #define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
12410  #define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
12411  #define SDIO_DCTRL_RWMOD_Pos           (10U)
12412  #define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
12413  #define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
12414  #define SDIO_DCTRL_SDIOEN_Pos          (11U)
12415  #define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
12416  #define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
12417  
12418  /******************  Bit definition for SDIO_DCOUNT register  *****************/
12419  #define SDIO_DCOUNT_DATACOUNT_Pos      (0U)
12420  #define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
12421  #define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
12422  
12423  /******************  Bit definition for SDIO_STA register  ********************/
12424  #define SDIO_STA_CCRCFAIL_Pos          (0U)
12425  #define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
12426  #define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
12427  #define SDIO_STA_DCRCFAIL_Pos          (1U)
12428  #define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
12429  #define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
12430  #define SDIO_STA_CTIMEOUT_Pos          (2U)
12431  #define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
12432  #define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
12433  #define SDIO_STA_DTIMEOUT_Pos          (3U)
12434  #define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
12435  #define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
12436  #define SDIO_STA_TXUNDERR_Pos          (4U)
12437  #define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
12438  #define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
12439  #define SDIO_STA_RXOVERR_Pos           (5U)
12440  #define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
12441  #define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
12442  #define SDIO_STA_CMDREND_Pos           (6U)
12443  #define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
12444  #define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
12445  #define SDIO_STA_CMDSENT_Pos           (7U)
12446  #define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
12447  #define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
12448  #define SDIO_STA_DATAEND_Pos           (8U)
12449  #define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
12450  #define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
12451  #define SDIO_STA_DBCKEND_Pos           (10U)
12452  #define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
12453  #define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
12454  #define SDIO_STA_CMDACT_Pos            (11U)
12455  #define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
12456  #define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
12457  #define SDIO_STA_TXACT_Pos             (12U)
12458  #define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
12459  #define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
12460  #define SDIO_STA_RXACT_Pos             (13U)
12461  #define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
12462  #define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
12463  #define SDIO_STA_TXFIFOHE_Pos          (14U)
12464  #define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
12465  #define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
12466  #define SDIO_STA_RXFIFOHF_Pos          (15U)
12467  #define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
12468  #define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
12469  #define SDIO_STA_TXFIFOF_Pos           (16U)
12470  #define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
12471  #define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
12472  #define SDIO_STA_RXFIFOF_Pos           (17U)
12473  #define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
12474  #define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
12475  #define SDIO_STA_TXFIFOE_Pos           (18U)
12476  #define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
12477  #define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
12478  #define SDIO_STA_RXFIFOE_Pos           (19U)
12479  #define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
12480  #define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
12481  #define SDIO_STA_TXDAVL_Pos            (20U)
12482  #define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
12483  #define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
12484  #define SDIO_STA_RXDAVL_Pos            (21U)
12485  #define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
12486  #define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
12487  #define SDIO_STA_SDIOIT_Pos            (22U)
12488  #define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
12489  #define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
12490  
12491  /*******************  Bit definition for SDIO_ICR register  *******************/
12492  #define SDIO_ICR_CCRCFAILC_Pos         (0U)
12493  #define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
12494  #define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
12495  #define SDIO_ICR_DCRCFAILC_Pos         (1U)
12496  #define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
12497  #define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
12498  #define SDIO_ICR_CTIMEOUTC_Pos         (2U)
12499  #define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
12500  #define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
12501  #define SDIO_ICR_DTIMEOUTC_Pos         (3U)
12502  #define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
12503  #define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
12504  #define SDIO_ICR_TXUNDERRC_Pos         (4U)
12505  #define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
12506  #define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
12507  #define SDIO_ICR_RXOVERRC_Pos          (5U)
12508  #define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
12509  #define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
12510  #define SDIO_ICR_CMDRENDC_Pos          (6U)
12511  #define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
12512  #define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
12513  #define SDIO_ICR_CMDSENTC_Pos          (7U)
12514  #define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
12515  #define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
12516  #define SDIO_ICR_DATAENDC_Pos          (8U)
12517  #define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
12518  #define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
12519  #define SDIO_ICR_DBCKENDC_Pos          (10U)
12520  #define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
12521  #define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
12522  #define SDIO_ICR_SDIOITC_Pos           (22U)
12523  #define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
12524  #define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
12525  
12526  /******************  Bit definition for SDIO_MASK register  *******************/
12527  #define SDIO_MASK_CCRCFAILIE_Pos       (0U)
12528  #define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
12529  #define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
12530  #define SDIO_MASK_DCRCFAILIE_Pos       (1U)
12531  #define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
12532  #define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
12533  #define SDIO_MASK_CTIMEOUTIE_Pos       (2U)
12534  #define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
12535  #define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
12536  #define SDIO_MASK_DTIMEOUTIE_Pos       (3U)
12537  #define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
12538  #define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
12539  #define SDIO_MASK_TXUNDERRIE_Pos       (4U)
12540  #define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
12541  #define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
12542  #define SDIO_MASK_RXOVERRIE_Pos        (5U)
12543  #define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
12544  #define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
12545  #define SDIO_MASK_CMDRENDIE_Pos        (6U)
12546  #define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
12547  #define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
12548  #define SDIO_MASK_CMDSENTIE_Pos        (7U)
12549  #define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
12550  #define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
12551  #define SDIO_MASK_DATAENDIE_Pos        (8U)
12552  #define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
12553  #define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
12554  #define SDIO_MASK_DBCKENDIE_Pos        (10U)
12555  #define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
12556  #define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
12557  #define SDIO_MASK_CMDACTIE_Pos         (11U)
12558  #define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
12559  #define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
12560  #define SDIO_MASK_TXACTIE_Pos          (12U)
12561  #define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
12562  #define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
12563  #define SDIO_MASK_RXACTIE_Pos          (13U)
12564  #define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
12565  #define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
12566  #define SDIO_MASK_TXFIFOHEIE_Pos       (14U)
12567  #define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
12568  #define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
12569  #define SDIO_MASK_RXFIFOHFIE_Pos       (15U)
12570  #define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
12571  #define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
12572  #define SDIO_MASK_TXFIFOFIE_Pos        (16U)
12573  #define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
12574  #define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
12575  #define SDIO_MASK_RXFIFOFIE_Pos        (17U)
12576  #define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
12577  #define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
12578  #define SDIO_MASK_TXFIFOEIE_Pos        (18U)
12579  #define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
12580  #define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
12581  #define SDIO_MASK_RXFIFOEIE_Pos        (19U)
12582  #define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
12583  #define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
12584  #define SDIO_MASK_TXDAVLIE_Pos         (20U)
12585  #define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
12586  #define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
12587  #define SDIO_MASK_RXDAVLIE_Pos         (21U)
12588  #define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
12589  #define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
12590  #define SDIO_MASK_SDIOITIE_Pos         (22U)
12591  #define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
12592  #define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
12593  
12594  /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
12595  #define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)
12596  #define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
12597  #define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
12598  
12599  /******************  Bit definition for SDIO_FIFO register  *******************/
12600  #define SDIO_FIFO_FIFODATA_Pos         (0U)
12601  #define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
12602  #define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
12603  
12604  /******************************************************************************/
12605  /*                                                                            */
12606  /*                        Serial Peripheral Interface                         */
12607  /*                                                                            */
12608  /******************************************************************************/
12609  #define I2S_APB1_APB2_FEATURE                                                  /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
12610  
12611  /*******************  Bit definition for SPI_CR1 register  ********************/
12612  #define SPI_CR1_CPHA_Pos            (0U)
12613  #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
12614  #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
12615  #define SPI_CR1_CPOL_Pos            (1U)
12616  #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
12617  #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
12618  #define SPI_CR1_MSTR_Pos            (2U)
12619  #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
12620  #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
12621  
12622  #define SPI_CR1_BR_Pos              (3U)
12623  #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
12624  #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
12625  #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
12626  #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
12627  #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
12628  
12629  #define SPI_CR1_SPE_Pos             (6U)
12630  #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
12631  #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
12632  #define SPI_CR1_LSBFIRST_Pos        (7U)
12633  #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
12634  #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
12635  #define SPI_CR1_SSI_Pos             (8U)
12636  #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
12637  #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
12638  #define SPI_CR1_SSM_Pos             (9U)
12639  #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
12640  #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
12641  #define SPI_CR1_RXONLY_Pos          (10U)
12642  #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
12643  #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
12644  #define SPI_CR1_DFF_Pos             (11U)
12645  #define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
12646  #define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
12647  #define SPI_CR1_CRCNEXT_Pos         (12U)
12648  #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
12649  #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
12650  #define SPI_CR1_CRCEN_Pos           (13U)
12651  #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
12652  #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
12653  #define SPI_CR1_BIDIOE_Pos          (14U)
12654  #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
12655  #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
12656  #define SPI_CR1_BIDIMODE_Pos        (15U)
12657  #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
12658  #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
12659  
12660  /*******************  Bit definition for SPI_CR2 register  ********************/
12661  #define SPI_CR2_RXDMAEN_Pos         (0U)
12662  #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
12663  #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
12664  #define SPI_CR2_TXDMAEN_Pos         (1U)
12665  #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
12666  #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
12667  #define SPI_CR2_SSOE_Pos            (2U)
12668  #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
12669  #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
12670  #define SPI_CR2_FRF_Pos             (4U)
12671  #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
12672  #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
12673  #define SPI_CR2_ERRIE_Pos           (5U)
12674  #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
12675  #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
12676  #define SPI_CR2_RXNEIE_Pos          (6U)
12677  #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
12678  #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
12679  #define SPI_CR2_TXEIE_Pos           (7U)
12680  #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
12681  #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
12682  
12683  /********************  Bit definition for SPI_SR register  ********************/
12684  #define SPI_SR_RXNE_Pos             (0U)
12685  #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
12686  #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
12687  #define SPI_SR_TXE_Pos              (1U)
12688  #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
12689  #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
12690  #define SPI_SR_CHSIDE_Pos           (2U)
12691  #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
12692  #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
12693  #define SPI_SR_UDR_Pos              (3U)
12694  #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
12695  #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
12696  #define SPI_SR_CRCERR_Pos           (4U)
12697  #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
12698  #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
12699  #define SPI_SR_MODF_Pos             (5U)
12700  #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
12701  #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
12702  #define SPI_SR_OVR_Pos              (6U)
12703  #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
12704  #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
12705  #define SPI_SR_BSY_Pos              (7U)
12706  #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
12707  #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
12708  #define SPI_SR_FRE_Pos              (8U)
12709  #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
12710  #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
12711  
12712  /********************  Bit definition for SPI_DR register  ********************/
12713  #define SPI_DR_DR_Pos               (0U)
12714  #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
12715  #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
12716  
12717  /*******************  Bit definition for SPI_CRCPR register  ******************/
12718  #define SPI_CRCPR_CRCPOLY_Pos       (0U)
12719  #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
12720  #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
12721  
12722  /******************  Bit definition for SPI_RXCRCR register  ******************/
12723  #define SPI_RXCRCR_RXCRC_Pos        (0U)
12724  #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
12725  #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
12726  
12727  /******************  Bit definition for SPI_TXCRCR register  ******************/
12728  #define SPI_TXCRCR_TXCRC_Pos        (0U)
12729  #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
12730  #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
12731  
12732  /******************  Bit definition for SPI_I2SCFGR register  *****************/
12733  #define SPI_I2SCFGR_CHLEN_Pos       (0U)
12734  #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
12735  #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
12736  
12737  #define SPI_I2SCFGR_DATLEN_Pos      (1U)
12738  #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
12739  #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
12740  #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
12741  #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
12742  
12743  #define SPI_I2SCFGR_CKPOL_Pos       (3U)
12744  #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
12745  #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
12746  
12747  #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
12748  #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
12749  #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
12750  #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
12751  #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
12752  
12753  #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
12754  #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
12755  #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
12756  
12757  #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
12758  #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
12759  #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
12760  #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
12761  #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
12762  
12763  #define SPI_I2SCFGR_I2SE_Pos        (10U)
12764  #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
12765  #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
12766  #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
12767  #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
12768  #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
12769  #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
12770  #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
12771  #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
12772  
12773  /******************  Bit definition for SPI_I2SPR register  *******************/
12774  #define SPI_I2SPR_I2SDIV_Pos        (0U)
12775  #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
12776  #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
12777  #define SPI_I2SPR_ODD_Pos           (8U)
12778  #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
12779  #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
12780  #define SPI_I2SPR_MCKOE_Pos         (9U)
12781  #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
12782  #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
12783  
12784  /******************************************************************************/
12785  /*                                                                            */
12786  /*                                 SYSCFG                                     */
12787  /*                                                                            */
12788  /******************************************************************************/
12789  /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
12790  #define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)
12791  #define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
12792  #define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
12793  #define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
12794  #define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
12795  #define SYSCFG_MEMRMP_MEM_MODE_2             (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
12796  #define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)
12797  #define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
12798  #define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */
12799  #define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)
12800  #define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
12801  #define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */
12802  #define SYSCFG_MEMRMP_SWP_FMC_0              (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
12803  /* Legacy Defines */
12804  #define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC
12805  /******************  Bit definition for SYSCFG_PMC register  ******************/
12806  #define SYSCFG_PMC_ADCxDC2_Pos               (16U)
12807  #define SYSCFG_PMC_ADCxDC2_Msk               (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */
12808  #define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12809  #define SYSCFG_PMC_ADC1DC2_Pos               (16U)
12810  #define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */
12811  #define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12812  #define SYSCFG_PMC_ADC2DC2_Pos               (17U)
12813  #define SYSCFG_PMC_ADC2DC2_Msk               (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */
12814  #define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12815  #define SYSCFG_PMC_ADC3DC2_Pos               (18U)
12816  #define SYSCFG_PMC_ADC3DC2_Msk               (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */
12817  #define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12818  
12819  /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
12820  #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)
12821  #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
12822  #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
12823  #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)
12824  #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
12825  #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
12826  #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)
12827  #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
12828  #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
12829  #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)
12830  #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
12831  #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
12832  /**
12833    * @brief   EXTI0 configuration
12834    */
12835  #define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
12836  #define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
12837  #define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
12838  #define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
12839  #define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
12840  #define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
12841  #define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
12842  #define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
12843  #define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */
12844  #define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */
12845  #define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */
12846  
12847  /**
12848    * @brief   EXTI1 configuration
12849    */
12850  #define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
12851  #define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
12852  #define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
12853  #define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
12854  #define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
12855  #define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
12856  #define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
12857  #define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
12858  #define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */
12859  #define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */
12860  #define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */
12861  
12862  /**
12863    * @brief   EXTI2 configuration
12864    */
12865  #define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
12866  #define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
12867  #define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
12868  #define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
12869  #define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
12870  #define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
12871  #define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
12872  #define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
12873  #define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */
12874  #define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */
12875  #define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */
12876  
12877  /**
12878    * @brief   EXTI3 configuration
12879    */
12880  #define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
12881  #define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
12882  #define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
12883  #define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
12884  #define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
12885  #define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
12886  #define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
12887  #define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
12888  #define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */
12889  #define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */
12890  #define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */
12891  
12892  /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
12893  #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)
12894  #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
12895  #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
12896  #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)
12897  #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
12898  #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
12899  #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)
12900  #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
12901  #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
12902  #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)
12903  #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
12904  #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
12905  
12906  /**
12907    * @brief   EXTI4 configuration
12908    */
12909  #define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
12910  #define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
12911  #define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
12912  #define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
12913  #define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
12914  #define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
12915  #define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
12916  #define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
12917  #define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */
12918  #define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */
12919  #define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */
12920  
12921  /**
12922    * @brief   EXTI5 configuration
12923    */
12924  #define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
12925  #define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
12926  #define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
12927  #define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
12928  #define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
12929  #define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
12930  #define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
12931  #define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
12932  #define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */
12933  #define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */
12934  #define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */
12935  
12936  /**
12937    * @brief   EXTI6 configuration
12938    */
12939  #define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
12940  #define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
12941  #define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
12942  #define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
12943  #define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
12944  #define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
12945  #define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
12946  #define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
12947  #define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */
12948  #define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */
12949  #define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */
12950  
12951  /**
12952    * @brief   EXTI7 configuration
12953    */
12954  #define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
12955  #define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
12956  #define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
12957  #define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
12958  #define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
12959  #define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
12960  #define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
12961  #define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
12962  #define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */
12963  #define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */
12964  #define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */
12965  
12966  /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
12967  #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)
12968  #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
12969  #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
12970  #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)
12971  #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
12972  #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
12973  #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)
12974  #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
12975  #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
12976  #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)
12977  #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
12978  #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
12979  
12980  /**
12981    * @brief   EXTI8 configuration
12982    */
12983  #define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
12984  #define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
12985  #define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
12986  #define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
12987  #define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
12988  #define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
12989  #define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
12990  #define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
12991  #define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */
12992  #define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */
12993  
12994  /**
12995    * @brief   EXTI9 configuration
12996    */
12997  #define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
12998  #define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
12999  #define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
13000  #define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
13001  #define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
13002  #define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
13003  #define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
13004  #define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
13005  #define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */
13006  #define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */
13007  
13008  /**
13009    * @brief   EXTI10 configuration
13010    */
13011  #define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
13012  #define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
13013  #define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
13014  #define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
13015  #define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
13016  #define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
13017  #define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
13018  #define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
13019  #define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */
13020  #define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */
13021  
13022  /**
13023    * @brief   EXTI11 configuration
13024    */
13025  #define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
13026  #define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
13027  #define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
13028  #define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
13029  #define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
13030  #define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
13031  #define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
13032  #define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
13033  #define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */
13034  #define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */
13035  
13036  
13037  /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
13038  #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)
13039  #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
13040  #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
13041  #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)
13042  #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
13043  #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
13044  #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)
13045  #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
13046  #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
13047  #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)
13048  #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
13049  #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
13050  
13051  /**
13052    * @brief   EXTI12 configuration
13053    */
13054  #define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
13055  #define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
13056  #define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
13057  #define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
13058  #define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
13059  #define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
13060  #define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
13061  #define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
13062  #define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */
13063  #define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */
13064  
13065  /**
13066    * @brief   EXTI13 configuration
13067    */
13068  #define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
13069  #define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
13070  #define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
13071  #define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
13072  #define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
13073  #define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
13074  #define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
13075  #define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
13076  #define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */
13077  #define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */
13078  
13079  /**
13080    * @brief   EXTI14 configuration
13081    */
13082  #define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
13083  #define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
13084  #define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
13085  #define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
13086  #define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
13087  #define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
13088  #define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
13089  #define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
13090  #define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */
13091  #define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */
13092  
13093  /**
13094    * @brief   EXTI15 configuration
13095    */
13096  #define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
13097  #define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
13098  #define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
13099  #define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
13100  #define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
13101  #define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
13102  #define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
13103  #define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
13104  #define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */
13105  #define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */
13106  
13107  /******************  Bit definition for SYSCFG_CMPCR register  ****************/
13108  #define SYSCFG_CMPCR_CMP_PD_Pos              (0U)
13109  #define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
13110  #define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
13111  #define SYSCFG_CMPCR_READY_Pos               (8U)
13112  #define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
13113  #define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
13114  /******************  Bit definition for SYSCFG_CFGR register  ****************/
13115  #define SYSCFG_CFGR_FMPI2C1_SCL_Pos          (0U)
13116  #define SYSCFG_CFGR_FMPI2C1_SCL_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
13117  #define SYSCFG_CFGR_FMPI2C1_SCL              SYSCFG_CFGR_FMPI2C1_SCL_Msk       /*!<FM+ drive capability for FMPI2C1_SCL pin */
13118  #define SYSCFG_CFGR_FMPI2C1_SDA_Pos          (1U)
13119  #define SYSCFG_CFGR_FMPI2C1_SDA_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
13120  #define SYSCFG_CFGR_FMPI2C1_SDA              SYSCFG_CFGR_FMPI2C1_SDA_Msk       /*!<FM+ drive capability for FMPI2C1_SDA pin */
13121  
13122  
13123  /******************************************************************************/
13124  /*                                                                            */
13125  /*                                    TIM                                     */
13126  /*                                                                            */
13127  /******************************************************************************/
13128  /*******************  Bit definition for TIM_CR1 register  ********************/
13129  #define TIM_CR1_CEN_Pos           (0U)
13130  #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
13131  #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
13132  #define TIM_CR1_UDIS_Pos          (1U)
13133  #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
13134  #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
13135  #define TIM_CR1_URS_Pos           (2U)
13136  #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
13137  #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
13138  #define TIM_CR1_OPM_Pos           (3U)
13139  #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
13140  #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
13141  #define TIM_CR1_DIR_Pos           (4U)
13142  #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
13143  #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
13144  
13145  #define TIM_CR1_CMS_Pos           (5U)
13146  #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
13147  #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
13148  #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
13149  #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
13150  
13151  #define TIM_CR1_ARPE_Pos          (7U)
13152  #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
13153  #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
13154  
13155  #define TIM_CR1_CKD_Pos           (8U)
13156  #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
13157  #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
13158  #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
13159  #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
13160  
13161  /*******************  Bit definition for TIM_CR2 register  ********************/
13162  #define TIM_CR2_CCPC_Pos          (0U)
13163  #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
13164  #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
13165  #define TIM_CR2_CCUS_Pos          (2U)
13166  #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
13167  #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
13168  #define TIM_CR2_CCDS_Pos          (3U)
13169  #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
13170  #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
13171  
13172  #define TIM_CR2_MMS_Pos           (4U)
13173  #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
13174  #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
13175  #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
13176  #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
13177  #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
13178  
13179  #define TIM_CR2_TI1S_Pos          (7U)
13180  #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
13181  #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
13182  #define TIM_CR2_OIS1_Pos          (8U)
13183  #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
13184  #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
13185  #define TIM_CR2_OIS1N_Pos         (9U)
13186  #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
13187  #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
13188  #define TIM_CR2_OIS2_Pos          (10U)
13189  #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
13190  #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
13191  #define TIM_CR2_OIS2N_Pos         (11U)
13192  #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
13193  #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
13194  #define TIM_CR2_OIS3_Pos          (12U)
13195  #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
13196  #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
13197  #define TIM_CR2_OIS3N_Pos         (13U)
13198  #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
13199  #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
13200  #define TIM_CR2_OIS4_Pos          (14U)
13201  #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
13202  #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
13203  
13204  /*******************  Bit definition for TIM_SMCR register  *******************/
13205  #define TIM_SMCR_SMS_Pos          (0U)
13206  #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
13207  #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
13208  #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
13209  #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
13210  #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
13211  
13212  #define TIM_SMCR_TS_Pos           (4U)
13213  #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
13214  #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
13215  #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
13216  #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
13217  #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
13218  
13219  #define TIM_SMCR_MSM_Pos          (7U)
13220  #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
13221  #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
13222  
13223  #define TIM_SMCR_ETF_Pos          (8U)
13224  #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
13225  #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
13226  #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
13227  #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
13228  #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
13229  #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
13230  
13231  #define TIM_SMCR_ETPS_Pos         (12U)
13232  #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
13233  #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
13234  #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
13235  #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
13236  
13237  #define TIM_SMCR_ECE_Pos          (14U)
13238  #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
13239  #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
13240  #define TIM_SMCR_ETP_Pos          (15U)
13241  #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
13242  #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
13243  
13244  /*******************  Bit definition for TIM_DIER register  *******************/
13245  #define TIM_DIER_UIE_Pos          (0U)
13246  #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
13247  #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
13248  #define TIM_DIER_CC1IE_Pos        (1U)
13249  #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
13250  #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
13251  #define TIM_DIER_CC2IE_Pos        (2U)
13252  #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
13253  #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
13254  #define TIM_DIER_CC3IE_Pos        (3U)
13255  #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
13256  #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
13257  #define TIM_DIER_CC4IE_Pos        (4U)
13258  #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
13259  #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
13260  #define TIM_DIER_COMIE_Pos        (5U)
13261  #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
13262  #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
13263  #define TIM_DIER_TIE_Pos          (6U)
13264  #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
13265  #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
13266  #define TIM_DIER_BIE_Pos          (7U)
13267  #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
13268  #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
13269  #define TIM_DIER_UDE_Pos          (8U)
13270  #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
13271  #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
13272  #define TIM_DIER_CC1DE_Pos        (9U)
13273  #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
13274  #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
13275  #define TIM_DIER_CC2DE_Pos        (10U)
13276  #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
13277  #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
13278  #define TIM_DIER_CC3DE_Pos        (11U)
13279  #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
13280  #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
13281  #define TIM_DIER_CC4DE_Pos        (12U)
13282  #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
13283  #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
13284  #define TIM_DIER_COMDE_Pos        (13U)
13285  #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
13286  #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
13287  #define TIM_DIER_TDE_Pos          (14U)
13288  #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
13289  #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
13290  
13291  /********************  Bit definition for TIM_SR register  ********************/
13292  #define TIM_SR_UIF_Pos            (0U)
13293  #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
13294  #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
13295  #define TIM_SR_CC1IF_Pos          (1U)
13296  #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
13297  #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
13298  #define TIM_SR_CC2IF_Pos          (2U)
13299  #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
13300  #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
13301  #define TIM_SR_CC3IF_Pos          (3U)
13302  #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
13303  #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
13304  #define TIM_SR_CC4IF_Pos          (4U)
13305  #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
13306  #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
13307  #define TIM_SR_COMIF_Pos          (5U)
13308  #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
13309  #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
13310  #define TIM_SR_TIF_Pos            (6U)
13311  #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
13312  #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
13313  #define TIM_SR_BIF_Pos            (7U)
13314  #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
13315  #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
13316  #define TIM_SR_CC1OF_Pos          (9U)
13317  #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
13318  #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
13319  #define TIM_SR_CC2OF_Pos          (10U)
13320  #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
13321  #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
13322  #define TIM_SR_CC3OF_Pos          (11U)
13323  #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
13324  #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
13325  #define TIM_SR_CC4OF_Pos          (12U)
13326  #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
13327  #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
13328  
13329  /*******************  Bit definition for TIM_EGR register  ********************/
13330  #define TIM_EGR_UG_Pos            (0U)
13331  #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
13332  #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
13333  #define TIM_EGR_CC1G_Pos          (1U)
13334  #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
13335  #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
13336  #define TIM_EGR_CC2G_Pos          (2U)
13337  #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
13338  #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
13339  #define TIM_EGR_CC3G_Pos          (3U)
13340  #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
13341  #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
13342  #define TIM_EGR_CC4G_Pos          (4U)
13343  #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
13344  #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
13345  #define TIM_EGR_COMG_Pos          (5U)
13346  #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
13347  #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
13348  #define TIM_EGR_TG_Pos            (6U)
13349  #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
13350  #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
13351  #define TIM_EGR_BG_Pos            (7U)
13352  #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
13353  #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
13354  
13355  /******************  Bit definition for TIM_CCMR1 register  *******************/
13356  #define TIM_CCMR1_CC1S_Pos        (0U)
13357  #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
13358  #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13359  #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
13360  #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
13361  
13362  #define TIM_CCMR1_OC1FE_Pos       (2U)
13363  #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
13364  #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
13365  #define TIM_CCMR1_OC1PE_Pos       (3U)
13366  #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
13367  #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
13368  
13369  #define TIM_CCMR1_OC1M_Pos        (4U)
13370  #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
13371  #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
13372  #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
13373  #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
13374  #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
13375  
13376  #define TIM_CCMR1_OC1CE_Pos       (7U)
13377  #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
13378  #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
13379  
13380  #define TIM_CCMR1_CC2S_Pos        (8U)
13381  #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
13382  #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13383  #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
13384  #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
13385  
13386  #define TIM_CCMR1_OC2FE_Pos       (10U)
13387  #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
13388  #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
13389  #define TIM_CCMR1_OC2PE_Pos       (11U)
13390  #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
13391  #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
13392  
13393  #define TIM_CCMR1_OC2M_Pos        (12U)
13394  #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
13395  #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
13396  #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
13397  #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
13398  #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
13399  
13400  #define TIM_CCMR1_OC2CE_Pos       (15U)
13401  #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
13402  #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
13403  
13404  /*----------------------------------------------------------------------------*/
13405  
13406  #define TIM_CCMR1_IC1PSC_Pos      (2U)
13407  #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
13408  #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
13409  #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
13410  #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
13411  
13412  #define TIM_CCMR1_IC1F_Pos        (4U)
13413  #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
13414  #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
13415  #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
13416  #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
13417  #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
13418  #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
13419  
13420  #define TIM_CCMR1_IC2PSC_Pos      (10U)
13421  #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
13422  #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
13423  #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
13424  #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
13425  
13426  #define TIM_CCMR1_IC2F_Pos        (12U)
13427  #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
13428  #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
13429  #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
13430  #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
13431  #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
13432  #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
13433  
13434  /******************  Bit definition for TIM_CCMR2 register  *******************/
13435  #define TIM_CCMR2_CC3S_Pos        (0U)
13436  #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
13437  #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
13438  #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
13439  #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
13440  
13441  #define TIM_CCMR2_OC3FE_Pos       (2U)
13442  #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
13443  #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
13444  #define TIM_CCMR2_OC3PE_Pos       (3U)
13445  #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
13446  #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
13447  
13448  #define TIM_CCMR2_OC3M_Pos        (4U)
13449  #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
13450  #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
13451  #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
13452  #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
13453  #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
13454  
13455  #define TIM_CCMR2_OC3CE_Pos       (7U)
13456  #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
13457  #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
13458  
13459  #define TIM_CCMR2_CC4S_Pos        (8U)
13460  #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
13461  #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
13462  #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
13463  #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
13464  
13465  #define TIM_CCMR2_OC4FE_Pos       (10U)
13466  #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
13467  #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
13468  #define TIM_CCMR2_OC4PE_Pos       (11U)
13469  #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
13470  #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
13471  
13472  #define TIM_CCMR2_OC4M_Pos        (12U)
13473  #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
13474  #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
13475  #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
13476  #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
13477  #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
13478  
13479  #define TIM_CCMR2_OC4CE_Pos       (15U)
13480  #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
13481  #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
13482  
13483  /*----------------------------------------------------------------------------*/
13484  
13485  #define TIM_CCMR2_IC3PSC_Pos      (2U)
13486  #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
13487  #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
13488  #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
13489  #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
13490  
13491  #define TIM_CCMR2_IC3F_Pos        (4U)
13492  #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
13493  #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
13494  #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
13495  #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
13496  #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
13497  #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
13498  
13499  #define TIM_CCMR2_IC4PSC_Pos      (10U)
13500  #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
13501  #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
13502  #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
13503  #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
13504  
13505  #define TIM_CCMR2_IC4F_Pos        (12U)
13506  #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
13507  #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
13508  #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
13509  #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
13510  #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
13511  #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
13512  
13513  /*******************  Bit definition for TIM_CCER register  *******************/
13514  #define TIM_CCER_CC1E_Pos         (0U)
13515  #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
13516  #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
13517  #define TIM_CCER_CC1P_Pos         (1U)
13518  #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
13519  #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
13520  #define TIM_CCER_CC1NE_Pos        (2U)
13521  #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
13522  #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
13523  #define TIM_CCER_CC1NP_Pos        (3U)
13524  #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
13525  #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
13526  #define TIM_CCER_CC2E_Pos         (4U)
13527  #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
13528  #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
13529  #define TIM_CCER_CC2P_Pos         (5U)
13530  #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
13531  #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
13532  #define TIM_CCER_CC2NE_Pos        (6U)
13533  #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
13534  #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
13535  #define TIM_CCER_CC2NP_Pos        (7U)
13536  #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
13537  #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
13538  #define TIM_CCER_CC3E_Pos         (8U)
13539  #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
13540  #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
13541  #define TIM_CCER_CC3P_Pos         (9U)
13542  #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
13543  #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
13544  #define TIM_CCER_CC3NE_Pos        (10U)
13545  #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
13546  #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
13547  #define TIM_CCER_CC3NP_Pos        (11U)
13548  #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
13549  #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
13550  #define TIM_CCER_CC4E_Pos         (12U)
13551  #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
13552  #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
13553  #define TIM_CCER_CC4P_Pos         (13U)
13554  #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
13555  #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
13556  #define TIM_CCER_CC4NP_Pos        (15U)
13557  #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
13558  #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
13559  
13560  /*******************  Bit definition for TIM_CNT register  ********************/
13561  #define TIM_CNT_CNT_Pos           (0U)
13562  #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
13563  #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
13564  
13565  /*******************  Bit definition for TIM_PSC register  ********************/
13566  #define TIM_PSC_PSC_Pos           (0U)
13567  #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
13568  #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
13569  
13570  /*******************  Bit definition for TIM_ARR register  ********************/
13571  #define TIM_ARR_ARR_Pos           (0U)
13572  #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
13573  #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
13574  
13575  /*******************  Bit definition for TIM_RCR register  ********************/
13576  #define TIM_RCR_REP_Pos           (0U)
13577  #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
13578  #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
13579  
13580  /*******************  Bit definition for TIM_CCR1 register  *******************/
13581  #define TIM_CCR1_CCR1_Pos         (0U)
13582  #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
13583  #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
13584  
13585  /*******************  Bit definition for TIM_CCR2 register  *******************/
13586  #define TIM_CCR2_CCR2_Pos         (0U)
13587  #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
13588  #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
13589  
13590  /*******************  Bit definition for TIM_CCR3 register  *******************/
13591  #define TIM_CCR3_CCR3_Pos         (0U)
13592  #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
13593  #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
13594  
13595  /*******************  Bit definition for TIM_CCR4 register  *******************/
13596  #define TIM_CCR4_CCR4_Pos         (0U)
13597  #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
13598  #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
13599  
13600  /*******************  Bit definition for TIM_BDTR register  *******************/
13601  #define TIM_BDTR_DTG_Pos          (0U)
13602  #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
13603  #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
13604  #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
13605  #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
13606  #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
13607  #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
13608  #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
13609  #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
13610  #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
13611  #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
13612  
13613  #define TIM_BDTR_LOCK_Pos         (8U)
13614  #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
13615  #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
13616  #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
13617  #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
13618  
13619  #define TIM_BDTR_OSSI_Pos         (10U)
13620  #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
13621  #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
13622  #define TIM_BDTR_OSSR_Pos         (11U)
13623  #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
13624  #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
13625  #define TIM_BDTR_BKE_Pos          (12U)
13626  #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
13627  #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
13628  #define TIM_BDTR_BKP_Pos          (13U)
13629  #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
13630  #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
13631  #define TIM_BDTR_AOE_Pos          (14U)
13632  #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
13633  #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
13634  #define TIM_BDTR_MOE_Pos          (15U)
13635  #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
13636  #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
13637  
13638  /*******************  Bit definition for TIM_DCR register  ********************/
13639  #define TIM_DCR_DBA_Pos           (0U)
13640  #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
13641  #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
13642  #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
13643  #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
13644  #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
13645  #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
13646  #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
13647  
13648  #define TIM_DCR_DBL_Pos           (8U)
13649  #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
13650  #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
13651  #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
13652  #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
13653  #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
13654  #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
13655  #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
13656  
13657  /*******************  Bit definition for TIM_DMAR register  *******************/
13658  #define TIM_DMAR_DMAB_Pos         (0U)
13659  #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
13660  #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
13661  
13662  /*******************  Bit definition for TIM_OR register  *********************/
13663  #define TIM_OR_TI1_RMP_Pos        (0U)
13664  #define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
13665  #define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
13666  #define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
13667  #define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
13668  
13669  #define TIM_OR_TI4_RMP_Pos        (6U)
13670  #define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
13671  #define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
13672  #define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
13673  #define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
13674  #define TIM_OR_ITR1_RMP_Pos       (10U)
13675  #define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
13676  #define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
13677  #define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
13678  #define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
13679  
13680  
13681  /******************************************************************************/
13682  /*                                                                            */
13683  /*         Universal Synchronous Asynchronous Receiver Transmitter            */
13684  /*                                                                            */
13685  /******************************************************************************/
13686  /*******************  Bit definition for USART_SR register  *******************/
13687  #define USART_SR_PE_Pos               (0U)
13688  #define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
13689  #define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
13690  #define USART_SR_FE_Pos               (1U)
13691  #define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
13692  #define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
13693  #define USART_SR_NE_Pos               (2U)
13694  #define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
13695  #define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
13696  #define USART_SR_ORE_Pos              (3U)
13697  #define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
13698  #define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
13699  #define USART_SR_IDLE_Pos             (4U)
13700  #define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
13701  #define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
13702  #define USART_SR_RXNE_Pos             (5U)
13703  #define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
13704  #define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
13705  #define USART_SR_TC_Pos               (6U)
13706  #define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
13707  #define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
13708  #define USART_SR_TXE_Pos              (7U)
13709  #define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
13710  #define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
13711  #define USART_SR_LBD_Pos              (8U)
13712  #define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
13713  #define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
13714  #define USART_SR_CTS_Pos              (9U)
13715  #define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
13716  #define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
13717  
13718  /*******************  Bit definition for USART_DR register  *******************/
13719  #define USART_DR_DR_Pos               (0U)
13720  #define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
13721  #define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
13722  
13723  /******************  Bit definition for USART_BRR register  *******************/
13724  #define USART_BRR_DIV_Fraction_Pos    (0U)
13725  #define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
13726  #define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
13727  #define USART_BRR_DIV_Mantissa_Pos    (4U)
13728  #define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
13729  #define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
13730  
13731  /******************  Bit definition for USART_CR1 register  *******************/
13732  #define USART_CR1_SBK_Pos             (0U)
13733  #define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
13734  #define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
13735  #define USART_CR1_RWU_Pos             (1U)
13736  #define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
13737  #define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
13738  #define USART_CR1_RE_Pos              (2U)
13739  #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
13740  #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
13741  #define USART_CR1_TE_Pos              (3U)
13742  #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
13743  #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
13744  #define USART_CR1_IDLEIE_Pos          (4U)
13745  #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
13746  #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
13747  #define USART_CR1_RXNEIE_Pos          (5U)
13748  #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
13749  #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
13750  #define USART_CR1_TCIE_Pos            (6U)
13751  #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
13752  #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
13753  #define USART_CR1_TXEIE_Pos           (7U)
13754  #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
13755  #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
13756  #define USART_CR1_PEIE_Pos            (8U)
13757  #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
13758  #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
13759  #define USART_CR1_PS_Pos              (9U)
13760  #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
13761  #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
13762  #define USART_CR1_PCE_Pos             (10U)
13763  #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
13764  #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
13765  #define USART_CR1_WAKE_Pos            (11U)
13766  #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
13767  #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
13768  #define USART_CR1_M_Pos               (12U)
13769  #define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
13770  #define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
13771  #define USART_CR1_UE_Pos              (13U)
13772  #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
13773  #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
13774  #define USART_CR1_OVER8_Pos           (15U)
13775  #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
13776  #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
13777  
13778  /******************  Bit definition for USART_CR2 register  *******************/
13779  #define USART_CR2_ADD_Pos             (0U)
13780  #define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
13781  #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
13782  #define USART_CR2_LBDL_Pos            (5U)
13783  #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
13784  #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
13785  #define USART_CR2_LBDIE_Pos           (6U)
13786  #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
13787  #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
13788  #define USART_CR2_LBCL_Pos            (8U)
13789  #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
13790  #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
13791  #define USART_CR2_CPHA_Pos            (9U)
13792  #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
13793  #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
13794  #define USART_CR2_CPOL_Pos            (10U)
13795  #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
13796  #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
13797  #define USART_CR2_CLKEN_Pos           (11U)
13798  #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
13799  #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
13800  
13801  #define USART_CR2_STOP_Pos            (12U)
13802  #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
13803  #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
13804  #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
13805  #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
13806  
13807  #define USART_CR2_LINEN_Pos           (14U)
13808  #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
13809  #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
13810  
13811  /******************  Bit definition for USART_CR3 register  *******************/
13812  #define USART_CR3_EIE_Pos             (0U)
13813  #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
13814  #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
13815  #define USART_CR3_IREN_Pos            (1U)
13816  #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
13817  #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
13818  #define USART_CR3_IRLP_Pos            (2U)
13819  #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
13820  #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
13821  #define USART_CR3_HDSEL_Pos           (3U)
13822  #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
13823  #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
13824  #define USART_CR3_NACK_Pos            (4U)
13825  #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
13826  #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
13827  #define USART_CR3_SCEN_Pos            (5U)
13828  #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
13829  #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
13830  #define USART_CR3_DMAR_Pos            (6U)
13831  #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
13832  #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
13833  #define USART_CR3_DMAT_Pos            (7U)
13834  #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
13835  #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
13836  #define USART_CR3_RTSE_Pos            (8U)
13837  #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
13838  #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
13839  #define USART_CR3_CTSE_Pos            (9U)
13840  #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
13841  #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
13842  #define USART_CR3_CTSIE_Pos           (10U)
13843  #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
13844  #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
13845  #define USART_CR3_ONEBIT_Pos          (11U)
13846  #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
13847  #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
13848  
13849  /******************  Bit definition for USART_GTPR register  ******************/
13850  #define USART_GTPR_PSC_Pos            (0U)
13851  #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
13852  #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
13853  #define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
13854  #define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
13855  #define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
13856  #define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
13857  #define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
13858  #define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
13859  #define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
13860  #define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
13861  
13862  #define USART_GTPR_GT_Pos             (8U)
13863  #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
13864  #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
13865  
13866  /******************************************************************************/
13867  /*                                                                            */
13868  /*                            Window WATCHDOG                                 */
13869  /*                                                                            */
13870  /******************************************************************************/
13871  /*******************  Bit definition for WWDG_CR register  ********************/
13872  #define WWDG_CR_T_Pos           (0U)
13873  #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
13874  #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
13875  #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
13876  #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
13877  #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
13878  #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
13879  #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
13880  #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
13881  #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
13882  /* Legacy defines */
13883  #define  WWDG_CR_T0                          WWDG_CR_T_0
13884  #define  WWDG_CR_T1                          WWDG_CR_T_1
13885  #define  WWDG_CR_T2                          WWDG_CR_T_2
13886  #define  WWDG_CR_T3                          WWDG_CR_T_3
13887  #define  WWDG_CR_T4                          WWDG_CR_T_4
13888  #define  WWDG_CR_T5                          WWDG_CR_T_5
13889  #define  WWDG_CR_T6                          WWDG_CR_T_6
13890  
13891  #define WWDG_CR_WDGA_Pos        (7U)
13892  #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
13893  #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
13894  
13895  /*******************  Bit definition for WWDG_CFR register  *******************/
13896  #define WWDG_CFR_W_Pos          (0U)
13897  #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
13898  #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
13899  #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
13900  #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
13901  #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
13902  #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
13903  #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
13904  #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
13905  #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
13906  /* Legacy defines */
13907  #define  WWDG_CFR_W0                         WWDG_CFR_W_0
13908  #define  WWDG_CFR_W1                         WWDG_CFR_W_1
13909  #define  WWDG_CFR_W2                         WWDG_CFR_W_2
13910  #define  WWDG_CFR_W3                         WWDG_CFR_W_3
13911  #define  WWDG_CFR_W4                         WWDG_CFR_W_4
13912  #define  WWDG_CFR_W5                         WWDG_CFR_W_5
13913  #define  WWDG_CFR_W6                         WWDG_CFR_W_6
13914  
13915  #define WWDG_CFR_WDGTB_Pos      (7U)
13916  #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
13917  #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
13918  #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
13919  #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
13920  /* Legacy defines */
13921  #define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
13922  #define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
13923  
13924  #define WWDG_CFR_EWI_Pos        (9U)
13925  #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
13926  #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
13927  
13928  /*******************  Bit definition for WWDG_SR register  ********************/
13929  #define WWDG_SR_EWIF_Pos        (0U)
13930  #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
13931  #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
13932  
13933  
13934  /******************************************************************************/
13935  /*                                                                            */
13936  /*                                DBG                                         */
13937  /*                                                                            */
13938  /******************************************************************************/
13939  /********************  Bit definition for DBGMCU_IDCODE register  *************/
13940  #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
13941  #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
13942  #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
13943  #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
13944  #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
13945  #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
13946  
13947  /********************  Bit definition for DBGMCU_CR register  *****************/
13948  #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
13949  #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
13950  #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
13951  #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
13952  #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
13953  #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
13954  #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
13955  #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
13956  #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
13957  #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
13958  #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
13959  #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
13960  
13961  #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
13962  #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
13963  #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
13964  #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
13965  #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
13966  
13967  /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
13968  #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
13969  #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
13970  #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13971  #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
13972  #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
13973  #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13974  #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)
13975  #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
13976  #define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13977  #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)
13978  #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
13979  #define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13980  #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
13981  #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
13982  #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13983  #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
13984  #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
13985  #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
13986  #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)
13987  #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
13988  #define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
13989  #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)
13990  #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
13991  #define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
13992  #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
13993  #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
13994  #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
13995  #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
13996  #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
13997  #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
13998  #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
13999  #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
14000  #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14001  #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
14002  #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
14003  #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14004  #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
14005  #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
14006  #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14007  #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
14008  #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
14009  #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14010  #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)
14011  #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
14012  #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14013  #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)
14014  #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
14015  #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
14016  #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)
14017  #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
14018  #define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14019  #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)
14020  #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
14021  #define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14022  /* Old IWDGSTOP bit definition, maintained for legacy purpose */
14023  #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
14024  
14025  /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
14026  #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
14027  #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
14028  #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14029  #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)
14030  #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
14031  #define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14032  #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)
14033  #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
14034  #define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14035  #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)
14036  #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
14037  #define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14038  #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)
14039  #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
14040  #define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14041  
14042  /******************************************************************************/
14043  /*                                                                            */
14044  /*                                       USB_OTG                              */
14045  /*                                                                            */
14046  /******************************************************************************/
14047  /********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
14048  #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
14049  #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
14050  #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
14051  #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
14052  #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
14053  #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
14054  #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
14055  #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
14056  #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
14057  #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
14058  #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
14059  #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
14060  #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
14061  #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
14062  #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
14063  #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
14064  #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
14065  #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
14066  #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
14067  #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
14068  #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
14069  #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
14070  #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
14071  #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
14072  #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
14073  #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
14074  #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
14075  #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
14076  #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
14077  #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
14078  #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
14079  #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
14080  #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
14081  #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
14082  #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
14083  #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
14084  #define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
14085  #define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
14086  #define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
14087  #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
14088  #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
14089  #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
14090  #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
14091  #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
14092  #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
14093  #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
14094  #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
14095  #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
14096  #define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
14097  #define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
14098  #define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
14099  #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
14100  #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
14101  #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
14102  
14103  /********************  Bit definition forUSB_OTG_HCFG register  ********************/
14104  
14105  #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
14106  #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
14107  #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
14108  #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
14109  #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
14110  #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
14111  #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
14112  #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
14113  
14114  /********************  Bit definition for USB_OTG_DCFG register  ********************/
14115  
14116  #define USB_OTG_DCFG_DSPD_Pos                    (0U)
14117  #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
14118  #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
14119  #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
14120  #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
14121  #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
14122  #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
14123  #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
14124  
14125  #define USB_OTG_DCFG_DAD_Pos                     (4U)
14126  #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
14127  #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
14128  #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
14129  #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
14130  #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
14131  #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
14132  #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
14133  #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
14134  #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
14135  
14136  #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
14137  #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
14138  #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
14139  #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
14140  #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
14141  
14142  #define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
14143  #define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
14144  #define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
14145  
14146  #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
14147  #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
14148  #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
14149  
14150  #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
14151  #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
14152  #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
14153  #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
14154  #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
14155  
14156  /********************  Bit definition for USB_OTG_PCGCR register  ********************/
14157  #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
14158  #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
14159  #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
14160  #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
14161  #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
14162  #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
14163  #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
14164  #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
14165  #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
14166  
14167  /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
14168  #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
14169  #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
14170  #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
14171  #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
14172  #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
14173  #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
14174  #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
14175  #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
14176  #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
14177  #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
14178  #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
14179  #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
14180  #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
14181  #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
14182  #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
14183  #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
14184  #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
14185  #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
14186  #define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)
14187  #define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
14188  #define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */
14189  
14190  /********************  Bit definition for USB_OTG_DCTL register  ********************/
14191  #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
14192  #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
14193  #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
14194  #define USB_OTG_DCTL_SDIS_Pos                    (1U)
14195  #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
14196  #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
14197  #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
14198  #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
14199  #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
14200  #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
14201  #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
14202  #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
14203  
14204  #define USB_OTG_DCTL_TCTL_Pos                    (4U)
14205  #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
14206  #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
14207  #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
14208  #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
14209  #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
14210  #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
14211  #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
14212  #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
14213  #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
14214  #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
14215  #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
14216  #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
14217  #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
14218  #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
14219  #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
14220  #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
14221  #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
14222  #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
14223  #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
14224  #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
14225  
14226  /********************  Bit definition for USB_OTG_HFIR register  ********************/
14227  #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
14228  #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
14229  #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
14230  
14231  /********************  Bit definition for USB_OTG_HFNUM register  ********************/
14232  #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
14233  #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
14234  #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
14235  #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
14236  #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
14237  #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
14238  
14239  /********************  Bit definition for USB_OTG_DSTS register  ********************/
14240  #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
14241  #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
14242  #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
14243  
14244  #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
14245  #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
14246  #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
14247  #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
14248  #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
14249  #define USB_OTG_DSTS_EERR_Pos                    (3U)
14250  #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
14251  #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
14252  #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
14253  #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
14254  #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
14255  
14256  /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
14257  #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
14258  #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
14259  #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
14260  #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
14261  #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
14262  #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
14263  #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
14264  #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
14265  #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
14266  #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
14267  #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
14268  #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
14269  #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
14270  #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
14271  #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
14272  #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
14273  #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
14274  #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
14275  #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
14276  #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
14277  
14278  /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
14279  
14280  #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
14281  #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
14282  #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
14283  #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
14284  #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
14285  #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
14286  #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
14287  #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
14288  #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
14289  #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
14290  #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
14291  #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
14292  #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
14293  #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
14294  #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
14295  #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
14296  #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
14297  #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
14298  #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
14299  #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
14300  #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
14301  #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
14302  #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
14303  #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
14304  #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
14305  #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
14306  #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
14307  #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
14308  #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
14309  #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
14310  #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
14311  #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
14312  #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
14313  #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
14314  #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
14315  #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
14316  #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
14317  #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
14318  #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
14319  #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
14320  #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
14321  #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
14322  #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
14323  #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
14324  #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
14325  #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
14326  #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
14327  #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
14328  #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
14329  #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
14330  #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
14331  #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
14332  #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
14333  #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
14334  #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
14335  #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
14336  #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
14337  #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
14338  #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
14339  #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
14340  #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
14341  
14342  /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
14343  #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
14344  #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
14345  #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
14346  #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
14347  #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
14348  #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
14349  #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
14350  #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
14351  #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
14352  #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
14353  #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
14354  #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
14355  #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
14356  #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
14357  #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
14358  
14359  
14360  #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
14361  #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
14362  #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
14363  #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
14364  #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
14365  #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
14366  #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
14367  #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
14368  #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
14369  #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
14370  #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
14371  #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
14372  #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
14373  #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
14374  
14375  /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
14376  #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
14377  #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
14378  #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
14379  #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
14380  #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
14381  #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
14382  #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
14383  #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
14384  #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
14385  #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
14386  #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
14387  #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
14388  #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
14389  #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
14390  #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
14391  #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
14392  #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
14393  #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
14394  #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
14395  #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
14396  #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
14397  #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
14398  #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
14399  #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
14400  
14401  /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
14402  #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
14403  #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
14404  #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
14405  #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
14406  #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
14407  #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
14408  #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
14409  #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
14410  #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
14411  #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
14412  #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
14413  #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
14414  #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
14415  #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
14416  
14417  #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
14418  #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
14419  #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
14420  #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
14421  #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
14422  #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
14423  #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
14424  #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
14425  #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
14426  #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
14427  #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
14428  
14429  /********************  Bit definition for USB_OTG_HAINT register  ********************/
14430  #define USB_OTG_HAINT_HAINT_Pos                  (0U)
14431  #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
14432  #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
14433  
14434  /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
14435  #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
14436  #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
14437  #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */
14438  #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
14439  #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
14440  #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
14441  #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
14442  #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
14443  #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
14444  #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
14445  #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
14446  #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
14447  #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
14448  #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
14449  #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
14450  #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
14451  #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
14452  #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
14453  #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
14454  #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
14455  #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
14456  #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
14457  #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
14458  #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
14459  #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
14460  #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
14461  #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
14462  #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
14463  #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
14464  #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
14465  #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
14466  #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
14467  #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
14468  #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
14469  #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
14470  #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
14471  /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
14472  #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
14473  #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
14474  #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
14475  #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
14476  #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
14477  #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
14478  #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
14479  #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
14480  #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
14481  #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
14482  #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
14483  #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
14484  #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
14485  #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
14486  #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
14487  #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
14488  #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
14489  #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
14490  #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
14491  #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
14492  #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
14493  #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
14494  #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
14495  #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
14496  #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
14497  #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
14498  #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
14499  #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
14500  #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
14501  #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
14502  #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
14503  #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
14504  #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
14505  #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
14506  #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
14507  #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
14508  #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
14509  #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
14510  #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
14511  #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
14512  #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
14513  #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
14514  #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
14515  #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
14516  #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
14517  #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
14518  #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
14519  #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
14520  #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
14521  #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
14522  #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
14523  #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
14524  #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
14525  #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
14526  #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
14527  #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
14528  #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
14529  #define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
14530  #define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
14531  #define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
14532  #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
14533  #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
14534  #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
14535  #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
14536  #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
14537  #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
14538  #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
14539  #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
14540  #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
14541  #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
14542  #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
14543  #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
14544  #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
14545  #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
14546  #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
14547  #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
14548  #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
14549  #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
14550  #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
14551  #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
14552  #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
14553  #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
14554  #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
14555  #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
14556  
14557  /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
14558  #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
14559  #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
14560  #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
14561  #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
14562  #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
14563  #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
14564  #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
14565  #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
14566  #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
14567  #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
14568  #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
14569  #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
14570  #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
14571  #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
14572  #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
14573  #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
14574  #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
14575  #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
14576  #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
14577  #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
14578  #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
14579  #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
14580  #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
14581  #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
14582  #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
14583  #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
14584  #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
14585  #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
14586  #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
14587  #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
14588  #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
14589  #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
14590  #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
14591  #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
14592  #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
14593  #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
14594  #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
14595  #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
14596  #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
14597  #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
14598  #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
14599  #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
14600  #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
14601  #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
14602  #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
14603  #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
14604  #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
14605  #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
14606  #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
14607  #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
14608  #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
14609  #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
14610  #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
14611  #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
14612  #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
14613  #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
14614  #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
14615  #define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
14616  #define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
14617  #define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
14618  #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
14619  #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
14620  #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
14621  #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
14622  #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
14623  #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
14624  #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
14625  #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
14626  #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
14627  #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
14628  #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
14629  #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
14630  #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
14631  #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
14632  #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
14633  #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
14634  #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
14635  #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
14636  #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
14637  #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
14638  #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
14639  #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
14640  #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
14641  #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
14642  
14643  /********************  Bit definition for USB_OTG_DAINT register  ********************/
14644  #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
14645  #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
14646  #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
14647  #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
14648  #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
14649  #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
14650  
14651  /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
14652  #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
14653  #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
14654  #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
14655  
14656  /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
14657  #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
14658  #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
14659  #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
14660  #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
14661  #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
14662  #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
14663  #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
14664  #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
14665  #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
14666  #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
14667  #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
14668  #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
14669  
14670  /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
14671  #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
14672  #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
14673  #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
14674  #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
14675  #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
14676  #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
14677  
14678  /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
14679  #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
14680  #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
14681  #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
14682  
14683  /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
14684  #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
14685  #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
14686  #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
14687  
14688  /********************  Bit definition for OTG register  ********************/
14689  #define USB_OTG_NPTXFSA_Pos                      (0U)
14690  #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
14691  #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
14692  #define USB_OTG_NPTXFD_Pos                       (16U)
14693  #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
14694  #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
14695  #define USB_OTG_TX0FSA_Pos                       (0U)
14696  #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
14697  #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
14698  #define USB_OTG_TX0FD_Pos                        (16U)
14699  #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
14700  #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
14701  
14702  /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
14703  #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
14704  #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
14705  #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
14706  
14707  /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
14708  #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
14709  #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
14710  #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
14711  
14712  #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
14713  #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
14714  #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
14715  #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
14716  #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
14717  #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
14718  #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
14719  #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
14720  #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
14721  #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
14722  #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
14723  
14724  #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
14725  #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
14726  #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
14727  #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
14728  #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
14729  #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
14730  #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
14731  #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
14732  #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
14733  #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
14734  
14735  /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
14736  #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
14737  #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
14738  #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
14739  #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
14740  #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
14741  #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
14742  
14743  #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
14744  #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
14745  #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
14746  #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
14747  #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
14748  #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
14749  #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
14750  #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
14751  #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
14752  #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
14753  #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
14754  #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
14755  #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
14756  #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
14757  #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
14758  
14759  #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
14760  #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
14761  #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
14762  #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
14763  #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
14764  #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
14765  #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
14766  #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
14767  #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
14768  #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
14769  #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
14770  #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
14771  #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
14772  #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
14773  #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
14774  
14775  /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
14776  #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
14777  #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
14778  #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
14779  
14780  /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
14781  #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
14782  #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
14783  #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
14784  #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
14785  #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
14786  #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
14787  
14788  /********************  Bit definition for USB_OTG_GCCFG register  ********************/
14789  #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
14790  #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
14791  #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
14792  #define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
14793  #define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
14794  #define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */
14795  
14796  /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
14797  #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
14798  #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
14799  #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
14800  #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
14801  #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
14802  #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
14803  
14804  /********************  Bit definition for USB_OTG_CID register  ********************/
14805  #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
14806  #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
14807  #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
14808  
14809  /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
14810  #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
14811  #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
14812  #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
14813  #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
14814  #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
14815  #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
14816  #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
14817  #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
14818  #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
14819  #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
14820  #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
14821  #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
14822  #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
14823  #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
14824  #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
14825  #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
14826  #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
14827  #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
14828  #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
14829  #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
14830  #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
14831  #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
14832  #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
14833  #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
14834  #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
14835  #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
14836  #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
14837  #define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
14838  #define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
14839  #define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
14840  #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
14841  #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
14842  #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
14843  #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
14844  #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
14845  #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
14846  #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
14847  #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
14848  #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
14849  #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
14850  #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
14851  #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
14852  #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
14853  #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
14854  #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
14855  
14856  /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
14857  #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
14858  #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14859  #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
14860  #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
14861  #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14862  #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
14863  #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
14864  #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14865  #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
14866  #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
14867  #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14868  #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
14869  #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
14870  #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14871  #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
14872  #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
14873  #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14874  #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
14875  #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
14876  #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14877  #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
14878  #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
14879  #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14880  #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
14881  #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
14882  #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14883  #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
14884  
14885  /********************  Bit definition for USB_OTG_HPRT register  ********************/
14886  #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
14887  #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
14888  #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
14889  #define USB_OTG_HPRT_PCDET_Pos                   (1U)
14890  #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
14891  #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
14892  #define USB_OTG_HPRT_PENA_Pos                    (2U)
14893  #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
14894  #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
14895  #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
14896  #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
14897  #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
14898  #define USB_OTG_HPRT_POCA_Pos                    (4U)
14899  #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
14900  #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
14901  #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
14902  #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
14903  #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
14904  #define USB_OTG_HPRT_PRES_Pos                    (6U)
14905  #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
14906  #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
14907  #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
14908  #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
14909  #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
14910  #define USB_OTG_HPRT_PRST_Pos                    (8U)
14911  #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
14912  #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
14913  
14914  #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
14915  #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
14916  #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
14917  #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
14918  #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
14919  #define USB_OTG_HPRT_PPWR_Pos                    (12U)
14920  #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
14921  #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
14922  
14923  #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
14924  #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
14925  #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
14926  #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
14927  #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
14928  #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
14929  #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
14930  
14931  #define USB_OTG_HPRT_PSPD_Pos                    (17U)
14932  #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
14933  #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
14934  #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
14935  #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
14936  
14937  /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
14938  #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
14939  #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14940  #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
14941  #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
14942  #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14943  #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
14944  #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
14945  #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14946  #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
14947  #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
14948  #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14949  #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
14950  #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
14951  #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14952  #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
14953  #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
14954  #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14955  #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
14956  #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
14957  #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14958  #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
14959  #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
14960  #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14961  #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
14962  #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
14963  #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
14964  #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
14965  #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
14966  #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14967  #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
14968  #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
14969  #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
14970  #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
14971  
14972  /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
14973  #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
14974  #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
14975  #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
14976  #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
14977  #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
14978  #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
14979  
14980  /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
14981  #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
14982  #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14983  #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
14984  #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
14985  #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14986  #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
14987  #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
14988  #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
14989  #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
14990  #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
14991  #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14992  #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
14993  
14994  #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
14995  #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14996  #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
14997  #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14998  #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14999  #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
15000  #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
15001  #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
15002  
15003  #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
15004  #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
15005  #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
15006  #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
15007  #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
15008  #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
15009  #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
15010  #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
15011  #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
15012  #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
15013  #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
15014  #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
15015  #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
15016  #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
15017  #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
15018  #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
15019  #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
15020  #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
15021  #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
15022  #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
15023  #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
15024  #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
15025  #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
15026  #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
15027  #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
15028  
15029  /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
15030  #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
15031  #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
15032  #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
15033  
15034  #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
15035  #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
15036  #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
15037  #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
15038  #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
15039  #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
15040  #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
15041  #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
15042  #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
15043  #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
15044  #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
15045  #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
15046  #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
15047  
15048  #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
15049  #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
15050  #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
15051  #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
15052  #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
15053  
15054  #define USB_OTG_HCCHAR_MC_Pos                    (20U)
15055  #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
15056  #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
15057  #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
15058  #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
15059  
15060  #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
15061  #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
15062  #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
15063  #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
15064  #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
15065  #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
15066  #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
15067  #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
15068  #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
15069  #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
15070  #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
15071  #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
15072  #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
15073  #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
15074  #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
15075  #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
15076  #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
15077  #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
15078  #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
15079  
15080  /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
15081  
15082  #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
15083  #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
15084  #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
15085  #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
15086  #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
15087  #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
15088  #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
15089  #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
15090  #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
15091  #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
15092  
15093  #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
15094  #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
15095  #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
15096  #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
15097  #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
15098  #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
15099  #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
15100  #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
15101  #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
15102  #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
15103  
15104  #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
15105  #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
15106  #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
15107  #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
15108  #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
15109  #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
15110  #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
15111  #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
15112  #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
15113  #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
15114  #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
15115  
15116  /********************  Bit definition for USB_OTG_HCINT register  ********************/
15117  #define USB_OTG_HCINT_XFRC_Pos                   (0U)
15118  #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
15119  #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
15120  #define USB_OTG_HCINT_CHH_Pos                    (1U)
15121  #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
15122  #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
15123  #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
15124  #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
15125  #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
15126  #define USB_OTG_HCINT_STALL_Pos                  (3U)
15127  #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
15128  #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
15129  #define USB_OTG_HCINT_NAK_Pos                    (4U)
15130  #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
15131  #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
15132  #define USB_OTG_HCINT_ACK_Pos                    (5U)
15133  #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
15134  #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
15135  #define USB_OTG_HCINT_NYET_Pos                   (6U)
15136  #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
15137  #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
15138  #define USB_OTG_HCINT_TXERR_Pos                  (7U)
15139  #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
15140  #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
15141  #define USB_OTG_HCINT_BBERR_Pos                  (8U)
15142  #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
15143  #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
15144  #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
15145  #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
15146  #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
15147  #define USB_OTG_HCINT_DTERR_Pos                  (10U)
15148  #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
15149  #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
15150  
15151  /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
15152  #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
15153  #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
15154  #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
15155  #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
15156  #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
15157  #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
15158  #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
15159  #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
15160  #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
15161  #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
15162  #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
15163  #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
15164  #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
15165  #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
15166  #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
15167  #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
15168  #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
15169  #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
15170  #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
15171  #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
15172  #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
15173  #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
15174  #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
15175  #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
15176  #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
15177  #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
15178  #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
15179  #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
15180  #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
15181  #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
15182  #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
15183  #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
15184  #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
15185  #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
15186  #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
15187  #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
15188  #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
15189  #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
15190  #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
15191  
15192  /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
15193  #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
15194  #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
15195  #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
15196  #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
15197  #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
15198  #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
15199  #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
15200  #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
15201  #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
15202  #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
15203  #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
15204  #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
15205  #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
15206  #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
15207  #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
15208  #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
15209  #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
15210  #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
15211  #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
15212  #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
15213  #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
15214  #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
15215  #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
15216  #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
15217  #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
15218  #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
15219  #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
15220  #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
15221  #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
15222  #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
15223  #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
15224  #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
15225  #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
15226  
15227  /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
15228  
15229  #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
15230  #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
15231  #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
15232  #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
15233  #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
15234  #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
15235  #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
15236  #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
15237  #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
15238  /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
15239  #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
15240  #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
15241  #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
15242  #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
15243  #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
15244  #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
15245  #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
15246  #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
15247  #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
15248  #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
15249  #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
15250  #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
15251  #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
15252  #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
15253  
15254  /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
15255  #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
15256  #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
15257  #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
15258  
15259  /********************  Bit definition for USB_OTG_HCDMA register  ********************/
15260  #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
15261  #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
15262  #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
15263  
15264  /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
15265  #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
15266  #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
15267  #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
15268  
15269  /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
15270  #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
15271  #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
15272  #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
15273  #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
15274  #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
15275  #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
15276  
15277  /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
15278  
15279  #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
15280  #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
15281  #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
15282  #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
15283  #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
15284  #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
15285  #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
15286  #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
15287  #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
15288  #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
15289  #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
15290  #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
15291  #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
15292  #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
15293  #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
15294  #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
15295  #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
15296  #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
15297  #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
15298  #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
15299  #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
15300  #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
15301  #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
15302  #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
15303  #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
15304  #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
15305  #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
15306  #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
15307  #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
15308  #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
15309  #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
15310  #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
15311  #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
15312  #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
15313  #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
15314  #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
15315  #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
15316  #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
15317  
15318  /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
15319  #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
15320  #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
15321  #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
15322  #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
15323  #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
15324  #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
15325  #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
15326  #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
15327  #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
15328  #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
15329  #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
15330  #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
15331  #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
15332  #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
15333  #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
15334  #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
15335  #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
15336  #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
15337  #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
15338  #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
15339  #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
15340  #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
15341  #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
15342  #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
15343  #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
15344  #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
15345  #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
15346  #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
15347  #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
15348  #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
15349  #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
15350  #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
15351  #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
15352  /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
15353  
15354  #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
15355  #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
15356  #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
15357  #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
15358  #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
15359  #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
15360  
15361  #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
15362  #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
15363  #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
15364  #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
15365  #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
15366  
15367  /********************  Bit definition for PCGCCTL register  ********************/
15368  #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
15369  #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
15370  #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
15371  #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
15372  #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
15373  #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
15374  #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
15375  #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
15376  #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
15377  
15378  /* Legacy define */
15379  /********************  Bit definition for OTG register  ********************/
15380  #define USB_OTG_CHNUM_Pos                        (0U)
15381  #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
15382  #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
15383  #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
15384  #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
15385  #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
15386  #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
15387  #define USB_OTG_BCNT_Pos                         (4U)
15388  #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
15389  #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
15390  
15391  #define USB_OTG_DPID_Pos                         (15U)
15392  #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
15393  #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
15394  #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
15395  #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
15396  
15397  #define USB_OTG_PKTSTS_Pos                       (17U)
15398  #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
15399  #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
15400  #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
15401  #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
15402  #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
15403  #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
15404  
15405  #define USB_OTG_EPNUM_Pos                        (0U)
15406  #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
15407  #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
15408  #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
15409  #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
15410  #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
15411  #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
15412  
15413  #define USB_OTG_FRMNUM_Pos                       (21U)
15414  #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
15415  #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
15416  #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
15417  #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
15418  #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
15419  #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
15420  /**
15421    * @}
15422    */
15423  
15424  /**
15425    * @}
15426    */
15427  
15428  /** @addtogroup Exported_macros
15429    * @{
15430    */
15431  
15432  /******************************* ADC Instances ********************************/
15433  #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
15434                                         ((INSTANCE) == ADC2) || \
15435                                         ((INSTANCE) == ADC3))
15436  
15437  #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15438  
15439  #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
15440  
15441  /******************************* CAN Instances ********************************/
15442  #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
15443                                         ((INSTANCE) == CAN2))
15444  /******************************* CRC Instances ********************************/
15445  #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15446  
15447  /******************************* DAC Instances ********************************/
15448  #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
15449  
15450  /******************************* DCMI Instances *******************************/
15451  #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
15452  
15453  /******************************** DMA Instances *******************************/
15454  #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
15455                                                ((INSTANCE) == DMA1_Stream1) || \
15456                                                ((INSTANCE) == DMA1_Stream2) || \
15457                                                ((INSTANCE) == DMA1_Stream3) || \
15458                                                ((INSTANCE) == DMA1_Stream4) || \
15459                                                ((INSTANCE) == DMA1_Stream5) || \
15460                                                ((INSTANCE) == DMA1_Stream6) || \
15461                                                ((INSTANCE) == DMA1_Stream7) || \
15462                                                ((INSTANCE) == DMA2_Stream0) || \
15463                                                ((INSTANCE) == DMA2_Stream1) || \
15464                                                ((INSTANCE) == DMA2_Stream2) || \
15465                                                ((INSTANCE) == DMA2_Stream3) || \
15466                                                ((INSTANCE) == DMA2_Stream4) || \
15467                                                ((INSTANCE) == DMA2_Stream5) || \
15468                                                ((INSTANCE) == DMA2_Stream6) || \
15469                                                ((INSTANCE) == DMA2_Stream7))
15470  
15471  /******************************* GPIO Instances *******************************/
15472  #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15473                                          ((INSTANCE) == GPIOB) || \
15474                                          ((INSTANCE) == GPIOC) || \
15475                                          ((INSTANCE) == GPIOD) || \
15476                                          ((INSTANCE) == GPIOE) || \
15477                                          ((INSTANCE) == GPIOF) || \
15478                                          ((INSTANCE) == GPIOG) || \
15479                                          ((INSTANCE) == GPIOH))
15480  
15481  /******************************** I2C Instances *******************************/
15482  #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15483                                         ((INSTANCE) == I2C2) || \
15484                                         ((INSTANCE) == I2C3))
15485  
15486  /******************************* SMBUS Instances ******************************/
15487  #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
15488  
15489  /******************************** I2S Instances *******************************/
15490  #define IS_I2S_APB1_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
15491                                           ((INSTANCE) == SPI3))
15492  
15493  #define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
15494                                          ((INSTANCE) == SPI2) || \
15495                                          ((INSTANCE) == SPI3))
15496  
15497  
15498  
15499  /****************************** RTC Instances *********************************/
15500  #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
15501  
15502  /******************************* SAI Instances ********************************/
15503  #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A)  || \
15504                                       ((PERIPH) == SAI1_Block_B)  || \
15505                                       ((PERIPH) == SAI2_Block_A)  || \
15506                                       ((PERIPH) == SAI2_Block_B))
15507  /* Legacy define */
15508  
15509  #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
15510  
15511  /******************************** SPI Instances *******************************/
15512  #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15513                                         ((INSTANCE) == SPI2) || \
15514                                         ((INSTANCE) == SPI3) || \
15515                                         ((INSTANCE) == SPI4))
15516  
15517  
15518  /****************** TIM Instances : All supported instances *******************/
15519  #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
15520                                      ((INSTANCE) == TIM2) || \
15521                                      ((INSTANCE) == TIM3) || \
15522                                      ((INSTANCE) == TIM4) || \
15523                                      ((INSTANCE) == TIM5) || \
15524                                      ((INSTANCE) == TIM6) || \
15525                                      ((INSTANCE) == TIM7) || \
15526                                      ((INSTANCE) == TIM8) || \
15527                                      ((INSTANCE) == TIM9) || \
15528                                      ((INSTANCE) == TIM10)|| \
15529                                      ((INSTANCE) == TIM11)|| \
15530                                      ((INSTANCE) == TIM12)|| \
15531                                      ((INSTANCE) == TIM13)|| \
15532                                      ((INSTANCE) == TIM14))
15533  
15534  /************* TIM Instances : at least 1 capture/compare channel *************/
15535  #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
15536                                           ((INSTANCE) == TIM2)  || \
15537                                           ((INSTANCE) == TIM3)  || \
15538                                           ((INSTANCE) == TIM4)  || \
15539                                           ((INSTANCE) == TIM5)  || \
15540                                           ((INSTANCE) == TIM8)  || \
15541                                           ((INSTANCE) == TIM9)  || \
15542                                           ((INSTANCE) == TIM10) || \
15543                                           ((INSTANCE) == TIM11) || \
15544                                           ((INSTANCE) == TIM12) || \
15545                                           ((INSTANCE) == TIM13) || \
15546                                           ((INSTANCE) == TIM14))
15547  
15548  /************ TIM Instances : at least 2 capture/compare channels *************/
15549  #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15550                                         ((INSTANCE) == TIM2) || \
15551                                         ((INSTANCE) == TIM3) || \
15552                                         ((INSTANCE) == TIM4) || \
15553                                         ((INSTANCE) == TIM5) || \
15554                                         ((INSTANCE) == TIM8) || \
15555                                         ((INSTANCE) == TIM9) || \
15556                                         ((INSTANCE) == TIM12))
15557  
15558  /************ TIM Instances : at least 3 capture/compare channels *************/
15559  #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
15560                                           ((INSTANCE) == TIM2) || \
15561                                           ((INSTANCE) == TIM3) || \
15562                                           ((INSTANCE) == TIM4) || \
15563                                           ((INSTANCE) == TIM5) || \
15564                                           ((INSTANCE) == TIM8))
15565  
15566  /************ TIM Instances : at least 4 capture/compare channels *************/
15567  #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15568                                         ((INSTANCE) == TIM2) || \
15569                                         ((INSTANCE) == TIM3) || \
15570                                         ((INSTANCE) == TIM4) || \
15571                                         ((INSTANCE) == TIM5) || \
15572                                         ((INSTANCE) == TIM8))
15573  
15574  /******************** TIM Instances : Advanced-control timers *****************/
15575  #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15576                                             ((INSTANCE) == TIM8))
15577  
15578  /******************* TIM Instances : Timer input XOR function *****************/
15579  #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
15580                                           ((INSTANCE) == TIM2) || \
15581                                           ((INSTANCE) == TIM3) || \
15582                                           ((INSTANCE) == TIM4) || \
15583                                           ((INSTANCE) == TIM5) || \
15584                                           ((INSTANCE) == TIM8))
15585  
15586  /****************** TIM Instances : DMA requests generation (UDE) *************/
15587  #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15588                                         ((INSTANCE) == TIM2) || \
15589                                         ((INSTANCE) == TIM3) || \
15590                                         ((INSTANCE) == TIM4) || \
15591                                         ((INSTANCE) == TIM5) || \
15592                                         ((INSTANCE) == TIM6) || \
15593                                         ((INSTANCE) == TIM7) || \
15594                                         ((INSTANCE) == TIM8))
15595  
15596  /************ TIM Instances : DMA requests generation (CCxDE) *****************/
15597  #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15598                                            ((INSTANCE) == TIM2) || \
15599                                            ((INSTANCE) == TIM3) || \
15600                                            ((INSTANCE) == TIM4) || \
15601                                            ((INSTANCE) == TIM5) || \
15602                                            ((INSTANCE) == TIM8))
15603  
15604  /************ TIM Instances : DMA requests generation (COMDE) *****************/
15605  #define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15606                                            ((INSTANCE) == TIM2) || \
15607                                            ((INSTANCE) == TIM3) || \
15608                                            ((INSTANCE) == TIM4) || \
15609                                            ((INSTANCE) == TIM5) || \
15610                                            ((INSTANCE) == TIM8))
15611  
15612  /******************** TIM Instances : DMA burst feature ***********************/
15613  #define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15614                                               ((INSTANCE) == TIM2) || \
15615                                               ((INSTANCE) == TIM3) || \
15616                                               ((INSTANCE) == TIM4) || \
15617                                               ((INSTANCE) == TIM5) || \
15618                                               ((INSTANCE) == TIM8))
15619  
15620  /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15621  #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
15622                                            ((INSTANCE) == TIM2)  || \
15623                                            ((INSTANCE) == TIM3)  || \
15624                                            ((INSTANCE) == TIM4)  || \
15625                                            ((INSTANCE) == TIM5)  || \
15626                                            ((INSTANCE) == TIM6)  || \
15627                                            ((INSTANCE) == TIM7)  || \
15628                                            ((INSTANCE) == TIM8))
15629  
15630  /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15631  #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15632                                           ((INSTANCE) == TIM2) || \
15633                                           ((INSTANCE) == TIM3) || \
15634                                           ((INSTANCE) == TIM4) || \
15635                                           ((INSTANCE) == TIM5) || \
15636                                           ((INSTANCE) == TIM8) || \
15637                                           ((INSTANCE) == TIM9) || \
15638                                           ((INSTANCE) == TIM12))
15639  /********************** TIM Instances : 32 bit Counter ************************/
15640  #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15641                                                ((INSTANCE) == TIM5))
15642  
15643  /***************** TIM Instances : external trigger input availabe ************/
15644  #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15645                                          ((INSTANCE) == TIM2) || \
15646                                          ((INSTANCE) == TIM3) || \
15647                                          ((INSTANCE) == TIM4) || \
15648                                          ((INSTANCE) == TIM5) || \
15649                                          ((INSTANCE) == TIM8))
15650  
15651  /****************** TIM Instances : remapping capability **********************/
15652  #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
15653                                           ((INSTANCE) == TIM5)  || \
15654                                           ((INSTANCE) == TIM11))
15655  
15656  /******************* TIM Instances : output(s) available **********************/
15657  #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15658      ((((INSTANCE) == TIM1) &&                  \
15659       (((CHANNEL) == TIM_CHANNEL_1) ||          \
15660        ((CHANNEL) == TIM_CHANNEL_2) ||          \
15661        ((CHANNEL) == TIM_CHANNEL_3) ||          \
15662        ((CHANNEL) == TIM_CHANNEL_4)))           \
15663      ||                                         \
15664      (((INSTANCE) == TIM2) &&                   \
15665       (((CHANNEL) == TIM_CHANNEL_1) ||          \
15666        ((CHANNEL) == TIM_CHANNEL_2) ||          \
15667        ((CHANNEL) == TIM_CHANNEL_3) ||          \
15668        ((CHANNEL) == TIM_CHANNEL_4)))           \
15669      ||                                         \
15670      (((INSTANCE) == TIM3) &&                   \
15671       (((CHANNEL) == TIM_CHANNEL_1) ||          \
15672        ((CHANNEL) == TIM_CHANNEL_2) ||          \
15673        ((CHANNEL) == TIM_CHANNEL_3) ||          \
15674        ((CHANNEL) == TIM_CHANNEL_4)))           \
15675      ||                                         \
15676      (((INSTANCE) == TIM4) &&                   \
15677       (((CHANNEL) == TIM_CHANNEL_1) ||          \
15678        ((CHANNEL) == TIM_CHANNEL_2) ||          \
15679        ((CHANNEL) == TIM_CHANNEL_3) ||          \
15680        ((CHANNEL) == TIM_CHANNEL_4)))           \
15681      ||                                         \
15682      (((INSTANCE) == TIM5) &&                   \
15683       (((CHANNEL) == TIM_CHANNEL_1) ||          \
15684        ((CHANNEL) == TIM_CHANNEL_2) ||          \
15685        ((CHANNEL) == TIM_CHANNEL_3) ||          \
15686        ((CHANNEL) == TIM_CHANNEL_4)))           \
15687      ||                                         \
15688      (((INSTANCE) == TIM8) &&                   \
15689       (((CHANNEL) == TIM_CHANNEL_1) ||          \
15690        ((CHANNEL) == TIM_CHANNEL_2) ||          \
15691        ((CHANNEL) == TIM_CHANNEL_3) ||          \
15692        ((CHANNEL) == TIM_CHANNEL_4)))           \
15693      ||                                         \
15694      (((INSTANCE) == TIM9) &&                   \
15695       (((CHANNEL) == TIM_CHANNEL_1) ||          \
15696        ((CHANNEL) == TIM_CHANNEL_2)))           \
15697      ||                                         \
15698      (((INSTANCE) == TIM10) &&                  \
15699       (((CHANNEL) == TIM_CHANNEL_1)))           \
15700      ||                                         \
15701      (((INSTANCE) == TIM11) &&                  \
15702       (((CHANNEL) == TIM_CHANNEL_1)))           \
15703      ||                                         \
15704      (((INSTANCE) == TIM12) &&                  \
15705       (((CHANNEL) == TIM_CHANNEL_1) ||          \
15706        ((CHANNEL) == TIM_CHANNEL_2)))           \
15707      ||                                         \
15708      (((INSTANCE) == TIM13) &&                  \
15709       (((CHANNEL) == TIM_CHANNEL_1)))           \
15710      ||                                         \
15711      (((INSTANCE) == TIM14) &&                  \
15712       (((CHANNEL) == TIM_CHANNEL_1))))
15713  
15714  /************ TIM Instances : complementary output(s) available ***************/
15715  #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15716     ((((INSTANCE) == TIM1) &&                    \
15717       (((CHANNEL) == TIM_CHANNEL_1) ||           \
15718        ((CHANNEL) == TIM_CHANNEL_2) ||           \
15719        ((CHANNEL) == TIM_CHANNEL_3)))            \
15720      ||                                          \
15721      (((INSTANCE) == TIM8) &&                    \
15722       (((CHANNEL) == TIM_CHANNEL_1) ||           \
15723        ((CHANNEL) == TIM_CHANNEL_2) ||           \
15724        ((CHANNEL) == TIM_CHANNEL_3))))
15725  
15726  /****************** TIM Instances : supporting counting mode selection ********/
15727  #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15728                                                          ((INSTANCE) == TIM2) || \
15729                                                          ((INSTANCE) == TIM3) || \
15730                                                          ((INSTANCE) == TIM4) || \
15731                                                          ((INSTANCE) == TIM5) || \
15732                                                          ((INSTANCE) == TIM8))
15733  
15734  /****************** TIM Instances : supporting clock division *****************/
15735  #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
15736                                                    ((INSTANCE) == TIM2) || \
15737                                                    ((INSTANCE) == TIM3) || \
15738                                                    ((INSTANCE) == TIM4) || \
15739                                                    ((INSTANCE) == TIM5) || \
15740                                                    ((INSTANCE) == TIM8) || \
15741                                                    ((INSTANCE) == TIM9) || \
15742                                                    ((INSTANCE) == TIM10)|| \
15743                                                    ((INSTANCE) == TIM11)|| \
15744                                                    ((INSTANCE) == TIM12)|| \
15745                                                    ((INSTANCE) == TIM13)|| \
15746                                                    ((INSTANCE) == TIM14))
15747  
15748  /****************** TIM Instances : supporting commutation event generation ***/
15749  #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15750                                                       ((INSTANCE) == TIM8))
15751  
15752  
15753  /****************** TIM Instances : supporting OCxREF clear *******************/
15754  #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
15755                                                         ((INSTANCE) == TIM2) || \
15756                                                         ((INSTANCE) == TIM3) || \
15757                                                         ((INSTANCE) == TIM4) || \
15758                                                         ((INSTANCE) == TIM5) || \
15759                                                         ((INSTANCE) == TIM8))
15760  
15761  /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15762  #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15763                                                          ((INSTANCE) == TIM2) || \
15764                                                          ((INSTANCE) == TIM3) || \
15765                                                          ((INSTANCE) == TIM4) || \
15766                                                          ((INSTANCE) == TIM5) || \
15767                                                          ((INSTANCE) == TIM8) || \
15768                                                          ((INSTANCE) == TIM9) || \
15769                                                          ((INSTANCE) == TIM12))
15770  
15771  /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15772  #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15773                                                          ((INSTANCE) == TIM2) || \
15774                                                          ((INSTANCE) == TIM3) || \
15775                                                          ((INSTANCE) == TIM4) || \
15776                                                          ((INSTANCE) == TIM5) || \
15777                                                          ((INSTANCE) == TIM8))
15778  
15779  /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
15780  #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
15781                                                          ((INSTANCE) == TIM2) || \
15782                                                          ((INSTANCE) == TIM3) || \
15783                                                          ((INSTANCE) == TIM4) || \
15784                                                          ((INSTANCE) == TIM5) || \
15785                                                          ((INSTANCE) == TIM8) || \
15786                                                          ((INSTANCE) == TIM9) || \
15787                                                          ((INSTANCE) == TIM12))
15788  
15789  /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
15790  #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
15791                                                          ((INSTANCE) == TIM2) || \
15792                                                          ((INSTANCE) == TIM3) || \
15793                                                          ((INSTANCE) == TIM4) || \
15794                                                          ((INSTANCE) == TIM5) || \
15795                                                          ((INSTANCE) == TIM8) || \
15796                                                          ((INSTANCE) == TIM9) || \
15797                                                          ((INSTANCE) == TIM12))
15798  
15799  /****************** TIM Instances : supporting repetition counter *************/
15800  #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15801                                                         ((INSTANCE) == TIM8))
15802  
15803  /****************** TIM Instances : supporting encoder interface **************/
15804  #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15805                                                        ((INSTANCE) == TIM2) || \
15806                                                        ((INSTANCE) == TIM3) || \
15807                                                        ((INSTANCE) == TIM4) || \
15808                                                        ((INSTANCE) == TIM5) || \
15809                                                        ((INSTANCE) == TIM8) || \
15810                                                        ((INSTANCE) == TIM9) || \
15811                                                        ((INSTANCE) == TIM12))
15812  /****************** TIM Instances : supporting Hall sensor interface **********/
15813  #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15814                                                            ((INSTANCE) == TIM2) || \
15815                                                            ((INSTANCE) == TIM3) || \
15816                                                            ((INSTANCE) == TIM4) || \
15817                                                            ((INSTANCE) == TIM5) || \
15818                                                            ((INSTANCE) == TIM8))
15819  /****************** TIM Instances : supporting the break function *************/
15820  #define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15821                                            ((INSTANCE) == TIM8))
15822  
15823  /******************** USART Instances : Synchronous mode **********************/
15824  #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15825                                       ((INSTANCE) == USART2) || \
15826                                       ((INSTANCE) == USART3) || \
15827                                       ((INSTANCE) == USART6))
15828  
15829  /******************** UART Instances : Half-Duplex mode **********************/
15830  #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15831                                                 ((INSTANCE) == USART2) || \
15832                                                 ((INSTANCE) == USART3) || \
15833                                                 ((INSTANCE) == UART4)  || \
15834                                                 ((INSTANCE) == UART5)  || \
15835                                                 ((INSTANCE) == USART6))
15836  
15837  /* Legacy defines */
15838  #define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
15839  
15840  /****************** UART Instances : Hardware Flow control ********************/
15841  #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15842                                             ((INSTANCE) == USART2) || \
15843                                             ((INSTANCE) == USART3) || \
15844                                             ((INSTANCE) == UART4)  || \
15845                                             ((INSTANCE) == UART5)  || \
15846                                             ((INSTANCE) == USART6))
15847  /******************** UART Instances : LIN mode **********************/
15848  #define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
15849  
15850  /********************* UART Instances : Smart card mode ***********************/
15851  #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15852                                           ((INSTANCE) == USART2) || \
15853                                           ((INSTANCE) == USART3) || \
15854                                           ((INSTANCE) == USART6))
15855  
15856  /*********************** UART Instances : IRDA mode ***************************/
15857  #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15858                                      ((INSTANCE) == USART2) || \
15859                                      ((INSTANCE) == USART3) || \
15860                                      ((INSTANCE) == UART4)  || \
15861                                      ((INSTANCE) == UART5)  || \
15862                                      ((INSTANCE) == USART6))
15863  
15864  
15865  /*********************** PCD Instances ****************************************/
15866  #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15867                                         ((INSTANCE) == USB_OTG_HS))
15868  
15869  /*********************** HCD Instances ****************************************/
15870  #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15871                                         ((INSTANCE) == USB_OTG_HS))
15872  
15873  /****************************** SDIO Instances ********************************/
15874  #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15875  
15876  /****************************** IWDG Instances ********************************/
15877  #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
15878  
15879  /****************************** WWDG Instances ********************************/
15880  #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
15881  
15882  
15883  /****************************** QSPI Instances ********************************/
15884  #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
15885  
15886  /******************************* CEC Instances ********************************/
15887  #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
15888  
15889  /***************************** FMPI2C Instances *******************************/
15890  #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
15891  #define IS_FMPSMBUS_ALL_INSTANCE         IS_FMPI2C_ALL_INSTANCE
15892  
15893  /******************************* SPDIFRX Instances ********************************/
15894  #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
15895  /****************************** USB Exported Constants ************************/
15896  #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
15897  #define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
15898  #define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
15899  #define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
15900  #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                16U
15901  #define USB_OTG_HS_MAX_IN_ENDPOINTS                    9U    /* Including EP0 */
15902  #define USB_OTG_HS_MAX_OUT_ENDPOINTS                   9U    /* Including EP0 */
15903  #define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
15904  
15905  /*
15906   * @brief Specific devices reset values definitions
15907   */
15908  #define RCC_PLLCFGR_RST_VALUE              0x24003010U
15909  #define RCC_PLLI2SCFGR_RST_VALUE           0x24003010U
15910  #define RCC_PLLSAICFGR_RST_VALUE           0x04003010U
15911  
15912  #define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/
15913  #define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
15914  #define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
15915  #define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */
15916  #define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
15917  #define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
15918  #define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
15919  #define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
15920  
15921  #define RCC_PLLN_MIN_VALUE                 50U
15922  #define RCC_PLLN_MAX_VALUE                432U
15923  
15924  #define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
15925  #define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
15926  #define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
15927  #define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
15928  #define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
15929  
15930  #define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
15931  #define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
15932  #define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
15933  #define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
15934  #define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */
15935  
15936  #define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
15937  #define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
15938  #define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
15939  
15940  /******************************************************************************/
15941  /*  For a painless codes migration between the STM32F4xx device product       */
15942  /*  lines, the aliases defined below are put in place to overcome the         */
15943  /*  differences in the interrupt handlers and IRQn definitions.               */
15944  /*  No need to update developed interrupt code when moving across             */
15945  /*  product lines within the same STM32F4 Family                              */
15946  /******************************************************************************/
15947  /* Aliases for __IRQn */
15948  #define FSMC_IRQn              FMC_IRQn
15949  
15950  /* Aliases for __IRQHandler */
15951  #define FSMC_IRQHandler        FMC_IRQHandler
15952  #define QuadSPI_IRQHandler     QUADSPI_IRQHandler
15953  
15954  /**
15955    * @}
15956    */
15957  
15958  /**
15959    * @}
15960    */
15961  
15962  /**
15963    * @}
15964    */
15965  
15966  #ifdef __cplusplus
15967  }
15968  #endif /* __cplusplus */
15969  
15970  #endif /* __STM32F446xx_H */
15971  
15972  
15973  
15974  /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
15975