xref: /btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h (revision a8f7f3fcbcd51f8d2e92aca076b6a9f812db358c) 
1  /**
2    ******************************************************************************
3    * @file    stm32f427xx.h
4    * @author  MCD Application Team
5    * @brief   CMSIS STM32F427xx Device Peripheral Access Layer Header File.
6    *
7    *          This file contains:
8    *           - Data structures and the address mapping for all peripherals
9    *           - peripherals registers declarations and bits definition
10    *           - Macros to access peripheral’s registers hardware
11    *
12    ******************************************************************************
13    * @attention
14    *
15    * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16    * All rights reserved.</center></h2>
17    *
18    * This software component is licensed by ST under BSD 3-Clause license,
19    * the "License"; You may not use this file except in compliance with the
20    * License. You may obtain a copy of the License at:
21    *                        opensource.org/licenses/BSD-3-Clause
22    *
23    ******************************************************************************
24    */
25  
26  /** @addtogroup CMSIS_Device
27    * @{
28    */
29  
30  /** @addtogroup stm32f427xx
31    * @{
32    */
33  
34  #ifndef __STM32F427xx_H
35  #define __STM32F427xx_H
36  
37  #ifdef __cplusplus
38   extern "C" {
39  #endif /* __cplusplus */
40  
41  /** @addtogroup Configuration_section_for_CMSIS
42    * @{
43    */
44  
45  /**
46    * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47    */
48  #define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
49  #define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
50  #define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
51  #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
52  #define __FPU_PRESENT             1U       /*!< FPU present                                   */
53  
54  /**
55    * @}
56    */
57  
58  /** @addtogroup Peripheral_interrupt_number_definition
59    * @{
60    */
61  
62  /**
63   * @brief STM32F4XX Interrupt Number Definition, according to the selected device
64   *        in @ref Library_configuration_section
65   */
66  typedef enum
67  {
68  /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69    NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
70    MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
71    BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
72    UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
73    SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
74    DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
75    PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
76    SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
77  /******  STM32 specific Interrupt Numbers **********************************************************************/
78    WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79    PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
80    TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
81    RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
82    FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
83    RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
84    EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
85    EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
86    EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
87    EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
88    EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
89    DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
90    DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
91    DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
92    DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
93    DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
94    DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
95    DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
96    ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
97    CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
98    CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
99    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
100    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
101    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
102    TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
103    TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
104    TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
105    TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
106    TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
107    TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
108    TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
109    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
110    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
111    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
112    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
113    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
114    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
115    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
116    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
117    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
118    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
119    RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
120    OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
121    TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
122    TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
123    TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
124    TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
125    DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
126    FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
127    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
128    TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
129    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
130    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
131    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
132    TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
133    TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
134    DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
135    DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
136    DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
137    DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
138    DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
139    ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
140    ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
141    CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
142    CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
143    CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
144    CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
145    OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
146    DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
147    DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
148    DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
149    USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
150    I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
151    I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
152    OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
153    OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
154    OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
155    OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
156    DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
157    HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
158    FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
159    UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
160    UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
161    SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
162    SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
163    SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
164    SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
165    DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
166  } IRQn_Type;
167  
168  /**
169    * @}
170    */
171  
172  #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
173  #include "system_stm32f4xx.h"
174  #include <stdint.h>
175  
176  /** @addtogroup Peripheral_registers_structures
177    * @{
178    */
179  
180  /**
181    * @brief Analog to Digital Converter
182    */
183  
184  typedef struct
185  {
186    __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
187    __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
188    __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
189    __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
190    __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
191    __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
192    __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
193    __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
194    __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
195    __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
196    __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
197    __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
198    __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
199    __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
200    __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
201    __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
202    __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
203    __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
204    __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
205    __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
206  } ADC_TypeDef;
207  
208  typedef struct
209  {
210    __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
211    __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
212    __IO uint32_t CDR;    /*!< ADC common regular data register for dual
213                               AND triple modes,                            Address offset: ADC1 base address + 0x308 */
214  } ADC_Common_TypeDef;
215  
216  
217  /**
218    * @brief Controller Area Network TxMailBox
219    */
220  
221  typedef struct
222  {
223    __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
224    __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
225    __IO uint32_t TDLR; /*!< CAN mailbox data low register */
226    __IO uint32_t TDHR; /*!< CAN mailbox data high register */
227  } CAN_TxMailBox_TypeDef;
228  
229  /**
230    * @brief Controller Area Network FIFOMailBox
231    */
232  
233  typedef struct
234  {
235    __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
236    __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
237    __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
238    __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
239  } CAN_FIFOMailBox_TypeDef;
240  
241  /**
242    * @brief Controller Area Network FilterRegister
243    */
244  
245  typedef struct
246  {
247    __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
248    __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
249  } CAN_FilterRegister_TypeDef;
250  
251  /**
252    * @brief Controller Area Network
253    */
254  
255  typedef struct
256  {
257    __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
258    __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
259    __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
260    __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
261    __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
262    __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
263    __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
264    __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
265    uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
266    CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
267    CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
268    uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
269    __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
270    __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
271    uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
272    __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
273    uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
274    __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
275    uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
276    __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
277    uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
278    CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
279  } CAN_TypeDef;
280  
281  /**
282    * @brief CRC calculation unit
283    */
284  
285  typedef struct
286  {
287    __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
288    __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
289    uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
290    uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
291    __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
292  } CRC_TypeDef;
293  
294  /**
295    * @brief Digital to Analog Converter
296    */
297  
298  typedef struct
299  {
300    __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
301    __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
302    __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
303    __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
304    __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
305    __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
306    __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
307    __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
308    __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
309    __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
310    __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
311    __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
312    __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
313    __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
314  } DAC_TypeDef;
315  
316  /**
317    * @brief Debug MCU
318    */
319  
320  typedef struct
321  {
322    __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
323    __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
324    __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
325    __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
326  }DBGMCU_TypeDef;
327  
328  /**
329    * @brief DCMI
330    */
331  
332  typedef struct
333  {
334    __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
335    __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
336    __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
337    __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
338    __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
339    __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
340    __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
341    __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
342    __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
343    __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
344    __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
345  } DCMI_TypeDef;
346  
347  /**
348    * @brief DMA Controller
349    */
350  
351  typedef struct
352  {
353    __IO uint32_t CR;     /*!< DMA stream x configuration register      */
354    __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
355    __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
356    __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
357    __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
358    __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
359  } DMA_Stream_TypeDef;
360  
361  typedef struct
362  {
363    __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
364    __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
365    __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
366    __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
367  } DMA_TypeDef;
368  
369  /**
370    * @brief DMA2D Controller
371    */
372  
373  typedef struct
374  {
375    __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
376    __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
377    __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
378    __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
379    __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
380    __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
381    __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
382    __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
383    __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
384    __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
385    __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
386    __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
387    __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
388    __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
389    __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
390    __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
391    __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
392    __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
393    __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
394    __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
395    uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
396    __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
397    __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
398  } DMA2D_TypeDef;
399  
400  /**
401    * @brief Ethernet MAC
402    */
403  
404  typedef struct
405  {
406    __IO uint32_t MACCR;
407    __IO uint32_t MACFFR;
408    __IO uint32_t MACHTHR;
409    __IO uint32_t MACHTLR;
410    __IO uint32_t MACMIIAR;
411    __IO uint32_t MACMIIDR;
412    __IO uint32_t MACFCR;
413    __IO uint32_t MACVLANTR;             /*    8 */
414    uint32_t      RESERVED0[2];
415    __IO uint32_t MACRWUFFR;             /*   11 */
416    __IO uint32_t MACPMTCSR;
417    uint32_t      RESERVED1;
418    __IO uint32_t MACDBGR;
419    __IO uint32_t MACSR;                 /*   15 */
420    __IO uint32_t MACIMR;
421    __IO uint32_t MACA0HR;
422    __IO uint32_t MACA0LR;
423    __IO uint32_t MACA1HR;
424    __IO uint32_t MACA1LR;
425    __IO uint32_t MACA2HR;
426    __IO uint32_t MACA2LR;
427    __IO uint32_t MACA3HR;
428    __IO uint32_t MACA3LR;               /*   24 */
429    uint32_t      RESERVED2[40];
430    __IO uint32_t MMCCR;                 /*   65 */
431    __IO uint32_t MMCRIR;
432    __IO uint32_t MMCTIR;
433    __IO uint32_t MMCRIMR;
434    __IO uint32_t MMCTIMR;               /*   69 */
435    uint32_t      RESERVED3[14];
436    __IO uint32_t MMCTGFSCCR;            /*   84 */
437    __IO uint32_t MMCTGFMSCCR;
438    uint32_t      RESERVED4[5];
439    __IO uint32_t MMCTGFCR;
440    uint32_t      RESERVED5[10];
441    __IO uint32_t MMCRFCECR;
442    __IO uint32_t MMCRFAECR;
443    uint32_t      RESERVED6[10];
444    __IO uint32_t MMCRGUFCR;
445    uint32_t      RESERVED7[334];
446    __IO uint32_t PTPTSCR;
447    __IO uint32_t PTPSSIR;
448    __IO uint32_t PTPTSHR;
449    __IO uint32_t PTPTSLR;
450    __IO uint32_t PTPTSHUR;
451    __IO uint32_t PTPTSLUR;
452    __IO uint32_t PTPTSAR;
453    __IO uint32_t PTPTTHR;
454    __IO uint32_t PTPTTLR;
455    __IO uint32_t RESERVED8;
456    __IO uint32_t PTPTSSR;
457    uint32_t      RESERVED9[565];
458    __IO uint32_t DMABMR;
459    __IO uint32_t DMATPDR;
460    __IO uint32_t DMARPDR;
461    __IO uint32_t DMARDLAR;
462    __IO uint32_t DMATDLAR;
463    __IO uint32_t DMASR;
464    __IO uint32_t DMAOMR;
465    __IO uint32_t DMAIER;
466    __IO uint32_t DMAMFBOCR;
467    __IO uint32_t DMARSWTR;
468    uint32_t      RESERVED10[8];
469    __IO uint32_t DMACHTDR;
470    __IO uint32_t DMACHRDR;
471    __IO uint32_t DMACHTBAR;
472    __IO uint32_t DMACHRBAR;
473  } ETH_TypeDef;
474  
475  /**
476    * @brief External Interrupt/Event Controller
477    */
478  
479  typedef struct
480  {
481    __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
482    __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
483    __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
484    __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
485    __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
486    __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
487  } EXTI_TypeDef;
488  
489  /**
490    * @brief FLASH Registers
491    */
492  
493  typedef struct
494  {
495    __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
496    __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
497    __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
498    __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
499    __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
500    __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
501    __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
502  } FLASH_TypeDef;
503  
504  /**
505    * @brief Flexible Memory Controller
506    */
507  
508  typedef struct
509  {
510    __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
511  } FMC_Bank1_TypeDef;
512  
513  /**
514    * @brief Flexible Memory Controller Bank1E
515    */
516  
517  typedef struct
518  {
519    __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
520  } FMC_Bank1E_TypeDef;
521  /**
522    * @brief Flexible Memory Controller Bank2
523    */
524  
525  typedef struct
526  {
527    __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
528    __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
529    __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
530    __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
531    uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
532    __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
533    uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
534    uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
535    __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
536    __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
537    __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
538    __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
539    uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
540    __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
541  } FMC_Bank2_3_TypeDef;
542  
543  /**
544    * @brief Flexible Memory Controller Bank4
545    */
546  
547  typedef struct
548  {
549    __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
550    __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
551    __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
552    __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
553    __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
554  } FMC_Bank4_TypeDef;
555  
556  /**
557    * @brief Flexible Memory Controller Bank5_6
558    */
559  
560  typedef struct
561  {
562    __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
563    __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
564    __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */
565    __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */
566    __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */
567  } FMC_Bank5_6_TypeDef;
568  
569  /**
570    * @brief General Purpose I/O
571    */
572  
573  typedef struct
574  {
575    __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
576    __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
577    __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
578    __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
579    __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
580    __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
581    __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
582    __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
583    __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
584  } GPIO_TypeDef;
585  
586  /**
587    * @brief System configuration controller
588    */
589  
590  typedef struct
591  {
592    __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
593    __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
594    __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
595    uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
596    __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
597  } SYSCFG_TypeDef;
598  
599  /**
600    * @brief Inter-integrated Circuit Interface
601    */
602  
603  typedef struct
604  {
605    __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
606    __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
607    __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
608    __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
609    __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
610    __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
611    __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
612    __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
613    __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
614    __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
615  } I2C_TypeDef;
616  
617  /**
618    * @brief Independent WATCHDOG
619    */
620  
621  typedef struct
622  {
623    __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
624    __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
625    __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
626    __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
627  } IWDG_TypeDef;
628  
629  
630  /**
631    * @brief Power Control
632    */
633  
634  typedef struct
635  {
636    __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
637    __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
638  } PWR_TypeDef;
639  
640  /**
641    * @brief Reset and Clock Control
642    */
643  
644  typedef struct
645  {
646    __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
647    __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
648    __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
649    __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
650    __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
651    __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
652    __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
653    uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
654    __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
655    __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
656    uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
657    __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
658    __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
659    __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
660    uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
661    __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
662    __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
663    uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
664    __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
665    __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
666    __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
667    uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
668    __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
669    __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
670    uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
671    __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
672    __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
673    uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
674    __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
675    __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
676    __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
677    __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
678  } RCC_TypeDef;
679  
680  /**
681    * @brief Real-Time Clock
682    */
683  
684  typedef struct
685  {
686    __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
687    __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
688    __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
689    __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
690    __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
691    __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
692    __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
693    __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
694    __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
695    __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
696    __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
697    __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
698    __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
699    __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
700    __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
701    __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
702    __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
703    __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
704    __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
705    uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
706    __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
707    __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
708    __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
709    __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
710    __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
711    __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
712    __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
713    __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
714    __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
715    __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
716    __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
717    __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
718    __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
719    __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
720    __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
721    __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
722    __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
723    __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
724    __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
725    __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
726  } RTC_TypeDef;
727  
728  /**
729    * @brief Serial Audio Interface
730    */
731  
732  typedef struct
733  {
734    __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
735  } SAI_TypeDef;
736  
737  typedef struct
738  {
739    __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
740    __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
741    __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
742    __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
743    __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
744    __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
745    __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
746    __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
747  } SAI_Block_TypeDef;
748  
749  /**
750    * @brief SD host Interface
751    */
752  
753  typedef struct
754  {
755    __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
756    __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
757    __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
758    __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
759    __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
760    __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
761    __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
762    __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
763    __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
764    __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
765    __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
766    __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
767    __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
768    __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
769    __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
770    __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
771    uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
772    __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
773    uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
774    __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
775  } SDIO_TypeDef;
776  
777  /**
778    * @brief Serial Peripheral Interface
779    */
780  
781  typedef struct
782  {
783    __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
784    __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
785    __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
786    __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
787    __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
788    __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
789    __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
790    __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
791    __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
792  } SPI_TypeDef;
793  
794  
795  /**
796    * @brief TIM
797    */
798  
799  typedef struct
800  {
801    __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
802    __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
803    __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
804    __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
805    __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
806    __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
807    __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
808    __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
809    __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
810    __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
811    __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
812    __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
813    __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
814    __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
815    __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
816    __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
817    __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
818    __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
819    __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
820    __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
821    __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
822  } TIM_TypeDef;
823  
824  /**
825    * @brief Universal Synchronous Asynchronous Receiver Transmitter
826    */
827  
828  typedef struct
829  {
830    __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
831    __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
832    __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
833    __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
834    __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
835    __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
836    __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
837  } USART_TypeDef;
838  
839  /**
840    * @brief Window WATCHDOG
841    */
842  
843  typedef struct
844  {
845    __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
846    __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
847    __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
848  } WWDG_TypeDef;
849  
850  /**
851    * @brief RNG
852    */
853  
854  typedef struct
855  {
856    __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
857    __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
858    __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
859  } RNG_TypeDef;
860  
861  /**
862    * @brief USB_OTG_Core_Registers
863    */
864  typedef struct
865  {
866    __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
867    __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
868    __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
869    __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
870    __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
871    __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
872    __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
873    __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
874    __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
875    __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
876    __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
877    __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
878    uint32_t Reserved30[2];             /*!< Reserved                                     030h */
879    __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
880    __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
881    uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */
882    __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
883    __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
884  } USB_OTG_GlobalTypeDef;
885  
886  /**
887    * @brief USB_OTG_device_Registers
888    */
889  typedef struct
890  {
891    __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
892    __IO uint32_t DCTL;            /*!< dev Control Register         804h */
893    __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
894    uint32_t Reserved0C;           /*!< Reserved                     80Ch */
895    __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
896    __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
897    __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
898    __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
899    uint32_t  Reserved20;          /*!< Reserved                     820h */
900    uint32_t Reserved9;            /*!< Reserved                     824h */
901    __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
902    __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
903    __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
904    __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
905    __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
906    __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
907    uint32_t Reserved40;           /*!< dedicated EP mask            840h */
908    __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
909    uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
910    __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
911  } USB_OTG_DeviceTypeDef;
912  
913  /**
914    * @brief USB_OTG_IN_Endpoint-Specific_Register
915    */
916  typedef struct
917  {
918    __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
919    uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
920    __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
921    uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
922    __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
923    __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
924    __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
925    uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
926  } USB_OTG_INEndpointTypeDef;
927  
928  /**
929    * @brief USB_OTG_OUT_Endpoint-Specific_Registers
930    */
931  typedef struct
932  {
933    __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
934    uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
935    __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
936    uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
937    __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
938    __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
939    uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
940  } USB_OTG_OUTEndpointTypeDef;
941  
942  /**
943    * @brief USB_OTG_Host_Mode_Register_Structures
944    */
945  typedef struct
946  {
947    __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
948    __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
949    __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
950    uint32_t Reserved40C;           /*!< Reserved                             40Ch */
951    __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
952    __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
953    __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
954  } USB_OTG_HostTypeDef;
955  
956  /**
957    * @brief USB_OTG_Host_Channel_Specific_Registers
958    */
959  typedef struct
960  {
961    __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
962    __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
963    __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
964    __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
965    __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
966    __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
967    uint32_t Reserved[2];           /*!< Reserved                                      */
968  } USB_OTG_HostChannelTypeDef;
969  
970  /**
971    * @}
972    */
973  
974  /** @addtogroup Peripheral_memory_map
975    * @{
976    */
977  #define FLASH_BASE            0x08000000UL /*!< FLASH(up to 2 MB) base address in the alias region                         */
978  #define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
979  #define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                              */
980  #define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
981  #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
982  #define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
983  #define FMC_R_BASE            0xA0000000UL /*!< FMC registers base address                                                 */
984  #define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
985  #define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
986  #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
987  #define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
988  #define FLASH_END             0x081FFFFFUL /*!< FLASH end address                                                          */
989  #define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
990  #define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
991  #define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */
992  
993  /* Legacy defines */
994  #define SRAM_BASE             SRAM1_BASE
995  #define SRAM_BB_BASE          SRAM1_BB_BASE
996  
997  /*!< Peripheral memory map */
998  #define APB1PERIPH_BASE       PERIPH_BASE
999  #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
1000  #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
1001  #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
1002  
1003  /*!< APB1 peripherals */
1004  #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
1005  #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
1006  #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
1007  #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
1008  #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
1009  #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
1010  #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
1011  #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
1012  #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
1013  #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
1014  #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
1015  #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
1016  #define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
1017  #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1018  #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1019  #define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)
1020  #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1021  #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
1022  #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1023  #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1024  #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1025  #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1026  #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
1027  #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
1028  #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
1029  #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1030  #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
1031  #define UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)
1032  #define UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)
1033  
1034  /*!< APB2 peripherals */
1035  #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
1036  #define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
1037  #define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
1038  #define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
1039  #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
1040  #define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
1041  #define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
1042  #define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
1043  /* Legacy define */
1044  #define ADC_BASE               ADC123_COMMON_BASE
1045  #define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
1046  #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1047  #define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)
1048  #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
1049  #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
1050  #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
1051  #define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
1052  #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
1053  #define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)
1054  #define SPI6_BASE             (APB2PERIPH_BASE + 0x5400UL)
1055  #define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)
1056  #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
1057  #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
1058  
1059  /*!< AHB1 peripherals */
1060  #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
1061  #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
1062  #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
1063  #define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
1064  #define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
1065  #define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
1066  #define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
1067  #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
1068  #define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
1069  #define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400UL)
1070  #define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800UL)
1071  #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1072  #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
1073  #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
1074  #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
1075  #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
1076  #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
1077  #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
1078  #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
1079  #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
1080  #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
1081  #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
1082  #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
1083  #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
1084  #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
1085  #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
1086  #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
1087  #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
1088  #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
1089  #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
1090  #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
1091  #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
1092  #define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
1093  #define ETH_MAC_BASE          (ETH_BASE)
1094  #define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
1095  #define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
1096  #define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
1097  #define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000UL)
1098  
1099  /*!< AHB2 peripherals */
1100  #define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
1101  #define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
1102  
1103  /*!< FMC Bankx registers base address */
1104  #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
1105  #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
1106  #define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060UL)
1107  #define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0UL)
1108  #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
1109  
1110  
1111  /*!< Debug MCU registers base address */
1112  #define DBGMCU_BASE           0xE0042000UL
1113  /*!< USB registers base address */
1114  #define USB_OTG_HS_PERIPH_BASE               0x40040000UL
1115  #define USB_OTG_FS_PERIPH_BASE               0x50000000UL
1116  
1117  #define USB_OTG_GLOBAL_BASE                  0x000UL
1118  #define USB_OTG_DEVICE_BASE                  0x800UL
1119  #define USB_OTG_IN_ENDPOINT_BASE             0x900UL
1120  #define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
1121  #define USB_OTG_EP_REG_SIZE                  0x20UL
1122  #define USB_OTG_HOST_BASE                    0x400UL
1123  #define USB_OTG_HOST_PORT_BASE               0x440UL
1124  #define USB_OTG_HOST_CHANNEL_BASE            0x500UL
1125  #define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
1126  #define USB_OTG_PCGCCTL_BASE                 0xE00UL
1127  #define USB_OTG_FIFO_BASE                    0x1000UL
1128  #define USB_OTG_FIFO_SIZE                    0x1000UL
1129  
1130  #define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
1131  #define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
1132  #define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
1133  /**
1134    * @}
1135    */
1136  
1137  /** @addtogroup Peripheral_declaration
1138    * @{
1139    */
1140  #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1141  #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1142  #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1143  #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1144  #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1145  #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1146  #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
1147  #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
1148  #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
1149  #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1150  #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1151  #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1152  #define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
1153  #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1154  #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1155  #define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
1156  #define USART2              ((USART_TypeDef *) USART2_BASE)
1157  #define USART3              ((USART_TypeDef *) USART3_BASE)
1158  #define UART4               ((USART_TypeDef *) UART4_BASE)
1159  #define UART5               ((USART_TypeDef *) UART5_BASE)
1160  #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1161  #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1162  #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1163  #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1164  #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1165  #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1166  #define DAC1                ((DAC_TypeDef *) DAC_BASE)
1167  #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1168  #define UART7               ((USART_TypeDef *) UART7_BASE)
1169  #define UART8               ((USART_TypeDef *) UART8_BASE)
1170  #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1171  #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1172  #define USART1              ((USART_TypeDef *) USART1_BASE)
1173  #define USART6              ((USART_TypeDef *) USART6_BASE)
1174  #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1175  #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1176  #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1177  #define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1178  /* Legacy define */
1179  #define ADC                  ADC123_COMMON
1180  #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
1181  #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1182  #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1183  #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1184  #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1185  #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
1186  #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
1187  #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
1188  #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
1189  #define SPI6                ((SPI_TypeDef *) SPI6_BASE)
1190  #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1191  #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1192  #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1193  #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1194  #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1195  #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1196  #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1197  #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1198  #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1199  #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1200  #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1201  #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
1202  #define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
1203  #define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
1204  #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1205  #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1206  #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1207  #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1208  #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1209  #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1210  #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1211  #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1212  #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1213  #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1214  #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1215  #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1216  #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1217  #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1218  #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1219  #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1220  #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1221  #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1222  #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1223  #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1224  #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1225  #define ETH                 ((ETH_TypeDef *) ETH_BASE)
1226  #define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
1227  #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
1228  #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1229  #define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1230  #define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1231  #define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1232  #define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1233  #define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1234  #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1235  #define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1236  #define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1237  
1238  /**
1239    * @}
1240    */
1241  
1242  /** @addtogroup Exported_constants
1243    * @{
1244    */
1245  
1246    /** @addtogroup Peripheral_Registers_Bits_Definition
1247    * @{
1248    */
1249  
1250  /******************************************************************************/
1251  /*                         Peripheral Registers_Bits_Definition               */
1252  /******************************************************************************/
1253  
1254  /******************************************************************************/
1255  /*                                                                            */
1256  /*                        Analog to Digital Converter                         */
1257  /*                                                                            */
1258  /******************************************************************************/
1259  /*
1260   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1261   */
1262  #define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */
1263  
1264  /********************  Bit definition for ADC_SR register  ********************/
1265  #define ADC_SR_AWD_Pos            (0U)
1266  #define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
1267  #define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
1268  #define ADC_SR_EOC_Pos            (1U)
1269  #define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
1270  #define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
1271  #define ADC_SR_JEOC_Pos           (2U)
1272  #define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
1273  #define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
1274  #define ADC_SR_JSTRT_Pos          (3U)
1275  #define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
1276  #define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
1277  #define ADC_SR_STRT_Pos           (4U)
1278  #define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
1279  #define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
1280  #define ADC_SR_OVR_Pos            (5U)
1281  #define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
1282  #define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
1283  
1284  /*******************  Bit definition for ADC_CR1 register  ********************/
1285  #define ADC_CR1_AWDCH_Pos         (0U)
1286  #define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
1287  #define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1288  #define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
1289  #define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
1290  #define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
1291  #define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
1292  #define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
1293  #define ADC_CR1_EOCIE_Pos         (5U)
1294  #define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
1295  #define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
1296  #define ADC_CR1_AWDIE_Pos         (6U)
1297  #define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
1298  #define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
1299  #define ADC_CR1_JEOCIE_Pos        (7U)
1300  #define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
1301  #define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
1302  #define ADC_CR1_SCAN_Pos          (8U)
1303  #define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
1304  #define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
1305  #define ADC_CR1_AWDSGL_Pos        (9U)
1306  #define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
1307  #define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
1308  #define ADC_CR1_JAUTO_Pos         (10U)
1309  #define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
1310  #define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
1311  #define ADC_CR1_DISCEN_Pos        (11U)
1312  #define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
1313  #define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
1314  #define ADC_CR1_JDISCEN_Pos       (12U)
1315  #define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
1316  #define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
1317  #define ADC_CR1_DISCNUM_Pos       (13U)
1318  #define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
1319  #define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1320  #define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
1321  #define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
1322  #define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
1323  #define ADC_CR1_JAWDEN_Pos        (22U)
1324  #define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
1325  #define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
1326  #define ADC_CR1_AWDEN_Pos         (23U)
1327  #define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
1328  #define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
1329  #define ADC_CR1_RES_Pos           (24U)
1330  #define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
1331  #define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
1332  #define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
1333  #define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
1334  #define ADC_CR1_OVRIE_Pos         (26U)
1335  #define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
1336  #define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
1337  
1338  /*******************  Bit definition for ADC_CR2 register  ********************/
1339  #define ADC_CR2_ADON_Pos          (0U)
1340  #define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
1341  #define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
1342  #define ADC_CR2_CONT_Pos          (1U)
1343  #define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
1344  #define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
1345  #define ADC_CR2_DMA_Pos           (8U)
1346  #define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
1347  #define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
1348  #define ADC_CR2_DDS_Pos           (9U)
1349  #define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
1350  #define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
1351  #define ADC_CR2_EOCS_Pos          (10U)
1352  #define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
1353  #define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
1354  #define ADC_CR2_ALIGN_Pos         (11U)
1355  #define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
1356  #define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
1357  #define ADC_CR2_JEXTSEL_Pos       (16U)
1358  #define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
1359  #define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1360  #define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
1361  #define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
1362  #define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
1363  #define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
1364  #define ADC_CR2_JEXTEN_Pos        (20U)
1365  #define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
1366  #define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1367  #define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
1368  #define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
1369  #define ADC_CR2_JSWSTART_Pos      (22U)
1370  #define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
1371  #define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
1372  #define ADC_CR2_EXTSEL_Pos        (24U)
1373  #define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
1374  #define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1375  #define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
1376  #define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
1377  #define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
1378  #define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
1379  #define ADC_CR2_EXTEN_Pos         (28U)
1380  #define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
1381  #define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1382  #define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
1383  #define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
1384  #define ADC_CR2_SWSTART_Pos       (30U)
1385  #define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
1386  #define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
1387  
1388  /******************  Bit definition for ADC_SMPR1 register  *******************/
1389  #define ADC_SMPR1_SMP10_Pos       (0U)
1390  #define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
1391  #define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1392  #define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
1393  #define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
1394  #define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
1395  #define ADC_SMPR1_SMP11_Pos       (3U)
1396  #define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
1397  #define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1398  #define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
1399  #define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
1400  #define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
1401  #define ADC_SMPR1_SMP12_Pos       (6U)
1402  #define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
1403  #define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1404  #define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
1405  #define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
1406  #define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
1407  #define ADC_SMPR1_SMP13_Pos       (9U)
1408  #define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
1409  #define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1410  #define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
1411  #define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
1412  #define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
1413  #define ADC_SMPR1_SMP14_Pos       (12U)
1414  #define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
1415  #define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1416  #define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
1417  #define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
1418  #define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
1419  #define ADC_SMPR1_SMP15_Pos       (15U)
1420  #define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
1421  #define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1422  #define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
1423  #define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
1424  #define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
1425  #define ADC_SMPR1_SMP16_Pos       (18U)
1426  #define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
1427  #define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1428  #define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
1429  #define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
1430  #define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
1431  #define ADC_SMPR1_SMP17_Pos       (21U)
1432  #define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
1433  #define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1434  #define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
1435  #define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
1436  #define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
1437  #define ADC_SMPR1_SMP18_Pos       (24U)
1438  #define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
1439  #define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1440  #define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
1441  #define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
1442  #define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
1443  
1444  /******************  Bit definition for ADC_SMPR2 register  *******************/
1445  #define ADC_SMPR2_SMP0_Pos        (0U)
1446  #define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
1447  #define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1448  #define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
1449  #define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
1450  #define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
1451  #define ADC_SMPR2_SMP1_Pos        (3U)
1452  #define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
1453  #define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1454  #define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
1455  #define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
1456  #define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
1457  #define ADC_SMPR2_SMP2_Pos        (6U)
1458  #define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
1459  #define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1460  #define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
1461  #define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
1462  #define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
1463  #define ADC_SMPR2_SMP3_Pos        (9U)
1464  #define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
1465  #define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1466  #define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
1467  #define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
1468  #define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
1469  #define ADC_SMPR2_SMP4_Pos        (12U)
1470  #define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
1471  #define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1472  #define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
1473  #define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
1474  #define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
1475  #define ADC_SMPR2_SMP5_Pos        (15U)
1476  #define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
1477  #define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1478  #define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
1479  #define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
1480  #define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
1481  #define ADC_SMPR2_SMP6_Pos        (18U)
1482  #define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
1483  #define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1484  #define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
1485  #define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
1486  #define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
1487  #define ADC_SMPR2_SMP7_Pos        (21U)
1488  #define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
1489  #define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1490  #define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
1491  #define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
1492  #define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
1493  #define ADC_SMPR2_SMP8_Pos        (24U)
1494  #define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
1495  #define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1496  #define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
1497  #define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
1498  #define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
1499  #define ADC_SMPR2_SMP9_Pos        (27U)
1500  #define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
1501  #define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1502  #define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
1503  #define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
1504  #define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
1505  
1506  /******************  Bit definition for ADC_JOFR1 register  *******************/
1507  #define ADC_JOFR1_JOFFSET1_Pos    (0U)
1508  #define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
1509  #define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
1510  
1511  /******************  Bit definition for ADC_JOFR2 register  *******************/
1512  #define ADC_JOFR2_JOFFSET2_Pos    (0U)
1513  #define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
1514  #define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
1515  
1516  /******************  Bit definition for ADC_JOFR3 register  *******************/
1517  #define ADC_JOFR3_JOFFSET3_Pos    (0U)
1518  #define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
1519  #define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
1520  
1521  /******************  Bit definition for ADC_JOFR4 register  *******************/
1522  #define ADC_JOFR4_JOFFSET4_Pos    (0U)
1523  #define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
1524  #define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
1525  
1526  /*******************  Bit definition for ADC_HTR register  ********************/
1527  #define ADC_HTR_HT_Pos            (0U)
1528  #define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
1529  #define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
1530  
1531  /*******************  Bit definition for ADC_LTR register  ********************/
1532  #define ADC_LTR_LT_Pos            (0U)
1533  #define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
1534  #define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
1535  
1536  /*******************  Bit definition for ADC_SQR1 register  *******************/
1537  #define ADC_SQR1_SQ13_Pos         (0U)
1538  #define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
1539  #define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1540  #define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
1541  #define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
1542  #define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
1543  #define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
1544  #define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
1545  #define ADC_SQR1_SQ14_Pos         (5U)
1546  #define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
1547  #define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1548  #define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
1549  #define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
1550  #define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
1551  #define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
1552  #define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
1553  #define ADC_SQR1_SQ15_Pos         (10U)
1554  #define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
1555  #define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1556  #define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
1557  #define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
1558  #define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
1559  #define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
1560  #define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
1561  #define ADC_SQR1_SQ16_Pos         (15U)
1562  #define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
1563  #define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1564  #define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
1565  #define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
1566  #define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
1567  #define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
1568  #define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
1569  #define ADC_SQR1_L_Pos            (20U)
1570  #define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
1571  #define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
1572  #define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
1573  #define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
1574  #define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
1575  #define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
1576  
1577  /*******************  Bit definition for ADC_SQR2 register  *******************/
1578  #define ADC_SQR2_SQ7_Pos          (0U)
1579  #define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
1580  #define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1581  #define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
1582  #define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
1583  #define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
1584  #define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
1585  #define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
1586  #define ADC_SQR2_SQ8_Pos          (5U)
1587  #define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
1588  #define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1589  #define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
1590  #define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
1591  #define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
1592  #define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
1593  #define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
1594  #define ADC_SQR2_SQ9_Pos          (10U)
1595  #define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
1596  #define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1597  #define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
1598  #define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
1599  #define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
1600  #define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
1601  #define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
1602  #define ADC_SQR2_SQ10_Pos         (15U)
1603  #define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
1604  #define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1605  #define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
1606  #define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
1607  #define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
1608  #define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
1609  #define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
1610  #define ADC_SQR2_SQ11_Pos         (20U)
1611  #define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
1612  #define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1613  #define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
1614  #define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
1615  #define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
1616  #define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
1617  #define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
1618  #define ADC_SQR2_SQ12_Pos         (25U)
1619  #define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
1620  #define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1621  #define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
1622  #define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
1623  #define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
1624  #define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
1625  #define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
1626  
1627  /*******************  Bit definition for ADC_SQR3 register  *******************/
1628  #define ADC_SQR3_SQ1_Pos          (0U)
1629  #define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
1630  #define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1631  #define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
1632  #define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
1633  #define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
1634  #define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
1635  #define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
1636  #define ADC_SQR3_SQ2_Pos          (5U)
1637  #define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
1638  #define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1639  #define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
1640  #define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
1641  #define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
1642  #define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
1643  #define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
1644  #define ADC_SQR3_SQ3_Pos          (10U)
1645  #define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
1646  #define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1647  #define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
1648  #define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
1649  #define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
1650  #define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
1651  #define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
1652  #define ADC_SQR3_SQ4_Pos          (15U)
1653  #define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
1654  #define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1655  #define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
1656  #define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
1657  #define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
1658  #define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
1659  #define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
1660  #define ADC_SQR3_SQ5_Pos          (20U)
1661  #define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
1662  #define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1663  #define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
1664  #define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
1665  #define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
1666  #define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
1667  #define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
1668  #define ADC_SQR3_SQ6_Pos          (25U)
1669  #define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
1670  #define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1671  #define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
1672  #define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
1673  #define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
1674  #define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
1675  #define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
1676  
1677  /*******************  Bit definition for ADC_JSQR register  *******************/
1678  #define ADC_JSQR_JSQ1_Pos         (0U)
1679  #define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
1680  #define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1681  #define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
1682  #define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
1683  #define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
1684  #define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
1685  #define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
1686  #define ADC_JSQR_JSQ2_Pos         (5U)
1687  #define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
1688  #define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1689  #define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
1690  #define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
1691  #define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
1692  #define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
1693  #define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
1694  #define ADC_JSQR_JSQ3_Pos         (10U)
1695  #define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
1696  #define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1697  #define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
1698  #define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
1699  #define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
1700  #define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
1701  #define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
1702  #define ADC_JSQR_JSQ4_Pos         (15U)
1703  #define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
1704  #define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1705  #define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
1706  #define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
1707  #define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
1708  #define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
1709  #define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
1710  #define ADC_JSQR_JL_Pos           (20U)
1711  #define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
1712  #define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
1713  #define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
1714  #define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
1715  
1716  /*******************  Bit definition for ADC_JDR1 register  *******************/
1717  #define ADC_JDR1_JDATA_Pos        (0U)
1718  #define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
1719  #define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
1720  
1721  /*******************  Bit definition for ADC_JDR2 register  *******************/
1722  #define ADC_JDR2_JDATA_Pos        (0U)
1723  #define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
1724  #define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
1725  
1726  /*******************  Bit definition for ADC_JDR3 register  *******************/
1727  #define ADC_JDR3_JDATA_Pos        (0U)
1728  #define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
1729  #define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
1730  
1731  /*******************  Bit definition for ADC_JDR4 register  *******************/
1732  #define ADC_JDR4_JDATA_Pos        (0U)
1733  #define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
1734  #define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
1735  
1736  /********************  Bit definition for ADC_DR register  ********************/
1737  #define ADC_DR_DATA_Pos           (0U)
1738  #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1739  #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
1740  #define ADC_DR_ADC2DATA_Pos       (16U)
1741  #define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
1742  #define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
1743  
1744  /*******************  Bit definition for ADC_CSR register  ********************/
1745  #define ADC_CSR_AWD1_Pos          (0U)
1746  #define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
1747  #define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
1748  #define ADC_CSR_EOC1_Pos          (1U)
1749  #define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
1750  #define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
1751  #define ADC_CSR_JEOC1_Pos         (2U)
1752  #define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
1753  #define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
1754  #define ADC_CSR_JSTRT1_Pos        (3U)
1755  #define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
1756  #define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
1757  #define ADC_CSR_STRT1_Pos         (4U)
1758  #define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
1759  #define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
1760  #define ADC_CSR_OVR1_Pos          (5U)
1761  #define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
1762  #define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
1763  #define ADC_CSR_AWD2_Pos          (8U)
1764  #define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
1765  #define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
1766  #define ADC_CSR_EOC2_Pos          (9U)
1767  #define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
1768  #define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
1769  #define ADC_CSR_JEOC2_Pos         (10U)
1770  #define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
1771  #define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
1772  #define ADC_CSR_JSTRT2_Pos        (11U)
1773  #define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
1774  #define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
1775  #define ADC_CSR_STRT2_Pos         (12U)
1776  #define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
1777  #define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
1778  #define ADC_CSR_OVR2_Pos          (13U)
1779  #define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
1780  #define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
1781  #define ADC_CSR_AWD3_Pos          (16U)
1782  #define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
1783  #define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
1784  #define ADC_CSR_EOC3_Pos          (17U)
1785  #define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
1786  #define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
1787  #define ADC_CSR_JEOC3_Pos         (18U)
1788  #define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
1789  #define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
1790  #define ADC_CSR_JSTRT3_Pos        (19U)
1791  #define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
1792  #define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
1793  #define ADC_CSR_STRT3_Pos         (20U)
1794  #define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
1795  #define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
1796  #define ADC_CSR_OVR3_Pos          (21U)
1797  #define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
1798  #define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
1799  
1800  /* Legacy defines */
1801  #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
1802  #define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
1803  #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
1804  
1805  /*******************  Bit definition for ADC_CCR register  ********************/
1806  #define ADC_CCR_MULTI_Pos         (0U)
1807  #define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
1808  #define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1809  #define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
1810  #define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
1811  #define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
1812  #define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
1813  #define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
1814  #define ADC_CCR_DELAY_Pos         (8U)
1815  #define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
1816  #define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1817  #define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
1818  #define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
1819  #define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
1820  #define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
1821  #define ADC_CCR_DDS_Pos           (13U)
1822  #define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
1823  #define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
1824  #define ADC_CCR_DMA_Pos           (14U)
1825  #define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
1826  #define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1827  #define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
1828  #define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
1829  #define ADC_CCR_ADCPRE_Pos        (16U)
1830  #define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
1831  #define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
1832  #define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
1833  #define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
1834  #define ADC_CCR_VBATE_Pos         (22U)
1835  #define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
1836  #define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
1837  #define ADC_CCR_TSVREFE_Pos       (23U)
1838  #define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
1839  #define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
1840  
1841  /*******************  Bit definition for ADC_CDR register  ********************/
1842  #define ADC_CDR_DATA1_Pos         (0U)
1843  #define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
1844  #define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
1845  #define ADC_CDR_DATA2_Pos         (16U)
1846  #define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
1847  #define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
1848  
1849  /* Legacy defines */
1850  #define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
1851  #define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
1852  
1853  /******************************************************************************/
1854  /*                                                                            */
1855  /*                         Controller Area Network                            */
1856  /*                                                                            */
1857  /******************************************************************************/
1858  /*!<CAN control and status registers */
1859  /*******************  Bit definition for CAN_MCR register  ********************/
1860  #define CAN_MCR_INRQ_Pos       (0U)
1861  #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
1862  #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
1863  #define CAN_MCR_SLEEP_Pos      (1U)
1864  #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
1865  #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
1866  #define CAN_MCR_TXFP_Pos       (2U)
1867  #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
1868  #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
1869  #define CAN_MCR_RFLM_Pos       (3U)
1870  #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
1871  #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
1872  #define CAN_MCR_NART_Pos       (4U)
1873  #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
1874  #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
1875  #define CAN_MCR_AWUM_Pos       (5U)
1876  #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
1877  #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
1878  #define CAN_MCR_ABOM_Pos       (6U)
1879  #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
1880  #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
1881  #define CAN_MCR_TTCM_Pos       (7U)
1882  #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
1883  #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
1884  #define CAN_MCR_RESET_Pos      (15U)
1885  #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
1886  #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
1887  #define CAN_MCR_DBF_Pos        (16U)
1888  #define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
1889  #define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
1890  /*******************  Bit definition for CAN_MSR register  ********************/
1891  #define CAN_MSR_INAK_Pos       (0U)
1892  #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
1893  #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
1894  #define CAN_MSR_SLAK_Pos       (1U)
1895  #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
1896  #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
1897  #define CAN_MSR_ERRI_Pos       (2U)
1898  #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
1899  #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
1900  #define CAN_MSR_WKUI_Pos       (3U)
1901  #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
1902  #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
1903  #define CAN_MSR_SLAKI_Pos      (4U)
1904  #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
1905  #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
1906  #define CAN_MSR_TXM_Pos        (8U)
1907  #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
1908  #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
1909  #define CAN_MSR_RXM_Pos        (9U)
1910  #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
1911  #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
1912  #define CAN_MSR_SAMP_Pos       (10U)
1913  #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
1914  #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
1915  #define CAN_MSR_RX_Pos         (11U)
1916  #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
1917  #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
1918  
1919  /*******************  Bit definition for CAN_TSR register  ********************/
1920  #define CAN_TSR_RQCP0_Pos      (0U)
1921  #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
1922  #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
1923  #define CAN_TSR_TXOK0_Pos      (1U)
1924  #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
1925  #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
1926  #define CAN_TSR_ALST0_Pos      (2U)
1927  #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
1928  #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
1929  #define CAN_TSR_TERR0_Pos      (3U)
1930  #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
1931  #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
1932  #define CAN_TSR_ABRQ0_Pos      (7U)
1933  #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
1934  #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
1935  #define CAN_TSR_RQCP1_Pos      (8U)
1936  #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
1937  #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
1938  #define CAN_TSR_TXOK1_Pos      (9U)
1939  #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
1940  #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
1941  #define CAN_TSR_ALST1_Pos      (10U)
1942  #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
1943  #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
1944  #define CAN_TSR_TERR1_Pos      (11U)
1945  #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
1946  #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
1947  #define CAN_TSR_ABRQ1_Pos      (15U)
1948  #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
1949  #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
1950  #define CAN_TSR_RQCP2_Pos      (16U)
1951  #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
1952  #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
1953  #define CAN_TSR_TXOK2_Pos      (17U)
1954  #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
1955  #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
1956  #define CAN_TSR_ALST2_Pos      (18U)
1957  #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
1958  #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
1959  #define CAN_TSR_TERR2_Pos      (19U)
1960  #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
1961  #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
1962  #define CAN_TSR_ABRQ2_Pos      (23U)
1963  #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
1964  #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
1965  #define CAN_TSR_CODE_Pos       (24U)
1966  #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
1967  #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
1968  
1969  #define CAN_TSR_TME_Pos        (26U)
1970  #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
1971  #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
1972  #define CAN_TSR_TME0_Pos       (26U)
1973  #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
1974  #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
1975  #define CAN_TSR_TME1_Pos       (27U)
1976  #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
1977  #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
1978  #define CAN_TSR_TME2_Pos       (28U)
1979  #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
1980  #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
1981  
1982  #define CAN_TSR_LOW_Pos        (29U)
1983  #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
1984  #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
1985  #define CAN_TSR_LOW0_Pos       (29U)
1986  #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
1987  #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
1988  #define CAN_TSR_LOW1_Pos       (30U)
1989  #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
1990  #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
1991  #define CAN_TSR_LOW2_Pos       (31U)
1992  #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
1993  #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
1994  
1995  /*******************  Bit definition for CAN_RF0R register  *******************/
1996  #define CAN_RF0R_FMP0_Pos      (0U)
1997  #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
1998  #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
1999  #define CAN_RF0R_FULL0_Pos     (3U)
2000  #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
2001  #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
2002  #define CAN_RF0R_FOVR0_Pos     (4U)
2003  #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
2004  #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
2005  #define CAN_RF0R_RFOM0_Pos     (5U)
2006  #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
2007  #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
2008  
2009  /*******************  Bit definition for CAN_RF1R register  *******************/
2010  #define CAN_RF1R_FMP1_Pos      (0U)
2011  #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
2012  #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
2013  #define CAN_RF1R_FULL1_Pos     (3U)
2014  #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
2015  #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
2016  #define CAN_RF1R_FOVR1_Pos     (4U)
2017  #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
2018  #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
2019  #define CAN_RF1R_RFOM1_Pos     (5U)
2020  #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
2021  #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
2022  
2023  /********************  Bit definition for CAN_IER register  *******************/
2024  #define CAN_IER_TMEIE_Pos      (0U)
2025  #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
2026  #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
2027  #define CAN_IER_FMPIE0_Pos     (1U)
2028  #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
2029  #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2030  #define CAN_IER_FFIE0_Pos      (2U)
2031  #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
2032  #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
2033  #define CAN_IER_FOVIE0_Pos     (3U)
2034  #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
2035  #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
2036  #define CAN_IER_FMPIE1_Pos     (4U)
2037  #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
2038  #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2039  #define CAN_IER_FFIE1_Pos      (5U)
2040  #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
2041  #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
2042  #define CAN_IER_FOVIE1_Pos     (6U)
2043  #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
2044  #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
2045  #define CAN_IER_EWGIE_Pos      (8U)
2046  #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
2047  #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
2048  #define CAN_IER_EPVIE_Pos      (9U)
2049  #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
2050  #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
2051  #define CAN_IER_BOFIE_Pos      (10U)
2052  #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
2053  #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
2054  #define CAN_IER_LECIE_Pos      (11U)
2055  #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
2056  #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
2057  #define CAN_IER_ERRIE_Pos      (15U)
2058  #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
2059  #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
2060  #define CAN_IER_WKUIE_Pos      (16U)
2061  #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
2062  #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
2063  #define CAN_IER_SLKIE_Pos      (17U)
2064  #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
2065  #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
2066  #define CAN_IER_EWGIE_Pos      (8U)
2067  
2068  /********************  Bit definition for CAN_ESR register  *******************/
2069  #define CAN_ESR_EWGF_Pos       (0U)
2070  #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
2071  #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
2072  #define CAN_ESR_EPVF_Pos       (1U)
2073  #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
2074  #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
2075  #define CAN_ESR_BOFF_Pos       (2U)
2076  #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
2077  #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
2078  
2079  #define CAN_ESR_LEC_Pos        (4U)
2080  #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
2081  #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
2082  #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
2083  #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
2084  #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
2085  
2086  #define CAN_ESR_TEC_Pos        (16U)
2087  #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
2088  #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2089  #define CAN_ESR_REC_Pos        (24U)
2090  #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
2091  #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2092  
2093  /*******************  Bit definition for CAN_BTR register  ********************/
2094  #define CAN_BTR_BRP_Pos        (0U)
2095  #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
2096  #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
2097  #define CAN_BTR_TS1_Pos        (16U)
2098  #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
2099  #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
2100  #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
2101  #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
2102  #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
2103  #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
2104  #define CAN_BTR_TS2_Pos        (20U)
2105  #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
2106  #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
2107  #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
2108  #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
2109  #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
2110  #define CAN_BTR_SJW_Pos        (24U)
2111  #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
2112  #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
2113  #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
2114  #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
2115  #define CAN_BTR_LBKM_Pos       (30U)
2116  #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
2117  #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
2118  #define CAN_BTR_SILM_Pos       (31U)
2119  #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
2120  #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
2121  
2122  
2123  /*!<Mailbox registers */
2124  /******************  Bit definition for CAN_TI0R register  ********************/
2125  #define CAN_TI0R_TXRQ_Pos      (0U)
2126  #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
2127  #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2128  #define CAN_TI0R_RTR_Pos       (1U)
2129  #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
2130  #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
2131  #define CAN_TI0R_IDE_Pos       (2U)
2132  #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
2133  #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
2134  #define CAN_TI0R_EXID_Pos      (3U)
2135  #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2136  #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
2137  #define CAN_TI0R_STID_Pos      (21U)
2138  #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
2139  #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2140  
2141  /******************  Bit definition for CAN_TDT0R register  *******************/
2142  #define CAN_TDT0R_DLC_Pos      (0U)
2143  #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
2144  #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
2145  #define CAN_TDT0R_TGT_Pos      (8U)
2146  #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
2147  #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2148  #define CAN_TDT0R_TIME_Pos     (16U)
2149  #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2150  #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
2151  
2152  /******************  Bit definition for CAN_TDL0R register  *******************/
2153  #define CAN_TDL0R_DATA0_Pos    (0U)
2154  #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2155  #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2156  #define CAN_TDL0R_DATA1_Pos    (8U)
2157  #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2158  #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2159  #define CAN_TDL0R_DATA2_Pos    (16U)
2160  #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2161  #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2162  #define CAN_TDL0R_DATA3_Pos    (24U)
2163  #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2164  #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2165  
2166  /******************  Bit definition for CAN_TDH0R register  *******************/
2167  #define CAN_TDH0R_DATA4_Pos    (0U)
2168  #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2169  #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2170  #define CAN_TDH0R_DATA5_Pos    (8U)
2171  #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2172  #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2173  #define CAN_TDH0R_DATA6_Pos    (16U)
2174  #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2175  #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2176  #define CAN_TDH0R_DATA7_Pos    (24U)
2177  #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2178  #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2179  
2180  /*******************  Bit definition for CAN_TI1R register  *******************/
2181  #define CAN_TI1R_TXRQ_Pos      (0U)
2182  #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
2183  #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2184  #define CAN_TI1R_RTR_Pos       (1U)
2185  #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
2186  #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
2187  #define CAN_TI1R_IDE_Pos       (2U)
2188  #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
2189  #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
2190  #define CAN_TI1R_EXID_Pos      (3U)
2191  #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2192  #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
2193  #define CAN_TI1R_STID_Pos      (21U)
2194  #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
2195  #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2196  
2197  /*******************  Bit definition for CAN_TDT1R register  ******************/
2198  #define CAN_TDT1R_DLC_Pos      (0U)
2199  #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
2200  #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
2201  #define CAN_TDT1R_TGT_Pos      (8U)
2202  #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
2203  #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2204  #define CAN_TDT1R_TIME_Pos     (16U)
2205  #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2206  #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
2207  
2208  /*******************  Bit definition for CAN_TDL1R register  ******************/
2209  #define CAN_TDL1R_DATA0_Pos    (0U)
2210  #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2211  #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2212  #define CAN_TDL1R_DATA1_Pos    (8U)
2213  #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2214  #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2215  #define CAN_TDL1R_DATA2_Pos    (16U)
2216  #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2217  #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2218  #define CAN_TDL1R_DATA3_Pos    (24U)
2219  #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2220  #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2221  
2222  /*******************  Bit definition for CAN_TDH1R register  ******************/
2223  #define CAN_TDH1R_DATA4_Pos    (0U)
2224  #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2225  #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2226  #define CAN_TDH1R_DATA5_Pos    (8U)
2227  #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2228  #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2229  #define CAN_TDH1R_DATA6_Pos    (16U)
2230  #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2231  #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2232  #define CAN_TDH1R_DATA7_Pos    (24U)
2233  #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2234  #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2235  
2236  /*******************  Bit definition for CAN_TI2R register  *******************/
2237  #define CAN_TI2R_TXRQ_Pos      (0U)
2238  #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
2239  #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2240  #define CAN_TI2R_RTR_Pos       (1U)
2241  #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
2242  #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
2243  #define CAN_TI2R_IDE_Pos       (2U)
2244  #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
2245  #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
2246  #define CAN_TI2R_EXID_Pos      (3U)
2247  #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
2248  #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
2249  #define CAN_TI2R_STID_Pos      (21U)
2250  #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
2251  #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2252  
2253  /*******************  Bit definition for CAN_TDT2R register  ******************/
2254  #define CAN_TDT2R_DLC_Pos      (0U)
2255  #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
2256  #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
2257  #define CAN_TDT2R_TGT_Pos      (8U)
2258  #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
2259  #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
2260  #define CAN_TDT2R_TIME_Pos     (16U)
2261  #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
2262  #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
2263  
2264  /*******************  Bit definition for CAN_TDL2R register  ******************/
2265  #define CAN_TDL2R_DATA0_Pos    (0U)
2266  #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
2267  #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2268  #define CAN_TDL2R_DATA1_Pos    (8U)
2269  #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
2270  #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2271  #define CAN_TDL2R_DATA2_Pos    (16U)
2272  #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
2273  #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2274  #define CAN_TDL2R_DATA3_Pos    (24U)
2275  #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
2276  #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2277  
2278  /*******************  Bit definition for CAN_TDH2R register  ******************/
2279  #define CAN_TDH2R_DATA4_Pos    (0U)
2280  #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
2281  #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2282  #define CAN_TDH2R_DATA5_Pos    (8U)
2283  #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
2284  #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2285  #define CAN_TDH2R_DATA6_Pos    (16U)
2286  #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
2287  #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2288  #define CAN_TDH2R_DATA7_Pos    (24U)
2289  #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
2290  #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2291  
2292  /*******************  Bit definition for CAN_RI0R register  *******************/
2293  #define CAN_RI0R_RTR_Pos       (1U)
2294  #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
2295  #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
2296  #define CAN_RI0R_IDE_Pos       (2U)
2297  #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
2298  #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
2299  #define CAN_RI0R_EXID_Pos      (3U)
2300  #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2301  #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
2302  #define CAN_RI0R_STID_Pos      (21U)
2303  #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
2304  #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2305  
2306  /*******************  Bit definition for CAN_RDT0R register  ******************/
2307  #define CAN_RDT0R_DLC_Pos      (0U)
2308  #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
2309  #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
2310  #define CAN_RDT0R_FMI_Pos      (8U)
2311  #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
2312  #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
2313  #define CAN_RDT0R_TIME_Pos     (16U)
2314  #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2315  #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
2316  
2317  /*******************  Bit definition for CAN_RDL0R register  ******************/
2318  #define CAN_RDL0R_DATA0_Pos    (0U)
2319  #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2320  #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
2321  #define CAN_RDL0R_DATA1_Pos    (8U)
2322  #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2323  #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
2324  #define CAN_RDL0R_DATA2_Pos    (16U)
2325  #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2326  #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
2327  #define CAN_RDL0R_DATA3_Pos    (24U)
2328  #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2329  #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
2330  
2331  /*******************  Bit definition for CAN_RDH0R register  ******************/
2332  #define CAN_RDH0R_DATA4_Pos    (0U)
2333  #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2334  #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
2335  #define CAN_RDH0R_DATA5_Pos    (8U)
2336  #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2337  #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
2338  #define CAN_RDH0R_DATA6_Pos    (16U)
2339  #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2340  #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
2341  #define CAN_RDH0R_DATA7_Pos    (24U)
2342  #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2343  #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
2344  
2345  /*******************  Bit definition for CAN_RI1R register  *******************/
2346  #define CAN_RI1R_RTR_Pos       (1U)
2347  #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
2348  #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
2349  #define CAN_RI1R_IDE_Pos       (2U)
2350  #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
2351  #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
2352  #define CAN_RI1R_EXID_Pos      (3U)
2353  #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2354  #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
2355  #define CAN_RI1R_STID_Pos      (21U)
2356  #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
2357  #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2358  
2359  /*******************  Bit definition for CAN_RDT1R register  ******************/
2360  #define CAN_RDT1R_DLC_Pos      (0U)
2361  #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
2362  #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
2363  #define CAN_RDT1R_FMI_Pos      (8U)
2364  #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
2365  #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
2366  #define CAN_RDT1R_TIME_Pos     (16U)
2367  #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2368  #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
2369  
2370  /*******************  Bit definition for CAN_RDL1R register  ******************/
2371  #define CAN_RDL1R_DATA0_Pos    (0U)
2372  #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2373  #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
2374  #define CAN_RDL1R_DATA1_Pos    (8U)
2375  #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2376  #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
2377  #define CAN_RDL1R_DATA2_Pos    (16U)
2378  #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2379  #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
2380  #define CAN_RDL1R_DATA3_Pos    (24U)
2381  #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2382  #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
2383  
2384  /*******************  Bit definition for CAN_RDH1R register  ******************/
2385  #define CAN_RDH1R_DATA4_Pos    (0U)
2386  #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2387  #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
2388  #define CAN_RDH1R_DATA5_Pos    (8U)
2389  #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2390  #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
2391  #define CAN_RDH1R_DATA6_Pos    (16U)
2392  #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2393  #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
2394  #define CAN_RDH1R_DATA7_Pos    (24U)
2395  #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2396  #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
2397  
2398  /*!<CAN filter registers */
2399  /*******************  Bit definition for CAN_FMR register  ********************/
2400  #define CAN_FMR_FINIT_Pos      (0U)
2401  #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
2402  #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
2403  #define CAN_FMR_CAN2SB_Pos     (8U)
2404  #define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
2405  #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
2406  
2407  /*******************  Bit definition for CAN_FM1R register  *******************/
2408  #define CAN_FM1R_FBM_Pos       (0U)
2409  #define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
2410  #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
2411  #define CAN_FM1R_FBM0_Pos      (0U)
2412  #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
2413  #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
2414  #define CAN_FM1R_FBM1_Pos      (1U)
2415  #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
2416  #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
2417  #define CAN_FM1R_FBM2_Pos      (2U)
2418  #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
2419  #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
2420  #define CAN_FM1R_FBM3_Pos      (3U)
2421  #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
2422  #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
2423  #define CAN_FM1R_FBM4_Pos      (4U)
2424  #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
2425  #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
2426  #define CAN_FM1R_FBM5_Pos      (5U)
2427  #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
2428  #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
2429  #define CAN_FM1R_FBM6_Pos      (6U)
2430  #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
2431  #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
2432  #define CAN_FM1R_FBM7_Pos      (7U)
2433  #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
2434  #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
2435  #define CAN_FM1R_FBM8_Pos      (8U)
2436  #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
2437  #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
2438  #define CAN_FM1R_FBM9_Pos      (9U)
2439  #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
2440  #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
2441  #define CAN_FM1R_FBM10_Pos     (10U)
2442  #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
2443  #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
2444  #define CAN_FM1R_FBM11_Pos     (11U)
2445  #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
2446  #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
2447  #define CAN_FM1R_FBM12_Pos     (12U)
2448  #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
2449  #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
2450  #define CAN_FM1R_FBM13_Pos     (13U)
2451  #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
2452  #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
2453  #define CAN_FM1R_FBM14_Pos     (14U)
2454  #define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
2455  #define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
2456  #define CAN_FM1R_FBM15_Pos     (15U)
2457  #define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
2458  #define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
2459  #define CAN_FM1R_FBM16_Pos     (16U)
2460  #define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
2461  #define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
2462  #define CAN_FM1R_FBM17_Pos     (17U)
2463  #define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
2464  #define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
2465  #define CAN_FM1R_FBM18_Pos     (18U)
2466  #define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
2467  #define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
2468  #define CAN_FM1R_FBM19_Pos     (19U)
2469  #define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
2470  #define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
2471  #define CAN_FM1R_FBM20_Pos     (20U)
2472  #define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
2473  #define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
2474  #define CAN_FM1R_FBM21_Pos     (21U)
2475  #define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
2476  #define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
2477  #define CAN_FM1R_FBM22_Pos     (22U)
2478  #define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
2479  #define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
2480  #define CAN_FM1R_FBM23_Pos     (23U)
2481  #define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
2482  #define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
2483  #define CAN_FM1R_FBM24_Pos     (24U)
2484  #define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
2485  #define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
2486  #define CAN_FM1R_FBM25_Pos     (25U)
2487  #define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
2488  #define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
2489  #define CAN_FM1R_FBM26_Pos     (26U)
2490  #define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
2491  #define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
2492  #define CAN_FM1R_FBM27_Pos     (27U)
2493  #define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
2494  #define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
2495  
2496  /*******************  Bit definition for CAN_FS1R register  *******************/
2497  #define CAN_FS1R_FSC_Pos       (0U)
2498  #define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
2499  #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
2500  #define CAN_FS1R_FSC0_Pos      (0U)
2501  #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
2502  #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
2503  #define CAN_FS1R_FSC1_Pos      (1U)
2504  #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
2505  #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
2506  #define CAN_FS1R_FSC2_Pos      (2U)
2507  #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
2508  #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
2509  #define CAN_FS1R_FSC3_Pos      (3U)
2510  #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
2511  #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
2512  #define CAN_FS1R_FSC4_Pos      (4U)
2513  #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
2514  #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
2515  #define CAN_FS1R_FSC5_Pos      (5U)
2516  #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
2517  #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
2518  #define CAN_FS1R_FSC6_Pos      (6U)
2519  #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
2520  #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
2521  #define CAN_FS1R_FSC7_Pos      (7U)
2522  #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
2523  #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
2524  #define CAN_FS1R_FSC8_Pos      (8U)
2525  #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
2526  #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
2527  #define CAN_FS1R_FSC9_Pos      (9U)
2528  #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
2529  #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
2530  #define CAN_FS1R_FSC10_Pos     (10U)
2531  #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
2532  #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
2533  #define CAN_FS1R_FSC11_Pos     (11U)
2534  #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
2535  #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
2536  #define CAN_FS1R_FSC12_Pos     (12U)
2537  #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
2538  #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
2539  #define CAN_FS1R_FSC13_Pos     (13U)
2540  #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
2541  #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
2542  #define CAN_FS1R_FSC14_Pos     (14U)
2543  #define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
2544  #define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
2545  #define CAN_FS1R_FSC15_Pos     (15U)
2546  #define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
2547  #define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
2548  #define CAN_FS1R_FSC16_Pos     (16U)
2549  #define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
2550  #define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
2551  #define CAN_FS1R_FSC17_Pos     (17U)
2552  #define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
2553  #define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
2554  #define CAN_FS1R_FSC18_Pos     (18U)
2555  #define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
2556  #define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
2557  #define CAN_FS1R_FSC19_Pos     (19U)
2558  #define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
2559  #define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
2560  #define CAN_FS1R_FSC20_Pos     (20U)
2561  #define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
2562  #define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
2563  #define CAN_FS1R_FSC21_Pos     (21U)
2564  #define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
2565  #define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
2566  #define CAN_FS1R_FSC22_Pos     (22U)
2567  #define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
2568  #define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
2569  #define CAN_FS1R_FSC23_Pos     (23U)
2570  #define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
2571  #define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
2572  #define CAN_FS1R_FSC24_Pos     (24U)
2573  #define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
2574  #define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
2575  #define CAN_FS1R_FSC25_Pos     (25U)
2576  #define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
2577  #define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
2578  #define CAN_FS1R_FSC26_Pos     (26U)
2579  #define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
2580  #define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
2581  #define CAN_FS1R_FSC27_Pos     (27U)
2582  #define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
2583  #define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
2584  
2585  /******************  Bit definition for CAN_FFA1R register  *******************/
2586  #define CAN_FFA1R_FFA_Pos      (0U)
2587  #define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
2588  #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
2589  #define CAN_FFA1R_FFA0_Pos     (0U)
2590  #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
2591  #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
2592  #define CAN_FFA1R_FFA1_Pos     (1U)
2593  #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
2594  #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
2595  #define CAN_FFA1R_FFA2_Pos     (2U)
2596  #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
2597  #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
2598  #define CAN_FFA1R_FFA3_Pos     (3U)
2599  #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
2600  #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
2601  #define CAN_FFA1R_FFA4_Pos     (4U)
2602  #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
2603  #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
2604  #define CAN_FFA1R_FFA5_Pos     (5U)
2605  #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
2606  #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
2607  #define CAN_FFA1R_FFA6_Pos     (6U)
2608  #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
2609  #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
2610  #define CAN_FFA1R_FFA7_Pos     (7U)
2611  #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
2612  #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
2613  #define CAN_FFA1R_FFA8_Pos     (8U)
2614  #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
2615  #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
2616  #define CAN_FFA1R_FFA9_Pos     (9U)
2617  #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
2618  #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
2619  #define CAN_FFA1R_FFA10_Pos    (10U)
2620  #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
2621  #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
2622  #define CAN_FFA1R_FFA11_Pos    (11U)
2623  #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
2624  #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
2625  #define CAN_FFA1R_FFA12_Pos    (12U)
2626  #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
2627  #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
2628  #define CAN_FFA1R_FFA13_Pos    (13U)
2629  #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
2630  #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
2631  #define CAN_FFA1R_FFA14_Pos    (14U)
2632  #define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
2633  #define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
2634  #define CAN_FFA1R_FFA15_Pos    (15U)
2635  #define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
2636  #define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
2637  #define CAN_FFA1R_FFA16_Pos    (16U)
2638  #define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
2639  #define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
2640  #define CAN_FFA1R_FFA17_Pos    (17U)
2641  #define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
2642  #define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
2643  #define CAN_FFA1R_FFA18_Pos    (18U)
2644  #define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
2645  #define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
2646  #define CAN_FFA1R_FFA19_Pos    (19U)
2647  #define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
2648  #define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
2649  #define CAN_FFA1R_FFA20_Pos    (20U)
2650  #define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
2651  #define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
2652  #define CAN_FFA1R_FFA21_Pos    (21U)
2653  #define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
2654  #define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
2655  #define CAN_FFA1R_FFA22_Pos    (22U)
2656  #define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
2657  #define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
2658  #define CAN_FFA1R_FFA23_Pos    (23U)
2659  #define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
2660  #define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
2661  #define CAN_FFA1R_FFA24_Pos    (24U)
2662  #define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
2663  #define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
2664  #define CAN_FFA1R_FFA25_Pos    (25U)
2665  #define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
2666  #define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
2667  #define CAN_FFA1R_FFA26_Pos    (26U)
2668  #define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
2669  #define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
2670  #define CAN_FFA1R_FFA27_Pos    (27U)
2671  #define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
2672  #define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
2673  
2674  /*******************  Bit definition for CAN_FA1R register  *******************/
2675  #define CAN_FA1R_FACT_Pos      (0U)
2676  #define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
2677  #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
2678  #define CAN_FA1R_FACT0_Pos     (0U)
2679  #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
2680  #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
2681  #define CAN_FA1R_FACT1_Pos     (1U)
2682  #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
2683  #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
2684  #define CAN_FA1R_FACT2_Pos     (2U)
2685  #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
2686  #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
2687  #define CAN_FA1R_FACT3_Pos     (3U)
2688  #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
2689  #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
2690  #define CAN_FA1R_FACT4_Pos     (4U)
2691  #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
2692  #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
2693  #define CAN_FA1R_FACT5_Pos     (5U)
2694  #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
2695  #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
2696  #define CAN_FA1R_FACT6_Pos     (6U)
2697  #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
2698  #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
2699  #define CAN_FA1R_FACT7_Pos     (7U)
2700  #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
2701  #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
2702  #define CAN_FA1R_FACT8_Pos     (8U)
2703  #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
2704  #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
2705  #define CAN_FA1R_FACT9_Pos     (9U)
2706  #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
2707  #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
2708  #define CAN_FA1R_FACT10_Pos    (10U)
2709  #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
2710  #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
2711  #define CAN_FA1R_FACT11_Pos    (11U)
2712  #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
2713  #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
2714  #define CAN_FA1R_FACT12_Pos    (12U)
2715  #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
2716  #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
2717  #define CAN_FA1R_FACT13_Pos    (13U)
2718  #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
2719  #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
2720  #define CAN_FA1R_FACT14_Pos    (14U)
2721  #define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
2722  #define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
2723  #define CAN_FA1R_FACT15_Pos    (15U)
2724  #define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
2725  #define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
2726  #define CAN_FA1R_FACT16_Pos    (16U)
2727  #define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
2728  #define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
2729  #define CAN_FA1R_FACT17_Pos    (17U)
2730  #define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
2731  #define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
2732  #define CAN_FA1R_FACT18_Pos    (18U)
2733  #define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
2734  #define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
2735  #define CAN_FA1R_FACT19_Pos    (19U)
2736  #define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
2737  #define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
2738  #define CAN_FA1R_FACT20_Pos    (20U)
2739  #define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
2740  #define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
2741  #define CAN_FA1R_FACT21_Pos    (21U)
2742  #define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
2743  #define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
2744  #define CAN_FA1R_FACT22_Pos    (22U)
2745  #define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
2746  #define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
2747  #define CAN_FA1R_FACT23_Pos    (23U)
2748  #define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
2749  #define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
2750  #define CAN_FA1R_FACT24_Pos    (24U)
2751  #define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
2752  #define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
2753  #define CAN_FA1R_FACT25_Pos    (25U)
2754  #define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
2755  #define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
2756  #define CAN_FA1R_FACT26_Pos    (26U)
2757  #define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
2758  #define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
2759  #define CAN_FA1R_FACT27_Pos    (27U)
2760  #define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
2761  #define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
2762  
2763  
2764  /*******************  Bit definition for CAN_F0R1 register  *******************/
2765  #define CAN_F0R1_FB0_Pos       (0U)
2766  #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
2767  #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
2768  #define CAN_F0R1_FB1_Pos       (1U)
2769  #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
2770  #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
2771  #define CAN_F0R1_FB2_Pos       (2U)
2772  #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
2773  #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
2774  #define CAN_F0R1_FB3_Pos       (3U)
2775  #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
2776  #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
2777  #define CAN_F0R1_FB4_Pos       (4U)
2778  #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
2779  #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
2780  #define CAN_F0R1_FB5_Pos       (5U)
2781  #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
2782  #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
2783  #define CAN_F0R1_FB6_Pos       (6U)
2784  #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
2785  #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
2786  #define CAN_F0R1_FB7_Pos       (7U)
2787  #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
2788  #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
2789  #define CAN_F0R1_FB8_Pos       (8U)
2790  #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
2791  #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
2792  #define CAN_F0R1_FB9_Pos       (9U)
2793  #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
2794  #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
2795  #define CAN_F0R1_FB10_Pos      (10U)
2796  #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
2797  #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
2798  #define CAN_F0R1_FB11_Pos      (11U)
2799  #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
2800  #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
2801  #define CAN_F0R1_FB12_Pos      (12U)
2802  #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
2803  #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
2804  #define CAN_F0R1_FB13_Pos      (13U)
2805  #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
2806  #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
2807  #define CAN_F0R1_FB14_Pos      (14U)
2808  #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
2809  #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
2810  #define CAN_F0R1_FB15_Pos      (15U)
2811  #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
2812  #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
2813  #define CAN_F0R1_FB16_Pos      (16U)
2814  #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
2815  #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2816  #define CAN_F0R1_FB17_Pos      (17U)
2817  #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
2818  #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2819  #define CAN_F0R1_FB18_Pos      (18U)
2820  #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
2821  #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2822  #define CAN_F0R1_FB19_Pos      (19U)
2823  #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
2824  #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2825  #define CAN_F0R1_FB20_Pos      (20U)
2826  #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
2827  #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2828  #define CAN_F0R1_FB21_Pos      (21U)
2829  #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
2830  #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2831  #define CAN_F0R1_FB22_Pos      (22U)
2832  #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
2833  #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2834  #define CAN_F0R1_FB23_Pos      (23U)
2835  #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
2836  #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2837  #define CAN_F0R1_FB24_Pos      (24U)
2838  #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
2839  #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2840  #define CAN_F0R1_FB25_Pos      (25U)
2841  #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
2842  #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2843  #define CAN_F0R1_FB26_Pos      (26U)
2844  #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
2845  #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2846  #define CAN_F0R1_FB27_Pos      (27U)
2847  #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
2848  #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2849  #define CAN_F0R1_FB28_Pos      (28U)
2850  #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
2851  #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2852  #define CAN_F0R1_FB29_Pos      (29U)
2853  #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
2854  #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
2855  #define CAN_F0R1_FB30_Pos      (30U)
2856  #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
2857  #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
2858  #define CAN_F0R1_FB31_Pos      (31U)
2859  #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
2860  #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
2861  
2862  /*******************  Bit definition for CAN_F1R1 register  *******************/
2863  #define CAN_F1R1_FB0_Pos       (0U)
2864  #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
2865  #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
2866  #define CAN_F1R1_FB1_Pos       (1U)
2867  #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
2868  #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
2869  #define CAN_F1R1_FB2_Pos       (2U)
2870  #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
2871  #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
2872  #define CAN_F1R1_FB3_Pos       (3U)
2873  #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
2874  #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
2875  #define CAN_F1R1_FB4_Pos       (4U)
2876  #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
2877  #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
2878  #define CAN_F1R1_FB5_Pos       (5U)
2879  #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
2880  #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
2881  #define CAN_F1R1_FB6_Pos       (6U)
2882  #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
2883  #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
2884  #define CAN_F1R1_FB7_Pos       (7U)
2885  #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
2886  #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
2887  #define CAN_F1R1_FB8_Pos       (8U)
2888  #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
2889  #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
2890  #define CAN_F1R1_FB9_Pos       (9U)
2891  #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
2892  #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
2893  #define CAN_F1R1_FB10_Pos      (10U)
2894  #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
2895  #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
2896  #define CAN_F1R1_FB11_Pos      (11U)
2897  #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
2898  #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
2899  #define CAN_F1R1_FB12_Pos      (12U)
2900  #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
2901  #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
2902  #define CAN_F1R1_FB13_Pos      (13U)
2903  #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
2904  #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
2905  #define CAN_F1R1_FB14_Pos      (14U)
2906  #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
2907  #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
2908  #define CAN_F1R1_FB15_Pos      (15U)
2909  #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
2910  #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
2911  #define CAN_F1R1_FB16_Pos      (16U)
2912  #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
2913  #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
2914  #define CAN_F1R1_FB17_Pos      (17U)
2915  #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
2916  #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
2917  #define CAN_F1R1_FB18_Pos      (18U)
2918  #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
2919  #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
2920  #define CAN_F1R1_FB19_Pos      (19U)
2921  #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
2922  #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
2923  #define CAN_F1R1_FB20_Pos      (20U)
2924  #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
2925  #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
2926  #define CAN_F1R1_FB21_Pos      (21U)
2927  #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
2928  #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
2929  #define CAN_F1R1_FB22_Pos      (22U)
2930  #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
2931  #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
2932  #define CAN_F1R1_FB23_Pos      (23U)
2933  #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
2934  #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
2935  #define CAN_F1R1_FB24_Pos      (24U)
2936  #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
2937  #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
2938  #define CAN_F1R1_FB25_Pos      (25U)
2939  #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
2940  #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
2941  #define CAN_F1R1_FB26_Pos      (26U)
2942  #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
2943  #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
2944  #define CAN_F1R1_FB27_Pos      (27U)
2945  #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
2946  #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
2947  #define CAN_F1R1_FB28_Pos      (28U)
2948  #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
2949  #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
2950  #define CAN_F1R1_FB29_Pos      (29U)
2951  #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
2952  #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
2953  #define CAN_F1R1_FB30_Pos      (30U)
2954  #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
2955  #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
2956  #define CAN_F1R1_FB31_Pos      (31U)
2957  #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
2958  #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
2959  
2960  /*******************  Bit definition for CAN_F2R1 register  *******************/
2961  #define CAN_F2R1_FB0_Pos       (0U)
2962  #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
2963  #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
2964  #define CAN_F2R1_FB1_Pos       (1U)
2965  #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
2966  #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
2967  #define CAN_F2R1_FB2_Pos       (2U)
2968  #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
2969  #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
2970  #define CAN_F2R1_FB3_Pos       (3U)
2971  #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
2972  #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
2973  #define CAN_F2R1_FB4_Pos       (4U)
2974  #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
2975  #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
2976  #define CAN_F2R1_FB5_Pos       (5U)
2977  #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
2978  #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
2979  #define CAN_F2R1_FB6_Pos       (6U)
2980  #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
2981  #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
2982  #define CAN_F2R1_FB7_Pos       (7U)
2983  #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
2984  #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
2985  #define CAN_F2R1_FB8_Pos       (8U)
2986  #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
2987  #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
2988  #define CAN_F2R1_FB9_Pos       (9U)
2989  #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
2990  #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
2991  #define CAN_F2R1_FB10_Pos      (10U)
2992  #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
2993  #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
2994  #define CAN_F2R1_FB11_Pos      (11U)
2995  #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
2996  #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
2997  #define CAN_F2R1_FB12_Pos      (12U)
2998  #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
2999  #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
3000  #define CAN_F2R1_FB13_Pos      (13U)
3001  #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
3002  #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
3003  #define CAN_F2R1_FB14_Pos      (14U)
3004  #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
3005  #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
3006  #define CAN_F2R1_FB15_Pos      (15U)
3007  #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
3008  #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
3009  #define CAN_F2R1_FB16_Pos      (16U)
3010  #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
3011  #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
3012  #define CAN_F2R1_FB17_Pos      (17U)
3013  #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
3014  #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
3015  #define CAN_F2R1_FB18_Pos      (18U)
3016  #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
3017  #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
3018  #define CAN_F2R1_FB19_Pos      (19U)
3019  #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
3020  #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
3021  #define CAN_F2R1_FB20_Pos      (20U)
3022  #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
3023  #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
3024  #define CAN_F2R1_FB21_Pos      (21U)
3025  #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
3026  #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
3027  #define CAN_F2R1_FB22_Pos      (22U)
3028  #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
3029  #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
3030  #define CAN_F2R1_FB23_Pos      (23U)
3031  #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
3032  #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
3033  #define CAN_F2R1_FB24_Pos      (24U)
3034  #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
3035  #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
3036  #define CAN_F2R1_FB25_Pos      (25U)
3037  #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
3038  #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
3039  #define CAN_F2R1_FB26_Pos      (26U)
3040  #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
3041  #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
3042  #define CAN_F2R1_FB27_Pos      (27U)
3043  #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
3044  #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
3045  #define CAN_F2R1_FB28_Pos      (28U)
3046  #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
3047  #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
3048  #define CAN_F2R1_FB29_Pos      (29U)
3049  #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
3050  #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
3051  #define CAN_F2R1_FB30_Pos      (30U)
3052  #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
3053  #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
3054  #define CAN_F2R1_FB31_Pos      (31U)
3055  #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
3056  #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
3057  
3058  /*******************  Bit definition for CAN_F3R1 register  *******************/
3059  #define CAN_F3R1_FB0_Pos       (0U)
3060  #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
3061  #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
3062  #define CAN_F3R1_FB1_Pos       (1U)
3063  #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
3064  #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
3065  #define CAN_F3R1_FB2_Pos       (2U)
3066  #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
3067  #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
3068  #define CAN_F3R1_FB3_Pos       (3U)
3069  #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
3070  #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
3071  #define CAN_F3R1_FB4_Pos       (4U)
3072  #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
3073  #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
3074  #define CAN_F3R1_FB5_Pos       (5U)
3075  #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
3076  #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3077  #define CAN_F3R1_FB6_Pos       (6U)
3078  #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
3079  #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3080  #define CAN_F3R1_FB7_Pos       (7U)
3081  #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
3082  #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3083  #define CAN_F3R1_FB8_Pos       (8U)
3084  #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
3085  #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3086  #define CAN_F3R1_FB9_Pos       (9U)
3087  #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3088  #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3089  #define CAN_F3R1_FB10_Pos      (10U)
3090  #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3091  #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3092  #define CAN_F3R1_FB11_Pos      (11U)
3093  #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3094  #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3095  #define CAN_F3R1_FB12_Pos      (12U)
3096  #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3097  #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3098  #define CAN_F3R1_FB13_Pos      (13U)
3099  #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3100  #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3101  #define CAN_F3R1_FB14_Pos      (14U)
3102  #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3103  #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3104  #define CAN_F3R1_FB15_Pos      (15U)
3105  #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3106  #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3107  #define CAN_F3R1_FB16_Pos      (16U)
3108  #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3109  #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3110  #define CAN_F3R1_FB17_Pos      (17U)
3111  #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3112  #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3113  #define CAN_F3R1_FB18_Pos      (18U)
3114  #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3115  #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3116  #define CAN_F3R1_FB19_Pos      (19U)
3117  #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3118  #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3119  #define CAN_F3R1_FB20_Pos      (20U)
3120  #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3121  #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3122  #define CAN_F3R1_FB21_Pos      (21U)
3123  #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3124  #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3125  #define CAN_F3R1_FB22_Pos      (22U)
3126  #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3127  #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3128  #define CAN_F3R1_FB23_Pos      (23U)
3129  #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3130  #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3131  #define CAN_F3R1_FB24_Pos      (24U)
3132  #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3133  #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3134  #define CAN_F3R1_FB25_Pos      (25U)
3135  #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3136  #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3137  #define CAN_F3R1_FB26_Pos      (26U)
3138  #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3139  #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3140  #define CAN_F3R1_FB27_Pos      (27U)
3141  #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3142  #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3143  #define CAN_F3R1_FB28_Pos      (28U)
3144  #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3145  #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3146  #define CAN_F3R1_FB29_Pos      (29U)
3147  #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3148  #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3149  #define CAN_F3R1_FB30_Pos      (30U)
3150  #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3151  #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3152  #define CAN_F3R1_FB31_Pos      (31U)
3153  #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3154  #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3155  
3156  /*******************  Bit definition for CAN_F4R1 register  *******************/
3157  #define CAN_F4R1_FB0_Pos       (0U)
3158  #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3159  #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3160  #define CAN_F4R1_FB1_Pos       (1U)
3161  #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3162  #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3163  #define CAN_F4R1_FB2_Pos       (2U)
3164  #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3165  #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3166  #define CAN_F4R1_FB3_Pos       (3U)
3167  #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3168  #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3169  #define CAN_F4R1_FB4_Pos       (4U)
3170  #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3171  #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3172  #define CAN_F4R1_FB5_Pos       (5U)
3173  #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3174  #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3175  #define CAN_F4R1_FB6_Pos       (6U)
3176  #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3177  #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3178  #define CAN_F4R1_FB7_Pos       (7U)
3179  #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3180  #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3181  #define CAN_F4R1_FB8_Pos       (8U)
3182  #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3183  #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3184  #define CAN_F4R1_FB9_Pos       (9U)
3185  #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3186  #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3187  #define CAN_F4R1_FB10_Pos      (10U)
3188  #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3189  #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3190  #define CAN_F4R1_FB11_Pos      (11U)
3191  #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3192  #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3193  #define CAN_F4R1_FB12_Pos      (12U)
3194  #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3195  #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3196  #define CAN_F4R1_FB13_Pos      (13U)
3197  #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3198  #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3199  #define CAN_F4R1_FB14_Pos      (14U)
3200  #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3201  #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3202  #define CAN_F4R1_FB15_Pos      (15U)
3203  #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3204  #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3205  #define CAN_F4R1_FB16_Pos      (16U)
3206  #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3207  #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3208  #define CAN_F4R1_FB17_Pos      (17U)
3209  #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3210  #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3211  #define CAN_F4R1_FB18_Pos      (18U)
3212  #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3213  #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3214  #define CAN_F4R1_FB19_Pos      (19U)
3215  #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3216  #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3217  #define CAN_F4R1_FB20_Pos      (20U)
3218  #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3219  #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3220  #define CAN_F4R1_FB21_Pos      (21U)
3221  #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3222  #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3223  #define CAN_F4R1_FB22_Pos      (22U)
3224  #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3225  #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3226  #define CAN_F4R1_FB23_Pos      (23U)
3227  #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3228  #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3229  #define CAN_F4R1_FB24_Pos      (24U)
3230  #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3231  #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3232  #define CAN_F4R1_FB25_Pos      (25U)
3233  #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3234  #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3235  #define CAN_F4R1_FB26_Pos      (26U)
3236  #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3237  #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3238  #define CAN_F4R1_FB27_Pos      (27U)
3239  #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
3240  #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3241  #define CAN_F4R1_FB28_Pos      (28U)
3242  #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
3243  #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3244  #define CAN_F4R1_FB29_Pos      (29U)
3245  #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
3246  #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3247  #define CAN_F4R1_FB30_Pos      (30U)
3248  #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
3249  #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3250  #define CAN_F4R1_FB31_Pos      (31U)
3251  #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
3252  #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3253  
3254  /*******************  Bit definition for CAN_F5R1 register  *******************/
3255  #define CAN_F5R1_FB0_Pos       (0U)
3256  #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
3257  #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3258  #define CAN_F5R1_FB1_Pos       (1U)
3259  #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
3260  #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3261  #define CAN_F5R1_FB2_Pos       (2U)
3262  #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
3263  #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3264  #define CAN_F5R1_FB3_Pos       (3U)
3265  #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
3266  #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3267  #define CAN_F5R1_FB4_Pos       (4U)
3268  #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
3269  #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3270  #define CAN_F5R1_FB5_Pos       (5U)
3271  #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
3272  #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3273  #define CAN_F5R1_FB6_Pos       (6U)
3274  #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
3275  #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3276  #define CAN_F5R1_FB7_Pos       (7U)
3277  #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
3278  #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3279  #define CAN_F5R1_FB8_Pos       (8U)
3280  #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
3281  #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3282  #define CAN_F5R1_FB9_Pos       (9U)
3283  #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
3284  #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3285  #define CAN_F5R1_FB10_Pos      (10U)
3286  #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
3287  #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3288  #define CAN_F5R1_FB11_Pos      (11U)
3289  #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
3290  #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3291  #define CAN_F5R1_FB12_Pos      (12U)
3292  #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
3293  #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3294  #define CAN_F5R1_FB13_Pos      (13U)
3295  #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
3296  #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3297  #define CAN_F5R1_FB14_Pos      (14U)
3298  #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
3299  #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3300  #define CAN_F5R1_FB15_Pos      (15U)
3301  #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
3302  #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3303  #define CAN_F5R1_FB16_Pos      (16U)
3304  #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
3305  #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3306  #define CAN_F5R1_FB17_Pos      (17U)
3307  #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
3308  #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3309  #define CAN_F5R1_FB18_Pos      (18U)
3310  #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
3311  #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3312  #define CAN_F5R1_FB19_Pos      (19U)
3313  #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
3314  #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3315  #define CAN_F5R1_FB20_Pos      (20U)
3316  #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
3317  #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3318  #define CAN_F5R1_FB21_Pos      (21U)
3319  #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
3320  #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3321  #define CAN_F5R1_FB22_Pos      (22U)
3322  #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
3323  #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3324  #define CAN_F5R1_FB23_Pos      (23U)
3325  #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
3326  #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3327  #define CAN_F5R1_FB24_Pos      (24U)
3328  #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
3329  #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3330  #define CAN_F5R1_FB25_Pos      (25U)
3331  #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
3332  #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3333  #define CAN_F5R1_FB26_Pos      (26U)
3334  #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
3335  #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3336  #define CAN_F5R1_FB27_Pos      (27U)
3337  #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
3338  #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3339  #define CAN_F5R1_FB28_Pos      (28U)
3340  #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
3341  #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3342  #define CAN_F5R1_FB29_Pos      (29U)
3343  #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
3344  #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3345  #define CAN_F5R1_FB30_Pos      (30U)
3346  #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
3347  #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3348  #define CAN_F5R1_FB31_Pos      (31U)
3349  #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
3350  #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3351  
3352  /*******************  Bit definition for CAN_F6R1 register  *******************/
3353  #define CAN_F6R1_FB0_Pos       (0U)
3354  #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
3355  #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3356  #define CAN_F6R1_FB1_Pos       (1U)
3357  #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
3358  #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3359  #define CAN_F6R1_FB2_Pos       (2U)
3360  #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
3361  #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3362  #define CAN_F6R1_FB3_Pos       (3U)
3363  #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
3364  #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3365  #define CAN_F6R1_FB4_Pos       (4U)
3366  #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
3367  #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3368  #define CAN_F6R1_FB5_Pos       (5U)
3369  #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
3370  #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3371  #define CAN_F6R1_FB6_Pos       (6U)
3372  #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
3373  #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3374  #define CAN_F6R1_FB7_Pos       (7U)
3375  #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
3376  #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3377  #define CAN_F6R1_FB8_Pos       (8U)
3378  #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
3379  #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3380  #define CAN_F6R1_FB9_Pos       (9U)
3381  #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
3382  #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3383  #define CAN_F6R1_FB10_Pos      (10U)
3384  #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
3385  #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3386  #define CAN_F6R1_FB11_Pos      (11U)
3387  #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
3388  #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3389  #define CAN_F6R1_FB12_Pos      (12U)
3390  #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
3391  #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3392  #define CAN_F6R1_FB13_Pos      (13U)
3393  #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
3394  #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3395  #define CAN_F6R1_FB14_Pos      (14U)
3396  #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
3397  #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3398  #define CAN_F6R1_FB15_Pos      (15U)
3399  #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
3400  #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3401  #define CAN_F6R1_FB16_Pos      (16U)
3402  #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
3403  #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3404  #define CAN_F6R1_FB17_Pos      (17U)
3405  #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
3406  #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3407  #define CAN_F6R1_FB18_Pos      (18U)
3408  #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
3409  #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3410  #define CAN_F6R1_FB19_Pos      (19U)
3411  #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
3412  #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3413  #define CAN_F6R1_FB20_Pos      (20U)
3414  #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
3415  #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3416  #define CAN_F6R1_FB21_Pos      (21U)
3417  #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
3418  #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3419  #define CAN_F6R1_FB22_Pos      (22U)
3420  #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
3421  #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3422  #define CAN_F6R1_FB23_Pos      (23U)
3423  #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
3424  #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3425  #define CAN_F6R1_FB24_Pos      (24U)
3426  #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
3427  #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3428  #define CAN_F6R1_FB25_Pos      (25U)
3429  #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
3430  #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3431  #define CAN_F6R1_FB26_Pos      (26U)
3432  #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
3433  #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3434  #define CAN_F6R1_FB27_Pos      (27U)
3435  #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
3436  #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3437  #define CAN_F6R1_FB28_Pos      (28U)
3438  #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
3439  #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3440  #define CAN_F6R1_FB29_Pos      (29U)
3441  #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
3442  #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3443  #define CAN_F6R1_FB30_Pos      (30U)
3444  #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
3445  #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3446  #define CAN_F6R1_FB31_Pos      (31U)
3447  #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
3448  #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3449  
3450  /*******************  Bit definition for CAN_F7R1 register  *******************/
3451  #define CAN_F7R1_FB0_Pos       (0U)
3452  #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
3453  #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3454  #define CAN_F7R1_FB1_Pos       (1U)
3455  #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
3456  #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3457  #define CAN_F7R1_FB2_Pos       (2U)
3458  #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
3459  #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3460  #define CAN_F7R1_FB3_Pos       (3U)
3461  #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
3462  #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3463  #define CAN_F7R1_FB4_Pos       (4U)
3464  #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
3465  #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3466  #define CAN_F7R1_FB5_Pos       (5U)
3467  #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
3468  #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3469  #define CAN_F7R1_FB6_Pos       (6U)
3470  #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
3471  #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3472  #define CAN_F7R1_FB7_Pos       (7U)
3473  #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
3474  #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3475  #define CAN_F7R1_FB8_Pos       (8U)
3476  #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
3477  #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3478  #define CAN_F7R1_FB9_Pos       (9U)
3479  #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
3480  #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
3481  #define CAN_F7R1_FB10_Pos      (10U)
3482  #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
3483  #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
3484  #define CAN_F7R1_FB11_Pos      (11U)
3485  #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
3486  #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
3487  #define CAN_F7R1_FB12_Pos      (12U)
3488  #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
3489  #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
3490  #define CAN_F7R1_FB13_Pos      (13U)
3491  #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
3492  #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
3493  #define CAN_F7R1_FB14_Pos      (14U)
3494  #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
3495  #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
3496  #define CAN_F7R1_FB15_Pos      (15U)
3497  #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
3498  #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
3499  #define CAN_F7R1_FB16_Pos      (16U)
3500  #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
3501  #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
3502  #define CAN_F7R1_FB17_Pos      (17U)
3503  #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
3504  #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
3505  #define CAN_F7R1_FB18_Pos      (18U)
3506  #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
3507  #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
3508  #define CAN_F7R1_FB19_Pos      (19U)
3509  #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
3510  #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
3511  #define CAN_F7R1_FB20_Pos      (20U)
3512  #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
3513  #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
3514  #define CAN_F7R1_FB21_Pos      (21U)
3515  #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
3516  #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
3517  #define CAN_F7R1_FB22_Pos      (22U)
3518  #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
3519  #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
3520  #define CAN_F7R1_FB23_Pos      (23U)
3521  #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
3522  #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
3523  #define CAN_F7R1_FB24_Pos      (24U)
3524  #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
3525  #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
3526  #define CAN_F7R1_FB25_Pos      (25U)
3527  #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
3528  #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
3529  #define CAN_F7R1_FB26_Pos      (26U)
3530  #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
3531  #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
3532  #define CAN_F7R1_FB27_Pos      (27U)
3533  #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
3534  #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
3535  #define CAN_F7R1_FB28_Pos      (28U)
3536  #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
3537  #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
3538  #define CAN_F7R1_FB29_Pos      (29U)
3539  #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
3540  #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
3541  #define CAN_F7R1_FB30_Pos      (30U)
3542  #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
3543  #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
3544  #define CAN_F7R1_FB31_Pos      (31U)
3545  #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
3546  #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
3547  
3548  /*******************  Bit definition for CAN_F8R1 register  *******************/
3549  #define CAN_F8R1_FB0_Pos       (0U)
3550  #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
3551  #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
3552  #define CAN_F8R1_FB1_Pos       (1U)
3553  #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
3554  #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
3555  #define CAN_F8R1_FB2_Pos       (2U)
3556  #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
3557  #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
3558  #define CAN_F8R1_FB3_Pos       (3U)
3559  #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
3560  #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
3561  #define CAN_F8R1_FB4_Pos       (4U)
3562  #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
3563  #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
3564  #define CAN_F8R1_FB5_Pos       (5U)
3565  #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
3566  #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
3567  #define CAN_F8R1_FB6_Pos       (6U)
3568  #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
3569  #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
3570  #define CAN_F8R1_FB7_Pos       (7U)
3571  #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
3572  #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
3573  #define CAN_F8R1_FB8_Pos       (8U)
3574  #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
3575  #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
3576  #define CAN_F8R1_FB9_Pos       (9U)
3577  #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
3578  #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
3579  #define CAN_F8R1_FB10_Pos      (10U)
3580  #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
3581  #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
3582  #define CAN_F8R1_FB11_Pos      (11U)
3583  #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
3584  #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
3585  #define CAN_F8R1_FB12_Pos      (12U)
3586  #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
3587  #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
3588  #define CAN_F8R1_FB13_Pos      (13U)
3589  #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
3590  #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
3591  #define CAN_F8R1_FB14_Pos      (14U)
3592  #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
3593  #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
3594  #define CAN_F8R1_FB15_Pos      (15U)
3595  #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
3596  #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
3597  #define CAN_F8R1_FB16_Pos      (16U)
3598  #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
3599  #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
3600  #define CAN_F8R1_FB17_Pos      (17U)
3601  #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
3602  #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
3603  #define CAN_F8R1_FB18_Pos      (18U)
3604  #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
3605  #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
3606  #define CAN_F8R1_FB19_Pos      (19U)
3607  #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
3608  #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
3609  #define CAN_F8R1_FB20_Pos      (20U)
3610  #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
3611  #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
3612  #define CAN_F8R1_FB21_Pos      (21U)
3613  #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
3614  #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
3615  #define CAN_F8R1_FB22_Pos      (22U)
3616  #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
3617  #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
3618  #define CAN_F8R1_FB23_Pos      (23U)
3619  #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
3620  #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
3621  #define CAN_F8R1_FB24_Pos      (24U)
3622  #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
3623  #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
3624  #define CAN_F8R1_FB25_Pos      (25U)
3625  #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
3626  #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
3627  #define CAN_F8R1_FB26_Pos      (26U)
3628  #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
3629  #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
3630  #define CAN_F8R1_FB27_Pos      (27U)
3631  #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
3632  #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
3633  #define CAN_F8R1_FB28_Pos      (28U)
3634  #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
3635  #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
3636  #define CAN_F8R1_FB29_Pos      (29U)
3637  #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
3638  #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
3639  #define CAN_F8R1_FB30_Pos      (30U)
3640  #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
3641  #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
3642  #define CAN_F8R1_FB31_Pos      (31U)
3643  #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
3644  #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
3645  
3646  /*******************  Bit definition for CAN_F9R1 register  *******************/
3647  #define CAN_F9R1_FB0_Pos       (0U)
3648  #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
3649  #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
3650  #define CAN_F9R1_FB1_Pos       (1U)
3651  #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
3652  #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
3653  #define CAN_F9R1_FB2_Pos       (2U)
3654  #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
3655  #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
3656  #define CAN_F9R1_FB3_Pos       (3U)
3657  #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
3658  #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
3659  #define CAN_F9R1_FB4_Pos       (4U)
3660  #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
3661  #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
3662  #define CAN_F9R1_FB5_Pos       (5U)
3663  #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
3664  #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
3665  #define CAN_F9R1_FB6_Pos       (6U)
3666  #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
3667  #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
3668  #define CAN_F9R1_FB7_Pos       (7U)
3669  #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
3670  #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
3671  #define CAN_F9R1_FB8_Pos       (8U)
3672  #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
3673  #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
3674  #define CAN_F9R1_FB9_Pos       (9U)
3675  #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
3676  #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
3677  #define CAN_F9R1_FB10_Pos      (10U)
3678  #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
3679  #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
3680  #define CAN_F9R1_FB11_Pos      (11U)
3681  #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
3682  #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
3683  #define CAN_F9R1_FB12_Pos      (12U)
3684  #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
3685  #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
3686  #define CAN_F9R1_FB13_Pos      (13U)
3687  #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
3688  #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
3689  #define CAN_F9R1_FB14_Pos      (14U)
3690  #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
3691  #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
3692  #define CAN_F9R1_FB15_Pos      (15U)
3693  #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
3694  #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
3695  #define CAN_F9R1_FB16_Pos      (16U)
3696  #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
3697  #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
3698  #define CAN_F9R1_FB17_Pos      (17U)
3699  #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
3700  #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
3701  #define CAN_F9R1_FB18_Pos      (18U)
3702  #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
3703  #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
3704  #define CAN_F9R1_FB19_Pos      (19U)
3705  #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
3706  #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
3707  #define CAN_F9R1_FB20_Pos      (20U)
3708  #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
3709  #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
3710  #define CAN_F9R1_FB21_Pos      (21U)
3711  #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
3712  #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
3713  #define CAN_F9R1_FB22_Pos      (22U)
3714  #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
3715  #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
3716  #define CAN_F9R1_FB23_Pos      (23U)
3717  #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
3718  #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
3719  #define CAN_F9R1_FB24_Pos      (24U)
3720  #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
3721  #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
3722  #define CAN_F9R1_FB25_Pos      (25U)
3723  #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
3724  #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
3725  #define CAN_F9R1_FB26_Pos      (26U)
3726  #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
3727  #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
3728  #define CAN_F9R1_FB27_Pos      (27U)
3729  #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
3730  #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
3731  #define CAN_F9R1_FB28_Pos      (28U)
3732  #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
3733  #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
3734  #define CAN_F9R1_FB29_Pos      (29U)
3735  #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
3736  #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
3737  #define CAN_F9R1_FB30_Pos      (30U)
3738  #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
3739  #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
3740  #define CAN_F9R1_FB31_Pos      (31U)
3741  #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
3742  #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
3743  
3744  /*******************  Bit definition for CAN_F10R1 register  ******************/
3745  #define CAN_F10R1_FB0_Pos      (0U)
3746  #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
3747  #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
3748  #define CAN_F10R1_FB1_Pos      (1U)
3749  #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
3750  #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
3751  #define CAN_F10R1_FB2_Pos      (2U)
3752  #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
3753  #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
3754  #define CAN_F10R1_FB3_Pos      (3U)
3755  #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
3756  #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
3757  #define CAN_F10R1_FB4_Pos      (4U)
3758  #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
3759  #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
3760  #define CAN_F10R1_FB5_Pos      (5U)
3761  #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
3762  #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
3763  #define CAN_F10R1_FB6_Pos      (6U)
3764  #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
3765  #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
3766  #define CAN_F10R1_FB7_Pos      (7U)
3767  #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
3768  #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
3769  #define CAN_F10R1_FB8_Pos      (8U)
3770  #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
3771  #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
3772  #define CAN_F10R1_FB9_Pos      (9U)
3773  #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
3774  #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
3775  #define CAN_F10R1_FB10_Pos     (10U)
3776  #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
3777  #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
3778  #define CAN_F10R1_FB11_Pos     (11U)
3779  #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
3780  #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
3781  #define CAN_F10R1_FB12_Pos     (12U)
3782  #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
3783  #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
3784  #define CAN_F10R1_FB13_Pos     (13U)
3785  #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
3786  #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
3787  #define CAN_F10R1_FB14_Pos     (14U)
3788  #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
3789  #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
3790  #define CAN_F10R1_FB15_Pos     (15U)
3791  #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
3792  #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
3793  #define CAN_F10R1_FB16_Pos     (16U)
3794  #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
3795  #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
3796  #define CAN_F10R1_FB17_Pos     (17U)
3797  #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
3798  #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
3799  #define CAN_F10R1_FB18_Pos     (18U)
3800  #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
3801  #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
3802  #define CAN_F10R1_FB19_Pos     (19U)
3803  #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
3804  #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
3805  #define CAN_F10R1_FB20_Pos     (20U)
3806  #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
3807  #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
3808  #define CAN_F10R1_FB21_Pos     (21U)
3809  #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
3810  #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
3811  #define CAN_F10R1_FB22_Pos     (22U)
3812  #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
3813  #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3814  #define CAN_F10R1_FB23_Pos     (23U)
3815  #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
3816  #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3817  #define CAN_F10R1_FB24_Pos     (24U)
3818  #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
3819  #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3820  #define CAN_F10R1_FB25_Pos     (25U)
3821  #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
3822  #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3823  #define CAN_F10R1_FB26_Pos     (26U)
3824  #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
3825  #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3826  #define CAN_F10R1_FB27_Pos     (27U)
3827  #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
3828  #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3829  #define CAN_F10R1_FB28_Pos     (28U)
3830  #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
3831  #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3832  #define CAN_F10R1_FB29_Pos     (29U)
3833  #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
3834  #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3835  #define CAN_F10R1_FB30_Pos     (30U)
3836  #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
3837  #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3838  #define CAN_F10R1_FB31_Pos     (31U)
3839  #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
3840  #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3841  
3842  /*******************  Bit definition for CAN_F11R1 register  ******************/
3843  #define CAN_F11R1_FB0_Pos      (0U)
3844  #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
3845  #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3846  #define CAN_F11R1_FB1_Pos      (1U)
3847  #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
3848  #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3849  #define CAN_F11R1_FB2_Pos      (2U)
3850  #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
3851  #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3852  #define CAN_F11R1_FB3_Pos      (3U)
3853  #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
3854  #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
3855  #define CAN_F11R1_FB4_Pos      (4U)
3856  #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
3857  #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
3858  #define CAN_F11R1_FB5_Pos      (5U)
3859  #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
3860  #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
3861  #define CAN_F11R1_FB6_Pos      (6U)
3862  #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
3863  #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
3864  #define CAN_F11R1_FB7_Pos      (7U)
3865  #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
3866  #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
3867  #define CAN_F11R1_FB8_Pos      (8U)
3868  #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
3869  #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
3870  #define CAN_F11R1_FB9_Pos      (9U)
3871  #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
3872  #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
3873  #define CAN_F11R1_FB10_Pos     (10U)
3874  #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
3875  #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
3876  #define CAN_F11R1_FB11_Pos     (11U)
3877  #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
3878  #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
3879  #define CAN_F11R1_FB12_Pos     (12U)
3880  #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
3881  #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
3882  #define CAN_F11R1_FB13_Pos     (13U)
3883  #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
3884  #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
3885  #define CAN_F11R1_FB14_Pos     (14U)
3886  #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
3887  #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
3888  #define CAN_F11R1_FB15_Pos     (15U)
3889  #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
3890  #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
3891  #define CAN_F11R1_FB16_Pos     (16U)
3892  #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
3893  #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
3894  #define CAN_F11R1_FB17_Pos     (17U)
3895  #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
3896  #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
3897  #define CAN_F11R1_FB18_Pos     (18U)
3898  #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
3899  #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
3900  #define CAN_F11R1_FB19_Pos     (19U)
3901  #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
3902  #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
3903  #define CAN_F11R1_FB20_Pos     (20U)
3904  #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
3905  #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
3906  #define CAN_F11R1_FB21_Pos     (21U)
3907  #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
3908  #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
3909  #define CAN_F11R1_FB22_Pos     (22U)
3910  #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
3911  #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
3912  #define CAN_F11R1_FB23_Pos     (23U)
3913  #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
3914  #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
3915  #define CAN_F11R1_FB24_Pos     (24U)
3916  #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
3917  #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
3918  #define CAN_F11R1_FB25_Pos     (25U)
3919  #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
3920  #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
3921  #define CAN_F11R1_FB26_Pos     (26U)
3922  #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
3923  #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
3924  #define CAN_F11R1_FB27_Pos     (27U)
3925  #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
3926  #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
3927  #define CAN_F11R1_FB28_Pos     (28U)
3928  #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
3929  #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
3930  #define CAN_F11R1_FB29_Pos     (29U)
3931  #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
3932  #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
3933  #define CAN_F11R1_FB30_Pos     (30U)
3934  #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
3935  #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
3936  #define CAN_F11R1_FB31_Pos     (31U)
3937  #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
3938  #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
3939  
3940  /*******************  Bit definition for CAN_F12R1 register  ******************/
3941  #define CAN_F12R1_FB0_Pos      (0U)
3942  #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
3943  #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
3944  #define CAN_F12R1_FB1_Pos      (1U)
3945  #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
3946  #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
3947  #define CAN_F12R1_FB2_Pos      (2U)
3948  #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
3949  #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
3950  #define CAN_F12R1_FB3_Pos      (3U)
3951  #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
3952  #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
3953  #define CAN_F12R1_FB4_Pos      (4U)
3954  #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
3955  #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
3956  #define CAN_F12R1_FB5_Pos      (5U)
3957  #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
3958  #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
3959  #define CAN_F12R1_FB6_Pos      (6U)
3960  #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
3961  #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
3962  #define CAN_F12R1_FB7_Pos      (7U)
3963  #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
3964  #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
3965  #define CAN_F12R1_FB8_Pos      (8U)
3966  #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
3967  #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
3968  #define CAN_F12R1_FB9_Pos      (9U)
3969  #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
3970  #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
3971  #define CAN_F12R1_FB10_Pos     (10U)
3972  #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
3973  #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
3974  #define CAN_F12R1_FB11_Pos     (11U)
3975  #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
3976  #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
3977  #define CAN_F12R1_FB12_Pos     (12U)
3978  #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
3979  #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
3980  #define CAN_F12R1_FB13_Pos     (13U)
3981  #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
3982  #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
3983  #define CAN_F12R1_FB14_Pos     (14U)
3984  #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
3985  #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
3986  #define CAN_F12R1_FB15_Pos     (15U)
3987  #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
3988  #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
3989  #define CAN_F12R1_FB16_Pos     (16U)
3990  #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
3991  #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
3992  #define CAN_F12R1_FB17_Pos     (17U)
3993  #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
3994  #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
3995  #define CAN_F12R1_FB18_Pos     (18U)
3996  #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
3997  #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
3998  #define CAN_F12R1_FB19_Pos     (19U)
3999  #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
4000  #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
4001  #define CAN_F12R1_FB20_Pos     (20U)
4002  #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
4003  #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
4004  #define CAN_F12R1_FB21_Pos     (21U)
4005  #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
4006  #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
4007  #define CAN_F12R1_FB22_Pos     (22U)
4008  #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
4009  #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
4010  #define CAN_F12R1_FB23_Pos     (23U)
4011  #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
4012  #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
4013  #define CAN_F12R1_FB24_Pos     (24U)
4014  #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
4015  #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
4016  #define CAN_F12R1_FB25_Pos     (25U)
4017  #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
4018  #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
4019  #define CAN_F12R1_FB26_Pos     (26U)
4020  #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
4021  #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
4022  #define CAN_F12R1_FB27_Pos     (27U)
4023  #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
4024  #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
4025  #define CAN_F12R1_FB28_Pos     (28U)
4026  #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
4027  #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
4028  #define CAN_F12R1_FB29_Pos     (29U)
4029  #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
4030  #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
4031  #define CAN_F12R1_FB30_Pos     (30U)
4032  #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
4033  #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
4034  #define CAN_F12R1_FB31_Pos     (31U)
4035  #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
4036  #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
4037  
4038  /*******************  Bit definition for CAN_F13R1 register  ******************/
4039  #define CAN_F13R1_FB0_Pos      (0U)
4040  #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
4041  #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
4042  #define CAN_F13R1_FB1_Pos      (1U)
4043  #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
4044  #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
4045  #define CAN_F13R1_FB2_Pos      (2U)
4046  #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
4047  #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
4048  #define CAN_F13R1_FB3_Pos      (3U)
4049  #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
4050  #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
4051  #define CAN_F13R1_FB4_Pos      (4U)
4052  #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
4053  #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
4054  #define CAN_F13R1_FB5_Pos      (5U)
4055  #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
4056  #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
4057  #define CAN_F13R1_FB6_Pos      (6U)
4058  #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
4059  #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
4060  #define CAN_F13R1_FB7_Pos      (7U)
4061  #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
4062  #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
4063  #define CAN_F13R1_FB8_Pos      (8U)
4064  #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
4065  #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
4066  #define CAN_F13R1_FB9_Pos      (9U)
4067  #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
4068  #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
4069  #define CAN_F13R1_FB10_Pos     (10U)
4070  #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
4071  #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
4072  #define CAN_F13R1_FB11_Pos     (11U)
4073  #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
4074  #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
4075  #define CAN_F13R1_FB12_Pos     (12U)
4076  #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
4077  #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4078  #define CAN_F13R1_FB13_Pos     (13U)
4079  #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
4080  #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4081  #define CAN_F13R1_FB14_Pos     (14U)
4082  #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
4083  #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4084  #define CAN_F13R1_FB15_Pos     (15U)
4085  #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
4086  #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4087  #define CAN_F13R1_FB16_Pos     (16U)
4088  #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4089  #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4090  #define CAN_F13R1_FB17_Pos     (17U)
4091  #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4092  #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4093  #define CAN_F13R1_FB18_Pos     (18U)
4094  #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4095  #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4096  #define CAN_F13R1_FB19_Pos     (19U)
4097  #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4098  #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4099  #define CAN_F13R1_FB20_Pos     (20U)
4100  #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4101  #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4102  #define CAN_F13R1_FB21_Pos     (21U)
4103  #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4104  #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4105  #define CAN_F13R1_FB22_Pos     (22U)
4106  #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4107  #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4108  #define CAN_F13R1_FB23_Pos     (23U)
4109  #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4110  #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4111  #define CAN_F13R1_FB24_Pos     (24U)
4112  #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4113  #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4114  #define CAN_F13R1_FB25_Pos     (25U)
4115  #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4116  #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4117  #define CAN_F13R1_FB26_Pos     (26U)
4118  #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4119  #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4120  #define CAN_F13R1_FB27_Pos     (27U)
4121  #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4122  #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4123  #define CAN_F13R1_FB28_Pos     (28U)
4124  #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4125  #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4126  #define CAN_F13R1_FB29_Pos     (29U)
4127  #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4128  #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4129  #define CAN_F13R1_FB30_Pos     (30U)
4130  #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4131  #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4132  #define CAN_F13R1_FB31_Pos     (31U)
4133  #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4134  #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4135  
4136  /*******************  Bit definition for CAN_F0R2 register  *******************/
4137  #define CAN_F0R2_FB0_Pos       (0U)
4138  #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4139  #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4140  #define CAN_F0R2_FB1_Pos       (1U)
4141  #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4142  #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4143  #define CAN_F0R2_FB2_Pos       (2U)
4144  #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4145  #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4146  #define CAN_F0R2_FB3_Pos       (3U)
4147  #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4148  #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4149  #define CAN_F0R2_FB4_Pos       (4U)
4150  #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4151  #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4152  #define CAN_F0R2_FB5_Pos       (5U)
4153  #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4154  #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4155  #define CAN_F0R2_FB6_Pos       (6U)
4156  #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4157  #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4158  #define CAN_F0R2_FB7_Pos       (7U)
4159  #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4160  #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4161  #define CAN_F0R2_FB8_Pos       (8U)
4162  #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4163  #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4164  #define CAN_F0R2_FB9_Pos       (9U)
4165  #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4166  #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4167  #define CAN_F0R2_FB10_Pos      (10U)
4168  #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4169  #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4170  #define CAN_F0R2_FB11_Pos      (11U)
4171  #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4172  #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4173  #define CAN_F0R2_FB12_Pos      (12U)
4174  #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4175  #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4176  #define CAN_F0R2_FB13_Pos      (13U)
4177  #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4178  #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4179  #define CAN_F0R2_FB14_Pos      (14U)
4180  #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4181  #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4182  #define CAN_F0R2_FB15_Pos      (15U)
4183  #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4184  #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4185  #define CAN_F0R2_FB16_Pos      (16U)
4186  #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4187  #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4188  #define CAN_F0R2_FB17_Pos      (17U)
4189  #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4190  #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4191  #define CAN_F0R2_FB18_Pos      (18U)
4192  #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4193  #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4194  #define CAN_F0R2_FB19_Pos      (19U)
4195  #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4196  #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4197  #define CAN_F0R2_FB20_Pos      (20U)
4198  #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4199  #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4200  #define CAN_F0R2_FB21_Pos      (21U)
4201  #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4202  #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4203  #define CAN_F0R2_FB22_Pos      (22U)
4204  #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4205  #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4206  #define CAN_F0R2_FB23_Pos      (23U)
4207  #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4208  #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4209  #define CAN_F0R2_FB24_Pos      (24U)
4210  #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4211  #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4212  #define CAN_F0R2_FB25_Pos      (25U)
4213  #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4214  #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4215  #define CAN_F0R2_FB26_Pos      (26U)
4216  #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4217  #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4218  #define CAN_F0R2_FB27_Pos      (27U)
4219  #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4220  #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4221  #define CAN_F0R2_FB28_Pos      (28U)
4222  #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4223  #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4224  #define CAN_F0R2_FB29_Pos      (29U)
4225  #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4226  #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4227  #define CAN_F0R2_FB30_Pos      (30U)
4228  #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4229  #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4230  #define CAN_F0R2_FB31_Pos      (31U)
4231  #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4232  #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4233  
4234  /*******************  Bit definition for CAN_F1R2 register  *******************/
4235  #define CAN_F1R2_FB0_Pos       (0U)
4236  #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4237  #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4238  #define CAN_F1R2_FB1_Pos       (1U)
4239  #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
4240  #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4241  #define CAN_F1R2_FB2_Pos       (2U)
4242  #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
4243  #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4244  #define CAN_F1R2_FB3_Pos       (3U)
4245  #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
4246  #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4247  #define CAN_F1R2_FB4_Pos       (4U)
4248  #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
4249  #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4250  #define CAN_F1R2_FB5_Pos       (5U)
4251  #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
4252  #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4253  #define CAN_F1R2_FB6_Pos       (6U)
4254  #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
4255  #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4256  #define CAN_F1R2_FB7_Pos       (7U)
4257  #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
4258  #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4259  #define CAN_F1R2_FB8_Pos       (8U)
4260  #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
4261  #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4262  #define CAN_F1R2_FB9_Pos       (9U)
4263  #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
4264  #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4265  #define CAN_F1R2_FB10_Pos      (10U)
4266  #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
4267  #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4268  #define CAN_F1R2_FB11_Pos      (11U)
4269  #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
4270  #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4271  #define CAN_F1R2_FB12_Pos      (12U)
4272  #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
4273  #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4274  #define CAN_F1R2_FB13_Pos      (13U)
4275  #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
4276  #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4277  #define CAN_F1R2_FB14_Pos      (14U)
4278  #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
4279  #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4280  #define CAN_F1R2_FB15_Pos      (15U)
4281  #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
4282  #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4283  #define CAN_F1R2_FB16_Pos      (16U)
4284  #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
4285  #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4286  #define CAN_F1R2_FB17_Pos      (17U)
4287  #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
4288  #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4289  #define CAN_F1R2_FB18_Pos      (18U)
4290  #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
4291  #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4292  #define CAN_F1R2_FB19_Pos      (19U)
4293  #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
4294  #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4295  #define CAN_F1R2_FB20_Pos      (20U)
4296  #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
4297  #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4298  #define CAN_F1R2_FB21_Pos      (21U)
4299  #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
4300  #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4301  #define CAN_F1R2_FB22_Pos      (22U)
4302  #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
4303  #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4304  #define CAN_F1R2_FB23_Pos      (23U)
4305  #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
4306  #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4307  #define CAN_F1R2_FB24_Pos      (24U)
4308  #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
4309  #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4310  #define CAN_F1R2_FB25_Pos      (25U)
4311  #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
4312  #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4313  #define CAN_F1R2_FB26_Pos      (26U)
4314  #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
4315  #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4316  #define CAN_F1R2_FB27_Pos      (27U)
4317  #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
4318  #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4319  #define CAN_F1R2_FB28_Pos      (28U)
4320  #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
4321  #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4322  #define CAN_F1R2_FB29_Pos      (29U)
4323  #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
4324  #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4325  #define CAN_F1R2_FB30_Pos      (30U)
4326  #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
4327  #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4328  #define CAN_F1R2_FB31_Pos      (31U)
4329  #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
4330  #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4331  
4332  /*******************  Bit definition for CAN_F2R2 register  *******************/
4333  #define CAN_F2R2_FB0_Pos       (0U)
4334  #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
4335  #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4336  #define CAN_F2R2_FB1_Pos       (1U)
4337  #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
4338  #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4339  #define CAN_F2R2_FB2_Pos       (2U)
4340  #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
4341  #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4342  #define CAN_F2R2_FB3_Pos       (3U)
4343  #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
4344  #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4345  #define CAN_F2R2_FB4_Pos       (4U)
4346  #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
4347  #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4348  #define CAN_F2R2_FB5_Pos       (5U)
4349  #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
4350  #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4351  #define CAN_F2R2_FB6_Pos       (6U)
4352  #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
4353  #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4354  #define CAN_F2R2_FB7_Pos       (7U)
4355  #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
4356  #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4357  #define CAN_F2R2_FB8_Pos       (8U)
4358  #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
4359  #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4360  #define CAN_F2R2_FB9_Pos       (9U)
4361  #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
4362  #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4363  #define CAN_F2R2_FB10_Pos      (10U)
4364  #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
4365  #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4366  #define CAN_F2R2_FB11_Pos      (11U)
4367  #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
4368  #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4369  #define CAN_F2R2_FB12_Pos      (12U)
4370  #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
4371  #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4372  #define CAN_F2R2_FB13_Pos      (13U)
4373  #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
4374  #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4375  #define CAN_F2R2_FB14_Pos      (14U)
4376  #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
4377  #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4378  #define CAN_F2R2_FB15_Pos      (15U)
4379  #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
4380  #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4381  #define CAN_F2R2_FB16_Pos      (16U)
4382  #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
4383  #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4384  #define CAN_F2R2_FB17_Pos      (17U)
4385  #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
4386  #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4387  #define CAN_F2R2_FB18_Pos      (18U)
4388  #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
4389  #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4390  #define CAN_F2R2_FB19_Pos      (19U)
4391  #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
4392  #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4393  #define CAN_F2R2_FB20_Pos      (20U)
4394  #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
4395  #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4396  #define CAN_F2R2_FB21_Pos      (21U)
4397  #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
4398  #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4399  #define CAN_F2R2_FB22_Pos      (22U)
4400  #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
4401  #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4402  #define CAN_F2R2_FB23_Pos      (23U)
4403  #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
4404  #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4405  #define CAN_F2R2_FB24_Pos      (24U)
4406  #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
4407  #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4408  #define CAN_F2R2_FB25_Pos      (25U)
4409  #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
4410  #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4411  #define CAN_F2R2_FB26_Pos      (26U)
4412  #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
4413  #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4414  #define CAN_F2R2_FB27_Pos      (27U)
4415  #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
4416  #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4417  #define CAN_F2R2_FB28_Pos      (28U)
4418  #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
4419  #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4420  #define CAN_F2R2_FB29_Pos      (29U)
4421  #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
4422  #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4423  #define CAN_F2R2_FB30_Pos      (30U)
4424  #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
4425  #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4426  #define CAN_F2R2_FB31_Pos      (31U)
4427  #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
4428  #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4429  
4430  /*******************  Bit definition for CAN_F3R2 register  *******************/
4431  #define CAN_F3R2_FB0_Pos       (0U)
4432  #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
4433  #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4434  #define CAN_F3R2_FB1_Pos       (1U)
4435  #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
4436  #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4437  #define CAN_F3R2_FB2_Pos       (2U)
4438  #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
4439  #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4440  #define CAN_F3R2_FB3_Pos       (3U)
4441  #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
4442  #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4443  #define CAN_F3R2_FB4_Pos       (4U)
4444  #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
4445  #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4446  #define CAN_F3R2_FB5_Pos       (5U)
4447  #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
4448  #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4449  #define CAN_F3R2_FB6_Pos       (6U)
4450  #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
4451  #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4452  #define CAN_F3R2_FB7_Pos       (7U)
4453  #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
4454  #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4455  #define CAN_F3R2_FB8_Pos       (8U)
4456  #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
4457  #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4458  #define CAN_F3R2_FB9_Pos       (9U)
4459  #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
4460  #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4461  #define CAN_F3R2_FB10_Pos      (10U)
4462  #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
4463  #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4464  #define CAN_F3R2_FB11_Pos      (11U)
4465  #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
4466  #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4467  #define CAN_F3R2_FB12_Pos      (12U)
4468  #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
4469  #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4470  #define CAN_F3R2_FB13_Pos      (13U)
4471  #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
4472  #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4473  #define CAN_F3R2_FB14_Pos      (14U)
4474  #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
4475  #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4476  #define CAN_F3R2_FB15_Pos      (15U)
4477  #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
4478  #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4479  #define CAN_F3R2_FB16_Pos      (16U)
4480  #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
4481  #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
4482  #define CAN_F3R2_FB17_Pos      (17U)
4483  #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
4484  #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
4485  #define CAN_F3R2_FB18_Pos      (18U)
4486  #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
4487  #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
4488  #define CAN_F3R2_FB19_Pos      (19U)
4489  #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
4490  #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
4491  #define CAN_F3R2_FB20_Pos      (20U)
4492  #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
4493  #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
4494  #define CAN_F3R2_FB21_Pos      (21U)
4495  #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
4496  #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
4497  #define CAN_F3R2_FB22_Pos      (22U)
4498  #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
4499  #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
4500  #define CAN_F3R2_FB23_Pos      (23U)
4501  #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
4502  #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
4503  #define CAN_F3R2_FB24_Pos      (24U)
4504  #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
4505  #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
4506  #define CAN_F3R2_FB25_Pos      (25U)
4507  #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
4508  #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
4509  #define CAN_F3R2_FB26_Pos      (26U)
4510  #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
4511  #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
4512  #define CAN_F3R2_FB27_Pos      (27U)
4513  #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
4514  #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
4515  #define CAN_F3R2_FB28_Pos      (28U)
4516  #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
4517  #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
4518  #define CAN_F3R2_FB29_Pos      (29U)
4519  #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
4520  #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
4521  #define CAN_F3R2_FB30_Pos      (30U)
4522  #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
4523  #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
4524  #define CAN_F3R2_FB31_Pos      (31U)
4525  #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
4526  #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
4527  
4528  /*******************  Bit definition for CAN_F4R2 register  *******************/
4529  #define CAN_F4R2_FB0_Pos       (0U)
4530  #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
4531  #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
4532  #define CAN_F4R2_FB1_Pos       (1U)
4533  #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
4534  #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
4535  #define CAN_F4R2_FB2_Pos       (2U)
4536  #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
4537  #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
4538  #define CAN_F4R2_FB3_Pos       (3U)
4539  #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
4540  #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
4541  #define CAN_F4R2_FB4_Pos       (4U)
4542  #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
4543  #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
4544  #define CAN_F4R2_FB5_Pos       (5U)
4545  #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
4546  #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
4547  #define CAN_F4R2_FB6_Pos       (6U)
4548  #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
4549  #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
4550  #define CAN_F4R2_FB7_Pos       (7U)
4551  #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
4552  #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
4553  #define CAN_F4R2_FB8_Pos       (8U)
4554  #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
4555  #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
4556  #define CAN_F4R2_FB9_Pos       (9U)
4557  #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
4558  #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
4559  #define CAN_F4R2_FB10_Pos      (10U)
4560  #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
4561  #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
4562  #define CAN_F4R2_FB11_Pos      (11U)
4563  #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
4564  #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
4565  #define CAN_F4R2_FB12_Pos      (12U)
4566  #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
4567  #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
4568  #define CAN_F4R2_FB13_Pos      (13U)
4569  #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
4570  #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
4571  #define CAN_F4R2_FB14_Pos      (14U)
4572  #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
4573  #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
4574  #define CAN_F4R2_FB15_Pos      (15U)
4575  #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
4576  #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
4577  #define CAN_F4R2_FB16_Pos      (16U)
4578  #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
4579  #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
4580  #define CAN_F4R2_FB17_Pos      (17U)
4581  #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
4582  #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
4583  #define CAN_F4R2_FB18_Pos      (18U)
4584  #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
4585  #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
4586  #define CAN_F4R2_FB19_Pos      (19U)
4587  #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
4588  #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
4589  #define CAN_F4R2_FB20_Pos      (20U)
4590  #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
4591  #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
4592  #define CAN_F4R2_FB21_Pos      (21U)
4593  #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
4594  #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
4595  #define CAN_F4R2_FB22_Pos      (22U)
4596  #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
4597  #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
4598  #define CAN_F4R2_FB23_Pos      (23U)
4599  #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
4600  #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
4601  #define CAN_F4R2_FB24_Pos      (24U)
4602  #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
4603  #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
4604  #define CAN_F4R2_FB25_Pos      (25U)
4605  #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
4606  #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
4607  #define CAN_F4R2_FB26_Pos      (26U)
4608  #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
4609  #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
4610  #define CAN_F4R2_FB27_Pos      (27U)
4611  #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
4612  #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
4613  #define CAN_F4R2_FB28_Pos      (28U)
4614  #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
4615  #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
4616  #define CAN_F4R2_FB29_Pos      (29U)
4617  #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
4618  #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
4619  #define CAN_F4R2_FB30_Pos      (30U)
4620  #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
4621  #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
4622  #define CAN_F4R2_FB31_Pos      (31U)
4623  #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
4624  #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
4625  
4626  /*******************  Bit definition for CAN_F5R2 register  *******************/
4627  #define CAN_F5R2_FB0_Pos       (0U)
4628  #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
4629  #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
4630  #define CAN_F5R2_FB1_Pos       (1U)
4631  #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
4632  #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
4633  #define CAN_F5R2_FB2_Pos       (2U)
4634  #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
4635  #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
4636  #define CAN_F5R2_FB3_Pos       (3U)
4637  #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
4638  #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
4639  #define CAN_F5R2_FB4_Pos       (4U)
4640  #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
4641  #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
4642  #define CAN_F5R2_FB5_Pos       (5U)
4643  #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
4644  #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
4645  #define CAN_F5R2_FB6_Pos       (6U)
4646  #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
4647  #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
4648  #define CAN_F5R2_FB7_Pos       (7U)
4649  #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
4650  #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
4651  #define CAN_F5R2_FB8_Pos       (8U)
4652  #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
4653  #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
4654  #define CAN_F5R2_FB9_Pos       (9U)
4655  #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
4656  #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
4657  #define CAN_F5R2_FB10_Pos      (10U)
4658  #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
4659  #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
4660  #define CAN_F5R2_FB11_Pos      (11U)
4661  #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
4662  #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
4663  #define CAN_F5R2_FB12_Pos      (12U)
4664  #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
4665  #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
4666  #define CAN_F5R2_FB13_Pos      (13U)
4667  #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
4668  #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
4669  #define CAN_F5R2_FB14_Pos      (14U)
4670  #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
4671  #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
4672  #define CAN_F5R2_FB15_Pos      (15U)
4673  #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
4674  #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
4675  #define CAN_F5R2_FB16_Pos      (16U)
4676  #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
4677  #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
4678  #define CAN_F5R2_FB17_Pos      (17U)
4679  #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
4680  #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
4681  #define CAN_F5R2_FB18_Pos      (18U)
4682  #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
4683  #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
4684  #define CAN_F5R2_FB19_Pos      (19U)
4685  #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
4686  #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
4687  #define CAN_F5R2_FB20_Pos      (20U)
4688  #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
4689  #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
4690  #define CAN_F5R2_FB21_Pos      (21U)
4691  #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
4692  #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
4693  #define CAN_F5R2_FB22_Pos      (22U)
4694  #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
4695  #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
4696  #define CAN_F5R2_FB23_Pos      (23U)
4697  #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
4698  #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
4699  #define CAN_F5R2_FB24_Pos      (24U)
4700  #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
4701  #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
4702  #define CAN_F5R2_FB25_Pos      (25U)
4703  #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
4704  #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
4705  #define CAN_F5R2_FB26_Pos      (26U)
4706  #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
4707  #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
4708  #define CAN_F5R2_FB27_Pos      (27U)
4709  #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
4710  #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
4711  #define CAN_F5R2_FB28_Pos      (28U)
4712  #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
4713  #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
4714  #define CAN_F5R2_FB29_Pos      (29U)
4715  #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
4716  #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
4717  #define CAN_F5R2_FB30_Pos      (30U)
4718  #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
4719  #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
4720  #define CAN_F5R2_FB31_Pos      (31U)
4721  #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
4722  #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
4723  
4724  /*******************  Bit definition for CAN_F6R2 register  *******************/
4725  #define CAN_F6R2_FB0_Pos       (0U)
4726  #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
4727  #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
4728  #define CAN_F6R2_FB1_Pos       (1U)
4729  #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
4730  #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
4731  #define CAN_F6R2_FB2_Pos       (2U)
4732  #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
4733  #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
4734  #define CAN_F6R2_FB3_Pos       (3U)
4735  #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
4736  #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
4737  #define CAN_F6R2_FB4_Pos       (4U)
4738  #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
4739  #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
4740  #define CAN_F6R2_FB5_Pos       (5U)
4741  #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
4742  #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
4743  #define CAN_F6R2_FB6_Pos       (6U)
4744  #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
4745  #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
4746  #define CAN_F6R2_FB7_Pos       (7U)
4747  #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
4748  #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
4749  #define CAN_F6R2_FB8_Pos       (8U)
4750  #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
4751  #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
4752  #define CAN_F6R2_FB9_Pos       (9U)
4753  #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
4754  #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
4755  #define CAN_F6R2_FB10_Pos      (10U)
4756  #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
4757  #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
4758  #define CAN_F6R2_FB11_Pos      (11U)
4759  #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
4760  #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
4761  #define CAN_F6R2_FB12_Pos      (12U)
4762  #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
4763  #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
4764  #define CAN_F6R2_FB13_Pos      (13U)
4765  #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
4766  #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
4767  #define CAN_F6R2_FB14_Pos      (14U)
4768  #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
4769  #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
4770  #define CAN_F6R2_FB15_Pos      (15U)
4771  #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
4772  #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
4773  #define CAN_F6R2_FB16_Pos      (16U)
4774  #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
4775  #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
4776  #define CAN_F6R2_FB17_Pos      (17U)
4777  #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
4778  #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
4779  #define CAN_F6R2_FB18_Pos      (18U)
4780  #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
4781  #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
4782  #define CAN_F6R2_FB19_Pos      (19U)
4783  #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
4784  #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
4785  #define CAN_F6R2_FB20_Pos      (20U)
4786  #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
4787  #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
4788  #define CAN_F6R2_FB21_Pos      (21U)
4789  #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
4790  #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
4791  #define CAN_F6R2_FB22_Pos      (22U)
4792  #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
4793  #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
4794  #define CAN_F6R2_FB23_Pos      (23U)
4795  #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
4796  #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
4797  #define CAN_F6R2_FB24_Pos      (24U)
4798  #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
4799  #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
4800  #define CAN_F6R2_FB25_Pos      (25U)
4801  #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
4802  #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
4803  #define CAN_F6R2_FB26_Pos      (26U)
4804  #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
4805  #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
4806  #define CAN_F6R2_FB27_Pos      (27U)
4807  #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
4808  #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
4809  #define CAN_F6R2_FB28_Pos      (28U)
4810  #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
4811  #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
4812  #define CAN_F6R2_FB29_Pos      (29U)
4813  #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
4814  #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4815  #define CAN_F6R2_FB30_Pos      (30U)
4816  #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
4817  #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4818  #define CAN_F6R2_FB31_Pos      (31U)
4819  #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
4820  #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4821  
4822  /*******************  Bit definition for CAN_F7R2 register  *******************/
4823  #define CAN_F7R2_FB0_Pos       (0U)
4824  #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
4825  #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4826  #define CAN_F7R2_FB1_Pos       (1U)
4827  #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
4828  #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4829  #define CAN_F7R2_FB2_Pos       (2U)
4830  #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
4831  #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4832  #define CAN_F7R2_FB3_Pos       (3U)
4833  #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
4834  #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4835  #define CAN_F7R2_FB4_Pos       (4U)
4836  #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
4837  #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4838  #define CAN_F7R2_FB5_Pos       (5U)
4839  #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
4840  #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4841  #define CAN_F7R2_FB6_Pos       (6U)
4842  #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
4843  #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4844  #define CAN_F7R2_FB7_Pos       (7U)
4845  #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
4846  #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4847  #define CAN_F7R2_FB8_Pos       (8U)
4848  #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
4849  #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4850  #define CAN_F7R2_FB9_Pos       (9U)
4851  #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
4852  #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
4853  #define CAN_F7R2_FB10_Pos      (10U)
4854  #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
4855  #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
4856  #define CAN_F7R2_FB11_Pos      (11U)
4857  #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
4858  #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
4859  #define CAN_F7R2_FB12_Pos      (12U)
4860  #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
4861  #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
4862  #define CAN_F7R2_FB13_Pos      (13U)
4863  #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
4864  #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
4865  #define CAN_F7R2_FB14_Pos      (14U)
4866  #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
4867  #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
4868  #define CAN_F7R2_FB15_Pos      (15U)
4869  #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
4870  #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
4871  #define CAN_F7R2_FB16_Pos      (16U)
4872  #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
4873  #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
4874  #define CAN_F7R2_FB17_Pos      (17U)
4875  #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
4876  #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
4877  #define CAN_F7R2_FB18_Pos      (18U)
4878  #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
4879  #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
4880  #define CAN_F7R2_FB19_Pos      (19U)
4881  #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
4882  #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
4883  #define CAN_F7R2_FB20_Pos      (20U)
4884  #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
4885  #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
4886  #define CAN_F7R2_FB21_Pos      (21U)
4887  #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
4888  #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
4889  #define CAN_F7R2_FB22_Pos      (22U)
4890  #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
4891  #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
4892  #define CAN_F7R2_FB23_Pos      (23U)
4893  #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
4894  #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
4895  #define CAN_F7R2_FB24_Pos      (24U)
4896  #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
4897  #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
4898  #define CAN_F7R2_FB25_Pos      (25U)
4899  #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
4900  #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
4901  #define CAN_F7R2_FB26_Pos      (26U)
4902  #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
4903  #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
4904  #define CAN_F7R2_FB27_Pos      (27U)
4905  #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
4906  #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
4907  #define CAN_F7R2_FB28_Pos      (28U)
4908  #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
4909  #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
4910  #define CAN_F7R2_FB29_Pos      (29U)
4911  #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
4912  #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
4913  #define CAN_F7R2_FB30_Pos      (30U)
4914  #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
4915  #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
4916  #define CAN_F7R2_FB31_Pos      (31U)
4917  #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
4918  #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
4919  
4920  /*******************  Bit definition for CAN_F8R2 register  *******************/
4921  #define CAN_F8R2_FB0_Pos       (0U)
4922  #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
4923  #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
4924  #define CAN_F8R2_FB1_Pos       (1U)
4925  #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
4926  #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
4927  #define CAN_F8R2_FB2_Pos       (2U)
4928  #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
4929  #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
4930  #define CAN_F8R2_FB3_Pos       (3U)
4931  #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
4932  #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
4933  #define CAN_F8R2_FB4_Pos       (4U)
4934  #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
4935  #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
4936  #define CAN_F8R2_FB5_Pos       (5U)
4937  #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
4938  #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
4939  #define CAN_F8R2_FB6_Pos       (6U)
4940  #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
4941  #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
4942  #define CAN_F8R2_FB7_Pos       (7U)
4943  #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
4944  #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
4945  #define CAN_F8R2_FB8_Pos       (8U)
4946  #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
4947  #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
4948  #define CAN_F8R2_FB9_Pos       (9U)
4949  #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
4950  #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
4951  #define CAN_F8R2_FB10_Pos      (10U)
4952  #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
4953  #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
4954  #define CAN_F8R2_FB11_Pos      (11U)
4955  #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
4956  #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
4957  #define CAN_F8R2_FB12_Pos      (12U)
4958  #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
4959  #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
4960  #define CAN_F8R2_FB13_Pos      (13U)
4961  #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
4962  #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
4963  #define CAN_F8R2_FB14_Pos      (14U)
4964  #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
4965  #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
4966  #define CAN_F8R2_FB15_Pos      (15U)
4967  #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
4968  #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
4969  #define CAN_F8R2_FB16_Pos      (16U)
4970  #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
4971  #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
4972  #define CAN_F8R2_FB17_Pos      (17U)
4973  #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
4974  #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
4975  #define CAN_F8R2_FB18_Pos      (18U)
4976  #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
4977  #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
4978  #define CAN_F8R2_FB19_Pos      (19U)
4979  #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
4980  #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
4981  #define CAN_F8R2_FB20_Pos      (20U)
4982  #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
4983  #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
4984  #define CAN_F8R2_FB21_Pos      (21U)
4985  #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
4986  #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
4987  #define CAN_F8R2_FB22_Pos      (22U)
4988  #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
4989  #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
4990  #define CAN_F8R2_FB23_Pos      (23U)
4991  #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
4992  #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
4993  #define CAN_F8R2_FB24_Pos      (24U)
4994  #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
4995  #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
4996  #define CAN_F8R2_FB25_Pos      (25U)
4997  #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
4998  #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
4999  #define CAN_F8R2_FB26_Pos      (26U)
5000  #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
5001  #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
5002  #define CAN_F8R2_FB27_Pos      (27U)
5003  #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
5004  #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
5005  #define CAN_F8R2_FB28_Pos      (28U)
5006  #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
5007  #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
5008  #define CAN_F8R2_FB29_Pos      (29U)
5009  #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
5010  #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
5011  #define CAN_F8R2_FB30_Pos      (30U)
5012  #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
5013  #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
5014  #define CAN_F8R2_FB31_Pos      (31U)
5015  #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
5016  #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
5017  
5018  /*******************  Bit definition for CAN_F9R2 register  *******************/
5019  #define CAN_F9R2_FB0_Pos       (0U)
5020  #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
5021  #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
5022  #define CAN_F9R2_FB1_Pos       (1U)
5023  #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
5024  #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
5025  #define CAN_F9R2_FB2_Pos       (2U)
5026  #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
5027  #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
5028  #define CAN_F9R2_FB3_Pos       (3U)
5029  #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
5030  #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
5031  #define CAN_F9R2_FB4_Pos       (4U)
5032  #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
5033  #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
5034  #define CAN_F9R2_FB5_Pos       (5U)
5035  #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
5036  #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
5037  #define CAN_F9R2_FB6_Pos       (6U)
5038  #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
5039  #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
5040  #define CAN_F9R2_FB7_Pos       (7U)
5041  #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
5042  #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
5043  #define CAN_F9R2_FB8_Pos       (8U)
5044  #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
5045  #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
5046  #define CAN_F9R2_FB9_Pos       (9U)
5047  #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
5048  #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
5049  #define CAN_F9R2_FB10_Pos      (10U)
5050  #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
5051  #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
5052  #define CAN_F9R2_FB11_Pos      (11U)
5053  #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
5054  #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
5055  #define CAN_F9R2_FB12_Pos      (12U)
5056  #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
5057  #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
5058  #define CAN_F9R2_FB13_Pos      (13U)
5059  #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
5060  #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
5061  #define CAN_F9R2_FB14_Pos      (14U)
5062  #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
5063  #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
5064  #define CAN_F9R2_FB15_Pos      (15U)
5065  #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
5066  #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
5067  #define CAN_F9R2_FB16_Pos      (16U)
5068  #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
5069  #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
5070  #define CAN_F9R2_FB17_Pos      (17U)
5071  #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
5072  #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
5073  #define CAN_F9R2_FB18_Pos      (18U)
5074  #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
5075  #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
5076  #define CAN_F9R2_FB19_Pos      (19U)
5077  #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
5078  #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5079  #define CAN_F9R2_FB20_Pos      (20U)
5080  #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
5081  #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5082  #define CAN_F9R2_FB21_Pos      (21U)
5083  #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
5084  #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5085  #define CAN_F9R2_FB22_Pos      (22U)
5086  #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
5087  #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5088  #define CAN_F9R2_FB23_Pos      (23U)
5089  #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5090  #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5091  #define CAN_F9R2_FB24_Pos      (24U)
5092  #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5093  #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5094  #define CAN_F9R2_FB25_Pos      (25U)
5095  #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5096  #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5097  #define CAN_F9R2_FB26_Pos      (26U)
5098  #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5099  #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5100  #define CAN_F9R2_FB27_Pos      (27U)
5101  #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5102  #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5103  #define CAN_F9R2_FB28_Pos      (28U)
5104  #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5105  #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5106  #define CAN_F9R2_FB29_Pos      (29U)
5107  #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5108  #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5109  #define CAN_F9R2_FB30_Pos      (30U)
5110  #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5111  #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5112  #define CAN_F9R2_FB31_Pos      (31U)
5113  #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5114  #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5115  
5116  /*******************  Bit definition for CAN_F10R2 register  ******************/
5117  #define CAN_F10R2_FB0_Pos      (0U)
5118  #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5119  #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5120  #define CAN_F10R2_FB1_Pos      (1U)
5121  #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5122  #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5123  #define CAN_F10R2_FB2_Pos      (2U)
5124  #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5125  #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5126  #define CAN_F10R2_FB3_Pos      (3U)
5127  #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5128  #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5129  #define CAN_F10R2_FB4_Pos      (4U)
5130  #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5131  #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5132  #define CAN_F10R2_FB5_Pos      (5U)
5133  #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5134  #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5135  #define CAN_F10R2_FB6_Pos      (6U)
5136  #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5137  #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5138  #define CAN_F10R2_FB7_Pos      (7U)
5139  #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5140  #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5141  #define CAN_F10R2_FB8_Pos      (8U)
5142  #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5143  #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5144  #define CAN_F10R2_FB9_Pos      (9U)
5145  #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5146  #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5147  #define CAN_F10R2_FB10_Pos     (10U)
5148  #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5149  #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5150  #define CAN_F10R2_FB11_Pos     (11U)
5151  #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5152  #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5153  #define CAN_F10R2_FB12_Pos     (12U)
5154  #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5155  #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5156  #define CAN_F10R2_FB13_Pos     (13U)
5157  #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5158  #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5159  #define CAN_F10R2_FB14_Pos     (14U)
5160  #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5161  #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5162  #define CAN_F10R2_FB15_Pos     (15U)
5163  #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5164  #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5165  #define CAN_F10R2_FB16_Pos     (16U)
5166  #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5167  #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5168  #define CAN_F10R2_FB17_Pos     (17U)
5169  #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5170  #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5171  #define CAN_F10R2_FB18_Pos     (18U)
5172  #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5173  #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5174  #define CAN_F10R2_FB19_Pos     (19U)
5175  #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5176  #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5177  #define CAN_F10R2_FB20_Pos     (20U)
5178  #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5179  #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5180  #define CAN_F10R2_FB21_Pos     (21U)
5181  #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5182  #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5183  #define CAN_F10R2_FB22_Pos     (22U)
5184  #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5185  #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5186  #define CAN_F10R2_FB23_Pos     (23U)
5187  #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5188  #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5189  #define CAN_F10R2_FB24_Pos     (24U)
5190  #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5191  #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5192  #define CAN_F10R2_FB25_Pos     (25U)
5193  #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5194  #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5195  #define CAN_F10R2_FB26_Pos     (26U)
5196  #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5197  #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5198  #define CAN_F10R2_FB27_Pos     (27U)
5199  #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5200  #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5201  #define CAN_F10R2_FB28_Pos     (28U)
5202  #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5203  #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5204  #define CAN_F10R2_FB29_Pos     (29U)
5205  #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5206  #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5207  #define CAN_F10R2_FB30_Pos     (30U)
5208  #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5209  #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5210  #define CAN_F10R2_FB31_Pos     (31U)
5211  #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5212  #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5213  
5214  /*******************  Bit definition for CAN_F11R2 register  ******************/
5215  #define CAN_F11R2_FB0_Pos      (0U)
5216  #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5217  #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5218  #define CAN_F11R2_FB1_Pos      (1U)
5219  #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5220  #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5221  #define CAN_F11R2_FB2_Pos      (2U)
5222  #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5223  #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5224  #define CAN_F11R2_FB3_Pos      (3U)
5225  #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5226  #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5227  #define CAN_F11R2_FB4_Pos      (4U)
5228  #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5229  #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5230  #define CAN_F11R2_FB5_Pos      (5U)
5231  #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5232  #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5233  #define CAN_F11R2_FB6_Pos      (6U)
5234  #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5235  #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5236  #define CAN_F11R2_FB7_Pos      (7U)
5237  #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5238  #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5239  #define CAN_F11R2_FB8_Pos      (8U)
5240  #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
5241  #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5242  #define CAN_F11R2_FB9_Pos      (9U)
5243  #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
5244  #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5245  #define CAN_F11R2_FB10_Pos     (10U)
5246  #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
5247  #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5248  #define CAN_F11R2_FB11_Pos     (11U)
5249  #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
5250  #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5251  #define CAN_F11R2_FB12_Pos     (12U)
5252  #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
5253  #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5254  #define CAN_F11R2_FB13_Pos     (13U)
5255  #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
5256  #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5257  #define CAN_F11R2_FB14_Pos     (14U)
5258  #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
5259  #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5260  #define CAN_F11R2_FB15_Pos     (15U)
5261  #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
5262  #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5263  #define CAN_F11R2_FB16_Pos     (16U)
5264  #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
5265  #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5266  #define CAN_F11R2_FB17_Pos     (17U)
5267  #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
5268  #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5269  #define CAN_F11R2_FB18_Pos     (18U)
5270  #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
5271  #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5272  #define CAN_F11R2_FB19_Pos     (19U)
5273  #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
5274  #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5275  #define CAN_F11R2_FB20_Pos     (20U)
5276  #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
5277  #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5278  #define CAN_F11R2_FB21_Pos     (21U)
5279  #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
5280  #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5281  #define CAN_F11R2_FB22_Pos     (22U)
5282  #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
5283  #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5284  #define CAN_F11R2_FB23_Pos     (23U)
5285  #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
5286  #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5287  #define CAN_F11R2_FB24_Pos     (24U)
5288  #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
5289  #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5290  #define CAN_F11R2_FB25_Pos     (25U)
5291  #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
5292  #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5293  #define CAN_F11R2_FB26_Pos     (26U)
5294  #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
5295  #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5296  #define CAN_F11R2_FB27_Pos     (27U)
5297  #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
5298  #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5299  #define CAN_F11R2_FB28_Pos     (28U)
5300  #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
5301  #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5302  #define CAN_F11R2_FB29_Pos     (29U)
5303  #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
5304  #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5305  #define CAN_F11R2_FB30_Pos     (30U)
5306  #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
5307  #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5308  #define CAN_F11R2_FB31_Pos     (31U)
5309  #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
5310  #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5311  
5312  /*******************  Bit definition for CAN_F12R2 register  ******************/
5313  #define CAN_F12R2_FB0_Pos      (0U)
5314  #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
5315  #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5316  #define CAN_F12R2_FB1_Pos      (1U)
5317  #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
5318  #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5319  #define CAN_F12R2_FB2_Pos      (2U)
5320  #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
5321  #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5322  #define CAN_F12R2_FB3_Pos      (3U)
5323  #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
5324  #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5325  #define CAN_F12R2_FB4_Pos      (4U)
5326  #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
5327  #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5328  #define CAN_F12R2_FB5_Pos      (5U)
5329  #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
5330  #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5331  #define CAN_F12R2_FB6_Pos      (6U)
5332  #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
5333  #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5334  #define CAN_F12R2_FB7_Pos      (7U)
5335  #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
5336  #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5337  #define CAN_F12R2_FB8_Pos      (8U)
5338  #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
5339  #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5340  #define CAN_F12R2_FB9_Pos      (9U)
5341  #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
5342  #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5343  #define CAN_F12R2_FB10_Pos     (10U)
5344  #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
5345  #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5346  #define CAN_F12R2_FB11_Pos     (11U)
5347  #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
5348  #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5349  #define CAN_F12R2_FB12_Pos     (12U)
5350  #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
5351  #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5352  #define CAN_F12R2_FB13_Pos     (13U)
5353  #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
5354  #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5355  #define CAN_F12R2_FB14_Pos     (14U)
5356  #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
5357  #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5358  #define CAN_F12R2_FB15_Pos     (15U)
5359  #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
5360  #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5361  #define CAN_F12R2_FB16_Pos     (16U)
5362  #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
5363  #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5364  #define CAN_F12R2_FB17_Pos     (17U)
5365  #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
5366  #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5367  #define CAN_F12R2_FB18_Pos     (18U)
5368  #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
5369  #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5370  #define CAN_F12R2_FB19_Pos     (19U)
5371  #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
5372  #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5373  #define CAN_F12R2_FB20_Pos     (20U)
5374  #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
5375  #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5376  #define CAN_F12R2_FB21_Pos     (21U)
5377  #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
5378  #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5379  #define CAN_F12R2_FB22_Pos     (22U)
5380  #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
5381  #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5382  #define CAN_F12R2_FB23_Pos     (23U)
5383  #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
5384  #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5385  #define CAN_F12R2_FB24_Pos     (24U)
5386  #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
5387  #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5388  #define CAN_F12R2_FB25_Pos     (25U)
5389  #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
5390  #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5391  #define CAN_F12R2_FB26_Pos     (26U)
5392  #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
5393  #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5394  #define CAN_F12R2_FB27_Pos     (27U)
5395  #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
5396  #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5397  #define CAN_F12R2_FB28_Pos     (28U)
5398  #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
5399  #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5400  #define CAN_F12R2_FB29_Pos     (29U)
5401  #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
5402  #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5403  #define CAN_F12R2_FB30_Pos     (30U)
5404  #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
5405  #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5406  #define CAN_F12R2_FB31_Pos     (31U)
5407  #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
5408  #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5409  
5410  /*******************  Bit definition for CAN_F13R2 register  ******************/
5411  #define CAN_F13R2_FB0_Pos      (0U)
5412  #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
5413  #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5414  #define CAN_F13R2_FB1_Pos      (1U)
5415  #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
5416  #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5417  #define CAN_F13R2_FB2_Pos      (2U)
5418  #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
5419  #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5420  #define CAN_F13R2_FB3_Pos      (3U)
5421  #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
5422  #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5423  #define CAN_F13R2_FB4_Pos      (4U)
5424  #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
5425  #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5426  #define CAN_F13R2_FB5_Pos      (5U)
5427  #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
5428  #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5429  #define CAN_F13R2_FB6_Pos      (6U)
5430  #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
5431  #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5432  #define CAN_F13R2_FB7_Pos      (7U)
5433  #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
5434  #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5435  #define CAN_F13R2_FB8_Pos      (8U)
5436  #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
5437  #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5438  #define CAN_F13R2_FB9_Pos      (9U)
5439  #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
5440  #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5441  #define CAN_F13R2_FB10_Pos     (10U)
5442  #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
5443  #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5444  #define CAN_F13R2_FB11_Pos     (11U)
5445  #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
5446  #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5447  #define CAN_F13R2_FB12_Pos     (12U)
5448  #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
5449  #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5450  #define CAN_F13R2_FB13_Pos     (13U)
5451  #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
5452  #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5453  #define CAN_F13R2_FB14_Pos     (14U)
5454  #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
5455  #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5456  #define CAN_F13R2_FB15_Pos     (15U)
5457  #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
5458  #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5459  #define CAN_F13R2_FB16_Pos     (16U)
5460  #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
5461  #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5462  #define CAN_F13R2_FB17_Pos     (17U)
5463  #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
5464  #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5465  #define CAN_F13R2_FB18_Pos     (18U)
5466  #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
5467  #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5468  #define CAN_F13R2_FB19_Pos     (19U)
5469  #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
5470  #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5471  #define CAN_F13R2_FB20_Pos     (20U)
5472  #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
5473  #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5474  #define CAN_F13R2_FB21_Pos     (21U)
5475  #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
5476  #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5477  #define CAN_F13R2_FB22_Pos     (22U)
5478  #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
5479  #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
5480  #define CAN_F13R2_FB23_Pos     (23U)
5481  #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
5482  #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
5483  #define CAN_F13R2_FB24_Pos     (24U)
5484  #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
5485  #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
5486  #define CAN_F13R2_FB25_Pos     (25U)
5487  #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
5488  #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
5489  #define CAN_F13R2_FB26_Pos     (26U)
5490  #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
5491  #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
5492  #define CAN_F13R2_FB27_Pos     (27U)
5493  #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
5494  #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
5495  #define CAN_F13R2_FB28_Pos     (28U)
5496  #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
5497  #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
5498  #define CAN_F13R2_FB29_Pos     (29U)
5499  #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
5500  #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
5501  #define CAN_F13R2_FB30_Pos     (30U)
5502  #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
5503  #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
5504  #define CAN_F13R2_FB31_Pos     (31U)
5505  #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
5506  #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
5507  
5508  /******************************************************************************/
5509  /*                                                                            */
5510  /*                          CRC calculation unit                              */
5511  /*                                                                            */
5512  /******************************************************************************/
5513  /*******************  Bit definition for CRC_DR register  *********************/
5514  #define CRC_DR_DR_Pos       (0U)
5515  #define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
5516  #define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
5517  
5518  
5519  /*******************  Bit definition for CRC_IDR register  ********************/
5520  #define CRC_IDR_IDR_Pos     (0U)
5521  #define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
5522  #define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
5523  
5524  
5525  /********************  Bit definition for CRC_CR register  ********************/
5526  #define CRC_CR_RESET_Pos    (0U)
5527  #define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
5528  #define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
5529  
5530  /******************************************************************************/
5531  /*                                                                            */
5532  /*                      Digital to Analog Converter                           */
5533  /*                                                                            */
5534  /******************************************************************************/
5535  /*
5536   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5537   */
5538  #define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5539  /********************  Bit definition for DAC_CR register  ********************/
5540  #define DAC_CR_EN1_Pos              (0U)
5541  #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
5542  #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
5543  #define DAC_CR_BOFF1_Pos            (1U)
5544  #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
5545  #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
5546  #define DAC_CR_TEN1_Pos             (2U)
5547  #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
5548  #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
5549  
5550  #define DAC_CR_TSEL1_Pos            (3U)
5551  #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
5552  #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5553  #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5554  #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5555  #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5556  
5557  #define DAC_CR_WAVE1_Pos            (6U)
5558  #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
5559  #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5560  #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5561  #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5562  
5563  #define DAC_CR_MAMP1_Pos            (8U)
5564  #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
5565  #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5566  #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5567  #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5568  #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5569  #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5570  
5571  #define DAC_CR_DMAEN1_Pos           (12U)
5572  #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
5573  #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
5574  #define DAC_CR_DMAUDRIE1_Pos        (13U)
5575  #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
5576  #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
5577  #define DAC_CR_EN2_Pos              (16U)
5578  #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
5579  #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
5580  #define DAC_CR_BOFF2_Pos            (17U)
5581  #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
5582  #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
5583  #define DAC_CR_TEN2_Pos             (18U)
5584  #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
5585  #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
5586  
5587  #define DAC_CR_TSEL2_Pos            (19U)
5588  #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
5589  #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5590  #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5591  #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5592  #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5593  
5594  #define DAC_CR_WAVE2_Pos            (22U)
5595  #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
5596  #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5597  #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5598  #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5599  
5600  #define DAC_CR_MAMP2_Pos            (24U)
5601  #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
5602  #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5603  #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5604  #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5605  #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5606  #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5607  
5608  #define DAC_CR_DMAEN2_Pos           (28U)
5609  #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
5610  #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
5611  #define DAC_CR_DMAUDRIE2_Pos        (29U)
5612  #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
5613  #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
5614  
5615  /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5616  #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5617  #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
5618  #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5619  #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5620  #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
5621  #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5622  
5623  /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5624  #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5625  #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
5626  #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5627  
5628  /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5629  #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5630  #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5631  #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5632  
5633  /******************  Bit definition for DAC_DHR8R1 register  ******************/
5634  #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5635  #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
5636  #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5637  
5638  /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5639  #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5640  #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
5641  #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5642  
5643  /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5644  #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5645  #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
5646  #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5647  
5648  /******************  Bit definition for DAC_DHR8R2 register  ******************/
5649  #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5650  #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
5651  #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5652  
5653  /*****************  Bit definition for DAC_DHR12RD register  ******************/
5654  #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5655  #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
5656  #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5657  #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5658  #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
5659  #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5660  
5661  /*****************  Bit definition for DAC_DHR12LD register  ******************/
5662  #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5663  #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5664  #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5665  #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5666  #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
5667  #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5668  
5669  /******************  Bit definition for DAC_DHR8RD register  ******************/
5670  #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5671  #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
5672  #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5673  #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5674  #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
5675  #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5676  
5677  /*******************  Bit definition for DAC_DOR1 register  *******************/
5678  #define DAC_DOR1_DACC1DOR_Pos       (0U)
5679  #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
5680  #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
5681  
5682  /*******************  Bit definition for DAC_DOR2 register  *******************/
5683  #define DAC_DOR2_DACC2DOR_Pos       (0U)
5684  #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
5685  #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
5686  
5687  /********************  Bit definition for DAC_SR register  ********************/
5688  #define DAC_SR_DMAUDR1_Pos          (13U)
5689  #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
5690  #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
5691  #define DAC_SR_DMAUDR2_Pos          (29U)
5692  #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
5693  #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
5694  
5695  /******************************************************************************/
5696  /*                                                                            */
5697  /*                                    DCMI                                    */
5698  /*                                                                            */
5699  /******************************************************************************/
5700  /********************  Bits definition for DCMI_CR register  ******************/
5701  #define DCMI_CR_CAPTURE_Pos        (0U)
5702  #define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
5703  #define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
5704  #define DCMI_CR_CM_Pos             (1U)
5705  #define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
5706  #define DCMI_CR_CM                 DCMI_CR_CM_Msk
5707  #define DCMI_CR_CROP_Pos           (2U)
5708  #define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
5709  #define DCMI_CR_CROP               DCMI_CR_CROP_Msk
5710  #define DCMI_CR_JPEG_Pos           (3U)
5711  #define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
5712  #define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
5713  #define DCMI_CR_ESS_Pos            (4U)
5714  #define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
5715  #define DCMI_CR_ESS                DCMI_CR_ESS_Msk
5716  #define DCMI_CR_PCKPOL_Pos         (5U)
5717  #define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
5718  #define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
5719  #define DCMI_CR_HSPOL_Pos          (6U)
5720  #define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
5721  #define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
5722  #define DCMI_CR_VSPOL_Pos          (7U)
5723  #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
5724  #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
5725  #define DCMI_CR_FCRC_0             0x00000100U
5726  #define DCMI_CR_FCRC_1             0x00000200U
5727  #define DCMI_CR_EDM_0              0x00000400U
5728  #define DCMI_CR_EDM_1              0x00000800U
5729  #define DCMI_CR_ENABLE_Pos         (14U)
5730  #define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
5731  #define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
5732  
5733  /********************  Bits definition for DCMI_SR register  ******************/
5734  #define DCMI_SR_HSYNC_Pos          (0U)
5735  #define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
5736  #define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
5737  #define DCMI_SR_VSYNC_Pos          (1U)
5738  #define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
5739  #define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
5740  #define DCMI_SR_FNE_Pos            (2U)
5741  #define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
5742  #define DCMI_SR_FNE                DCMI_SR_FNE_Msk
5743  
5744  /********************  Bits definition for DCMI_RIS register  *****************/
5745  #define DCMI_RIS_FRAME_RIS_Pos     (0U)
5746  #define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
5747  #define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
5748  #define DCMI_RIS_OVR_RIS_Pos       (1U)
5749  #define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
5750  #define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
5751  #define DCMI_RIS_ERR_RIS_Pos       (2U)
5752  #define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
5753  #define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
5754  #define DCMI_RIS_VSYNC_RIS_Pos     (3U)
5755  #define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
5756  #define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
5757  #define DCMI_RIS_LINE_RIS_Pos      (4U)
5758  #define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
5759  #define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
5760  /* Legacy defines */
5761  #define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
5762  #define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
5763  #define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
5764  #define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
5765  #define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
5766  #define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
5767  
5768  /********************  Bits definition for DCMI_IER register  *****************/
5769  #define DCMI_IER_FRAME_IE_Pos      (0U)
5770  #define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
5771  #define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
5772  #define DCMI_IER_OVR_IE_Pos        (1U)
5773  #define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
5774  #define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
5775  #define DCMI_IER_ERR_IE_Pos        (2U)
5776  #define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
5777  #define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
5778  #define DCMI_IER_VSYNC_IE_Pos      (3U)
5779  #define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
5780  #define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
5781  #define DCMI_IER_LINE_IE_Pos       (4U)
5782  #define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
5783  #define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
5784  /* Legacy defines */
5785  #define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
5786  
5787  /********************  Bits definition for DCMI_MIS register  *****************/
5788  #define DCMI_MIS_FRAME_MIS_Pos     (0U)
5789  #define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
5790  #define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
5791  #define DCMI_MIS_OVR_MIS_Pos       (1U)
5792  #define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
5793  #define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
5794  #define DCMI_MIS_ERR_MIS_Pos       (2U)
5795  #define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
5796  #define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
5797  #define DCMI_MIS_VSYNC_MIS_Pos     (3U)
5798  #define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
5799  #define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
5800  #define DCMI_MIS_LINE_MIS_Pos      (4U)
5801  #define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
5802  #define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
5803  
5804  /* Legacy defines */
5805  #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
5806  #define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
5807  #define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
5808  #define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
5809  #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
5810  
5811  /********************  Bits definition for DCMI_ICR register  *****************/
5812  #define DCMI_ICR_FRAME_ISC_Pos     (0U)
5813  #define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
5814  #define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
5815  #define DCMI_ICR_OVR_ISC_Pos       (1U)
5816  #define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
5817  #define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
5818  #define DCMI_ICR_ERR_ISC_Pos       (2U)
5819  #define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
5820  #define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
5821  #define DCMI_ICR_VSYNC_ISC_Pos     (3U)
5822  #define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
5823  #define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
5824  #define DCMI_ICR_LINE_ISC_Pos      (4U)
5825  #define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
5826  #define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
5827  
5828  /* Legacy defines */
5829  #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
5830  
5831  /********************  Bits definition for DCMI_ESCR register  ******************/
5832  #define DCMI_ESCR_FSC_Pos          (0U)
5833  #define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
5834  #define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
5835  #define DCMI_ESCR_LSC_Pos          (8U)
5836  #define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
5837  #define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
5838  #define DCMI_ESCR_LEC_Pos          (16U)
5839  #define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
5840  #define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
5841  #define DCMI_ESCR_FEC_Pos          (24U)
5842  #define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
5843  #define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
5844  
5845  /********************  Bits definition for DCMI_ESUR register  ******************/
5846  #define DCMI_ESUR_FSU_Pos          (0U)
5847  #define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
5848  #define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
5849  #define DCMI_ESUR_LSU_Pos          (8U)
5850  #define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
5851  #define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
5852  #define DCMI_ESUR_LEU_Pos          (16U)
5853  #define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
5854  #define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
5855  #define DCMI_ESUR_FEU_Pos          (24U)
5856  #define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
5857  #define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
5858  
5859  /********************  Bits definition for DCMI_CWSTRT register  ******************/
5860  #define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
5861  #define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
5862  #define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
5863  #define DCMI_CWSTRT_VST_Pos        (16U)
5864  #define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
5865  #define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
5866  
5867  /********************  Bits definition for DCMI_CWSIZE register  ******************/
5868  #define DCMI_CWSIZE_CAPCNT_Pos     (0U)
5869  #define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
5870  #define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
5871  #define DCMI_CWSIZE_VLINE_Pos      (16U)
5872  #define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
5873  #define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
5874  
5875  /********************  Bits definition for DCMI_DR register  *********************/
5876  #define DCMI_DR_BYTE0_Pos          (0U)
5877  #define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
5878  #define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
5879  #define DCMI_DR_BYTE1_Pos          (8U)
5880  #define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
5881  #define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
5882  #define DCMI_DR_BYTE2_Pos          (16U)
5883  #define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
5884  #define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
5885  #define DCMI_DR_BYTE3_Pos          (24U)
5886  #define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
5887  #define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
5888  
5889  /******************************************************************************/
5890  /*                                                                            */
5891  /*                             DMA Controller                                 */
5892  /*                                                                            */
5893  /******************************************************************************/
5894  /********************  Bits definition for DMA_SxCR register  *****************/
5895  #define DMA_SxCR_CHSEL_Pos       (25U)
5896  #define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
5897  #define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk
5898  #define DMA_SxCR_CHSEL_0         0x02000000U
5899  #define DMA_SxCR_CHSEL_1         0x04000000U
5900  #define DMA_SxCR_CHSEL_2         0x08000000U
5901  #define DMA_SxCR_MBURST_Pos      (23U)
5902  #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
5903  #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
5904  #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
5905  #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
5906  #define DMA_SxCR_PBURST_Pos      (21U)
5907  #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
5908  #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
5909  #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
5910  #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
5911  #define DMA_SxCR_CT_Pos          (19U)
5912  #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
5913  #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
5914  #define DMA_SxCR_DBM_Pos         (18U)
5915  #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
5916  #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
5917  #define DMA_SxCR_PL_Pos          (16U)
5918  #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
5919  #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
5920  #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
5921  #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
5922  #define DMA_SxCR_PINCOS_Pos      (15U)
5923  #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
5924  #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
5925  #define DMA_SxCR_MSIZE_Pos       (13U)
5926  #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
5927  #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
5928  #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
5929  #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
5930  #define DMA_SxCR_PSIZE_Pos       (11U)
5931  #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
5932  #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
5933  #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
5934  #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
5935  #define DMA_SxCR_MINC_Pos        (10U)
5936  #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
5937  #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
5938  #define DMA_SxCR_PINC_Pos        (9U)
5939  #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
5940  #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
5941  #define DMA_SxCR_CIRC_Pos        (8U)
5942  #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
5943  #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
5944  #define DMA_SxCR_DIR_Pos         (6U)
5945  #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
5946  #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
5947  #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
5948  #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
5949  #define DMA_SxCR_PFCTRL_Pos      (5U)
5950  #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
5951  #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
5952  #define DMA_SxCR_TCIE_Pos        (4U)
5953  #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
5954  #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
5955  #define DMA_SxCR_HTIE_Pos        (3U)
5956  #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
5957  #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
5958  #define DMA_SxCR_TEIE_Pos        (2U)
5959  #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
5960  #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
5961  #define DMA_SxCR_DMEIE_Pos       (1U)
5962  #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
5963  #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
5964  #define DMA_SxCR_EN_Pos          (0U)
5965  #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
5966  #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
5967  
5968  /* Legacy defines */
5969  #define DMA_SxCR_ACK_Pos         (20U)
5970  #define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
5971  #define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk
5972  
5973  /********************  Bits definition for DMA_SxCNDTR register  **************/
5974  #define DMA_SxNDT_Pos            (0U)
5975  #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
5976  #define DMA_SxNDT                DMA_SxNDT_Msk
5977  #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
5978  #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
5979  #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
5980  #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
5981  #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
5982  #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
5983  #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
5984  #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
5985  #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
5986  #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
5987  #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
5988  #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
5989  #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
5990  #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
5991  #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
5992  #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
5993  
5994  /********************  Bits definition for DMA_SxFCR register  ****************/
5995  #define DMA_SxFCR_FEIE_Pos       (7U)
5996  #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
5997  #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
5998  #define DMA_SxFCR_FS_Pos         (3U)
5999  #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
6000  #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
6001  #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
6002  #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
6003  #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
6004  #define DMA_SxFCR_DMDIS_Pos      (2U)
6005  #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
6006  #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
6007  #define DMA_SxFCR_FTH_Pos        (0U)
6008  #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
6009  #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
6010  #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
6011  #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
6012  
6013  /********************  Bits definition for DMA_LISR register  *****************/
6014  #define DMA_LISR_TCIF3_Pos       (27U)
6015  #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
6016  #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
6017  #define DMA_LISR_HTIF3_Pos       (26U)
6018  #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
6019  #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
6020  #define DMA_LISR_TEIF3_Pos       (25U)
6021  #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
6022  #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
6023  #define DMA_LISR_DMEIF3_Pos      (24U)
6024  #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
6025  #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
6026  #define DMA_LISR_FEIF3_Pos       (22U)
6027  #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
6028  #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
6029  #define DMA_LISR_TCIF2_Pos       (21U)
6030  #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
6031  #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
6032  #define DMA_LISR_HTIF2_Pos       (20U)
6033  #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
6034  #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
6035  #define DMA_LISR_TEIF2_Pos       (19U)
6036  #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
6037  #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
6038  #define DMA_LISR_DMEIF2_Pos      (18U)
6039  #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
6040  #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
6041  #define DMA_LISR_FEIF2_Pos       (16U)
6042  #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
6043  #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
6044  #define DMA_LISR_TCIF1_Pos       (11U)
6045  #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
6046  #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
6047  #define DMA_LISR_HTIF1_Pos       (10U)
6048  #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
6049  #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
6050  #define DMA_LISR_TEIF1_Pos       (9U)
6051  #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
6052  #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
6053  #define DMA_LISR_DMEIF1_Pos      (8U)
6054  #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
6055  #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
6056  #define DMA_LISR_FEIF1_Pos       (6U)
6057  #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
6058  #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
6059  #define DMA_LISR_TCIF0_Pos       (5U)
6060  #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
6061  #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
6062  #define DMA_LISR_HTIF0_Pos       (4U)
6063  #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
6064  #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
6065  #define DMA_LISR_TEIF0_Pos       (3U)
6066  #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
6067  #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
6068  #define DMA_LISR_DMEIF0_Pos      (2U)
6069  #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
6070  #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
6071  #define DMA_LISR_FEIF0_Pos       (0U)
6072  #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
6073  #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
6074  
6075  /********************  Bits definition for DMA_HISR register  *****************/
6076  #define DMA_HISR_TCIF7_Pos       (27U)
6077  #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
6078  #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
6079  #define DMA_HISR_HTIF7_Pos       (26U)
6080  #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
6081  #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
6082  #define DMA_HISR_TEIF7_Pos       (25U)
6083  #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
6084  #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
6085  #define DMA_HISR_DMEIF7_Pos      (24U)
6086  #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
6087  #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
6088  #define DMA_HISR_FEIF7_Pos       (22U)
6089  #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
6090  #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
6091  #define DMA_HISR_TCIF6_Pos       (21U)
6092  #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
6093  #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
6094  #define DMA_HISR_HTIF6_Pos       (20U)
6095  #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
6096  #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
6097  #define DMA_HISR_TEIF6_Pos       (19U)
6098  #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
6099  #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
6100  #define DMA_HISR_DMEIF6_Pos      (18U)
6101  #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
6102  #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
6103  #define DMA_HISR_FEIF6_Pos       (16U)
6104  #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
6105  #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
6106  #define DMA_HISR_TCIF5_Pos       (11U)
6107  #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
6108  #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
6109  #define DMA_HISR_HTIF5_Pos       (10U)
6110  #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
6111  #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
6112  #define DMA_HISR_TEIF5_Pos       (9U)
6113  #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
6114  #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
6115  #define DMA_HISR_DMEIF5_Pos      (8U)
6116  #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
6117  #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
6118  #define DMA_HISR_FEIF5_Pos       (6U)
6119  #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
6120  #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
6121  #define DMA_HISR_TCIF4_Pos       (5U)
6122  #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
6123  #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
6124  #define DMA_HISR_HTIF4_Pos       (4U)
6125  #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
6126  #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
6127  #define DMA_HISR_TEIF4_Pos       (3U)
6128  #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
6129  #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
6130  #define DMA_HISR_DMEIF4_Pos      (2U)
6131  #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
6132  #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
6133  #define DMA_HISR_FEIF4_Pos       (0U)
6134  #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
6135  #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
6136  
6137  /********************  Bits definition for DMA_LIFCR register  ****************/
6138  #define DMA_LIFCR_CTCIF3_Pos     (27U)
6139  #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
6140  #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
6141  #define DMA_LIFCR_CHTIF3_Pos     (26U)
6142  #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
6143  #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
6144  #define DMA_LIFCR_CTEIF3_Pos     (25U)
6145  #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
6146  #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
6147  #define DMA_LIFCR_CDMEIF3_Pos    (24U)
6148  #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
6149  #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
6150  #define DMA_LIFCR_CFEIF3_Pos     (22U)
6151  #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
6152  #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
6153  #define DMA_LIFCR_CTCIF2_Pos     (21U)
6154  #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
6155  #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
6156  #define DMA_LIFCR_CHTIF2_Pos     (20U)
6157  #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
6158  #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
6159  #define DMA_LIFCR_CTEIF2_Pos     (19U)
6160  #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
6161  #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
6162  #define DMA_LIFCR_CDMEIF2_Pos    (18U)
6163  #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
6164  #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
6165  #define DMA_LIFCR_CFEIF2_Pos     (16U)
6166  #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
6167  #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
6168  #define DMA_LIFCR_CTCIF1_Pos     (11U)
6169  #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
6170  #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
6171  #define DMA_LIFCR_CHTIF1_Pos     (10U)
6172  #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
6173  #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
6174  #define DMA_LIFCR_CTEIF1_Pos     (9U)
6175  #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
6176  #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
6177  #define DMA_LIFCR_CDMEIF1_Pos    (8U)
6178  #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
6179  #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
6180  #define DMA_LIFCR_CFEIF1_Pos     (6U)
6181  #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
6182  #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
6183  #define DMA_LIFCR_CTCIF0_Pos     (5U)
6184  #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
6185  #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
6186  #define DMA_LIFCR_CHTIF0_Pos     (4U)
6187  #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
6188  #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
6189  #define DMA_LIFCR_CTEIF0_Pos     (3U)
6190  #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
6191  #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
6192  #define DMA_LIFCR_CDMEIF0_Pos    (2U)
6193  #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
6194  #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
6195  #define DMA_LIFCR_CFEIF0_Pos     (0U)
6196  #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
6197  #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
6198  
6199  /********************  Bits definition for DMA_HIFCR  register  ****************/
6200  #define DMA_HIFCR_CTCIF7_Pos     (27U)
6201  #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
6202  #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
6203  #define DMA_HIFCR_CHTIF7_Pos     (26U)
6204  #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
6205  #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
6206  #define DMA_HIFCR_CTEIF7_Pos     (25U)
6207  #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
6208  #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
6209  #define DMA_HIFCR_CDMEIF7_Pos    (24U)
6210  #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
6211  #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
6212  #define DMA_HIFCR_CFEIF7_Pos     (22U)
6213  #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
6214  #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
6215  #define DMA_HIFCR_CTCIF6_Pos     (21U)
6216  #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
6217  #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
6218  #define DMA_HIFCR_CHTIF6_Pos     (20U)
6219  #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
6220  #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
6221  #define DMA_HIFCR_CTEIF6_Pos     (19U)
6222  #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
6223  #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
6224  #define DMA_HIFCR_CDMEIF6_Pos    (18U)
6225  #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
6226  #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
6227  #define DMA_HIFCR_CFEIF6_Pos     (16U)
6228  #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
6229  #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
6230  #define DMA_HIFCR_CTCIF5_Pos     (11U)
6231  #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
6232  #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
6233  #define DMA_HIFCR_CHTIF5_Pos     (10U)
6234  #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
6235  #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
6236  #define DMA_HIFCR_CTEIF5_Pos     (9U)
6237  #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
6238  #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
6239  #define DMA_HIFCR_CDMEIF5_Pos    (8U)
6240  #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
6241  #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
6242  #define DMA_HIFCR_CFEIF5_Pos     (6U)
6243  #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
6244  #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
6245  #define DMA_HIFCR_CTCIF4_Pos     (5U)
6246  #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
6247  #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
6248  #define DMA_HIFCR_CHTIF4_Pos     (4U)
6249  #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
6250  #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
6251  #define DMA_HIFCR_CTEIF4_Pos     (3U)
6252  #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
6253  #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
6254  #define DMA_HIFCR_CDMEIF4_Pos    (2U)
6255  #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
6256  #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
6257  #define DMA_HIFCR_CFEIF4_Pos     (0U)
6258  #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
6259  #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
6260  
6261  /******************  Bit definition for DMA_SxPAR register  ********************/
6262  #define DMA_SxPAR_PA_Pos         (0U)
6263  #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
6264  #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
6265  
6266  /******************  Bit definition for DMA_SxM0AR register  ********************/
6267  #define DMA_SxM0AR_M0A_Pos       (0U)
6268  #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
6269  #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
6270  
6271  /******************  Bit definition for DMA_SxM1AR register  ********************/
6272  #define DMA_SxM1AR_M1A_Pos       (0U)
6273  #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
6274  #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
6275  
6276  
6277  /******************************************************************************/
6278  /*                                                                            */
6279  /*                         AHB Master DMA2D Controller (DMA2D)                */
6280  /*                                                                            */
6281  /******************************************************************************/
6282  
6283  /********************  Bit definition for DMA2D_CR register  ******************/
6284  
6285  #define DMA2D_CR_START_Pos         (0U)
6286  #define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)                /*!< 0x00000001 */
6287  #define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
6288  #define DMA2D_CR_SUSP_Pos          (1U)
6289  #define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */
6290  #define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
6291  #define DMA2D_CR_ABORT_Pos         (2U)
6292  #define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */
6293  #define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
6294  #define DMA2D_CR_TEIE_Pos          (8U)
6295  #define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */
6296  #define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
6297  #define DMA2D_CR_TCIE_Pos          (9U)
6298  #define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */
6299  #define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
6300  #define DMA2D_CR_TWIE_Pos          (10U)
6301  #define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */
6302  #define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
6303  #define DMA2D_CR_CAEIE_Pos         (11U)
6304  #define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */
6305  #define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
6306  #define DMA2D_CR_CTCIE_Pos         (12U)
6307  #define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */
6308  #define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
6309  #define DMA2D_CR_CEIE_Pos          (13U)
6310  #define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */
6311  #define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
6312  #define DMA2D_CR_MODE_Pos          (16U)
6313  #define DMA2D_CR_MODE_Msk          (0x3UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */
6314  #define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */
6315  #define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
6316  #define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
6317  
6318  /********************  Bit definition for DMA2D_ISR register  *****************/
6319  
6320  #define DMA2D_ISR_TEIF_Pos         (0U)
6321  #define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */
6322  #define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
6323  #define DMA2D_ISR_TCIF_Pos         (1U)
6324  #define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */
6325  #define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
6326  #define DMA2D_ISR_TWIF_Pos         (2U)
6327  #define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */
6328  #define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
6329  #define DMA2D_ISR_CAEIF_Pos        (3U)
6330  #define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */
6331  #define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
6332  #define DMA2D_ISR_CTCIF_Pos        (4U)
6333  #define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */
6334  #define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
6335  #define DMA2D_ISR_CEIF_Pos         (5U)
6336  #define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */
6337  #define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
6338  
6339  /********************  Bit definition for DMA2D_IFCR register  ****************/
6340  
6341  #define DMA2D_IFCR_CTEIF_Pos       (0U)
6342  #define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */
6343  #define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
6344  #define DMA2D_IFCR_CTCIF_Pos       (1U)
6345  #define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */
6346  #define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
6347  #define DMA2D_IFCR_CTWIF_Pos       (2U)
6348  #define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */
6349  #define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
6350  #define DMA2D_IFCR_CAECIF_Pos      (3U)
6351  #define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */
6352  #define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
6353  #define DMA2D_IFCR_CCTCIF_Pos      (4U)
6354  #define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */
6355  #define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
6356  #define DMA2D_IFCR_CCEIF_Pos       (5U)
6357  #define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */
6358  #define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
6359  
6360  /* Legacy defines */
6361  #define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
6362  #define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
6363  #define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
6364  #define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
6365  #define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
6366  #define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
6367  
6368  /********************  Bit definition for DMA2D_FGMAR register  ***************/
6369  
6370  #define DMA2D_FGMAR_MA_Pos         (0U)
6371  #define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
6372  #define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
6373  
6374  /********************  Bit definition for DMA2D_FGOR register  ****************/
6375  
6376  #define DMA2D_FGOR_LO_Pos          (0U)
6377  #define DMA2D_FGOR_LO_Msk          (0x3FFFUL << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */
6378  #define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
6379  
6380  /********************  Bit definition for DMA2D_BGMAR register  ***************/
6381  
6382  #define DMA2D_BGMAR_MA_Pos         (0U)
6383  #define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
6384  #define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
6385  
6386  /********************  Bit definition for DMA2D_BGOR register  ****************/
6387  
6388  #define DMA2D_BGOR_LO_Pos          (0U)
6389  #define DMA2D_BGOR_LO_Msk          (0x3FFFUL << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */
6390  #define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
6391  
6392  /********************  Bit definition for DMA2D_FGPFCCR register  *************/
6393  
6394  #define DMA2D_FGPFCCR_CM_Pos       (0U)
6395  #define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */
6396  #define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
6397  #define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
6398  #define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
6399  #define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
6400  #define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
6401  #define DMA2D_FGPFCCR_CCM_Pos      (4U)
6402  #define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */
6403  #define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
6404  #define DMA2D_FGPFCCR_START_Pos    (5U)
6405  #define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */
6406  #define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
6407  #define DMA2D_FGPFCCR_CS_Pos       (8U)
6408  #define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
6409  #define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
6410  #define DMA2D_FGPFCCR_AM_Pos       (16U)
6411  #define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */
6412  #define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
6413  #define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
6414  #define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
6415  #define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
6416  #define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
6417  #define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
6418  
6419  /********************  Bit definition for DMA2D_FGCOLR register  **************/
6420  
6421  #define DMA2D_FGCOLR_BLUE_Pos      (0U)
6422  #define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */
6423  #define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
6424  #define DMA2D_FGCOLR_GREEN_Pos     (8U)
6425  #define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
6426  #define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
6427  #define DMA2D_FGCOLR_RED_Pos       (16U)
6428  #define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */
6429  #define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
6430  
6431  /********************  Bit definition for DMA2D_BGPFCCR register  *************/
6432  
6433  #define DMA2D_BGPFCCR_CM_Pos       (0U)
6434  #define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */
6435  #define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
6436  #define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
6437  #define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
6438  #define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
6439  #define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */
6440  #define DMA2D_BGPFCCR_CCM_Pos      (4U)
6441  #define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */
6442  #define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
6443  #define DMA2D_BGPFCCR_START_Pos    (5U)
6444  #define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */
6445  #define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
6446  #define DMA2D_BGPFCCR_CS_Pos       (8U)
6447  #define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
6448  #define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
6449  #define DMA2D_BGPFCCR_AM_Pos       (16U)
6450  #define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */
6451  #define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
6452  #define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
6453  #define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
6454  #define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
6455  #define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
6456  #define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
6457  
6458  /********************  Bit definition for DMA2D_BGCOLR register  **************/
6459  
6460  #define DMA2D_BGCOLR_BLUE_Pos      (0U)
6461  #define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */
6462  #define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
6463  #define DMA2D_BGCOLR_GREEN_Pos     (8U)
6464  #define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
6465  #define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
6466  #define DMA2D_BGCOLR_RED_Pos       (16U)
6467  #define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */
6468  #define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
6469  
6470  /********************  Bit definition for DMA2D_FGCMAR register  **************/
6471  
6472  #define DMA2D_FGCMAR_MA_Pos        (0U)
6473  #define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
6474  #define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
6475  
6476  /********************  Bit definition for DMA2D_BGCMAR register  **************/
6477  
6478  #define DMA2D_BGCMAR_MA_Pos        (0U)
6479  #define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
6480  #define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
6481  
6482  /********************  Bit definition for DMA2D_OPFCCR register  **************/
6483  
6484  #define DMA2D_OPFCCR_CM_Pos        (0U)
6485  #define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */
6486  #define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
6487  #define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */
6488  #define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */
6489  #define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */
6490  
6491  /********************  Bit definition for DMA2D_OCOLR register  ***************/
6492  
6493  /*!<Mode_ARGB8888/RGB888 */
6494  
6495  #define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */
6496  #define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */
6497  #define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */
6498  #define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */
6499  
6500  /*!<Mode_RGB565 */
6501  #define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */
6502  #define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */
6503  #define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */
6504  
6505  /*!<Mode_ARGB1555 */
6506  #define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */
6507  #define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */
6508  #define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */
6509  #define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */
6510  
6511  /*!<Mode_ARGB4444 */
6512  #define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */
6513  #define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */
6514  #define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */
6515  #define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */
6516  
6517  /********************  Bit definition for DMA2D_OMAR register  ****************/
6518  
6519  #define DMA2D_OMAR_MA_Pos          (0U)
6520  #define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */
6521  #define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
6522  
6523  /********************  Bit definition for DMA2D_OOR register  *****************/
6524  
6525  #define DMA2D_OOR_LO_Pos           (0U)
6526  #define DMA2D_OOR_LO_Msk           (0x3FFFUL << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */
6527  #define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
6528  
6529  /********************  Bit definition for DMA2D_NLR register  *****************/
6530  
6531  #define DMA2D_NLR_NL_Pos           (0U)
6532  #define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */
6533  #define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
6534  #define DMA2D_NLR_PL_Pos           (16U)
6535  #define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */
6536  #define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
6537  
6538  /********************  Bit definition for DMA2D_LWR register  *****************/
6539  
6540  #define DMA2D_LWR_LW_Pos           (0U)
6541  #define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */
6542  #define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
6543  
6544  /********************  Bit definition for DMA2D_AMTCR register  ***************/
6545  
6546  #define DMA2D_AMTCR_EN_Pos         (0U)
6547  #define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */
6548  #define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
6549  #define DMA2D_AMTCR_DT_Pos         (8U)
6550  #define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
6551  #define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
6552  
6553  /********************  Bit definition for DMA2D_FGCLUT register  **************/
6554  
6555  /********************  Bit definition for DMA2D_BGCLUT register  **************/
6556  
6557  
6558  /******************************************************************************/
6559  /*                                                                            */
6560  /*                    External Interrupt/Event Controller                     */
6561  /*                                                                            */
6562  /******************************************************************************/
6563  /*******************  Bit definition for EXTI_IMR register  *******************/
6564  #define EXTI_IMR_MR0_Pos          (0U)
6565  #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
6566  #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
6567  #define EXTI_IMR_MR1_Pos          (1U)
6568  #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
6569  #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
6570  #define EXTI_IMR_MR2_Pos          (2U)
6571  #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
6572  #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
6573  #define EXTI_IMR_MR3_Pos          (3U)
6574  #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
6575  #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
6576  #define EXTI_IMR_MR4_Pos          (4U)
6577  #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
6578  #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
6579  #define EXTI_IMR_MR5_Pos          (5U)
6580  #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
6581  #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
6582  #define EXTI_IMR_MR6_Pos          (6U)
6583  #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
6584  #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
6585  #define EXTI_IMR_MR7_Pos          (7U)
6586  #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
6587  #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
6588  #define EXTI_IMR_MR8_Pos          (8U)
6589  #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
6590  #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
6591  #define EXTI_IMR_MR9_Pos          (9U)
6592  #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
6593  #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
6594  #define EXTI_IMR_MR10_Pos         (10U)
6595  #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
6596  #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
6597  #define EXTI_IMR_MR11_Pos         (11U)
6598  #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
6599  #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
6600  #define EXTI_IMR_MR12_Pos         (12U)
6601  #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
6602  #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
6603  #define EXTI_IMR_MR13_Pos         (13U)
6604  #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
6605  #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
6606  #define EXTI_IMR_MR14_Pos         (14U)
6607  #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
6608  #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
6609  #define EXTI_IMR_MR15_Pos         (15U)
6610  #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
6611  #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
6612  #define EXTI_IMR_MR16_Pos         (16U)
6613  #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
6614  #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
6615  #define EXTI_IMR_MR17_Pos         (17U)
6616  #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
6617  #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
6618  #define EXTI_IMR_MR18_Pos         (18U)
6619  #define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
6620  #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
6621  #define EXTI_IMR_MR19_Pos         (19U)
6622  #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
6623  #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
6624  #define EXTI_IMR_MR20_Pos         (20U)
6625  #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
6626  #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
6627  #define EXTI_IMR_MR21_Pos         (21U)
6628  #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
6629  #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
6630  #define EXTI_IMR_MR22_Pos         (22U)
6631  #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
6632  #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
6633  
6634  /* Reference Defines */
6635  #define  EXTI_IMR_IM0                        EXTI_IMR_MR0
6636  #define  EXTI_IMR_IM1                        EXTI_IMR_MR1
6637  #define  EXTI_IMR_IM2                        EXTI_IMR_MR2
6638  #define  EXTI_IMR_IM3                        EXTI_IMR_MR3
6639  #define  EXTI_IMR_IM4                        EXTI_IMR_MR4
6640  #define  EXTI_IMR_IM5                        EXTI_IMR_MR5
6641  #define  EXTI_IMR_IM6                        EXTI_IMR_MR6
6642  #define  EXTI_IMR_IM7                        EXTI_IMR_MR7
6643  #define  EXTI_IMR_IM8                        EXTI_IMR_MR8
6644  #define  EXTI_IMR_IM9                        EXTI_IMR_MR9
6645  #define  EXTI_IMR_IM10                       EXTI_IMR_MR10
6646  #define  EXTI_IMR_IM11                       EXTI_IMR_MR11
6647  #define  EXTI_IMR_IM12                       EXTI_IMR_MR12
6648  #define  EXTI_IMR_IM13                       EXTI_IMR_MR13
6649  #define  EXTI_IMR_IM14                       EXTI_IMR_MR14
6650  #define  EXTI_IMR_IM15                       EXTI_IMR_MR15
6651  #define  EXTI_IMR_IM16                       EXTI_IMR_MR16
6652  #define  EXTI_IMR_IM17                       EXTI_IMR_MR17
6653  #define  EXTI_IMR_IM18                       EXTI_IMR_MR18
6654  #define  EXTI_IMR_IM19                       EXTI_IMR_MR19
6655  #define  EXTI_IMR_IM20                       EXTI_IMR_MR20
6656  #define  EXTI_IMR_IM21                       EXTI_IMR_MR21
6657  #define  EXTI_IMR_IM22                       EXTI_IMR_MR22
6658  #define EXTI_IMR_IM_Pos           (0U)
6659  #define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
6660  #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
6661  
6662  /*******************  Bit definition for EXTI_EMR register  *******************/
6663  #define EXTI_EMR_MR0_Pos          (0U)
6664  #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
6665  #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
6666  #define EXTI_EMR_MR1_Pos          (1U)
6667  #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
6668  #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
6669  #define EXTI_EMR_MR2_Pos          (2U)
6670  #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
6671  #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
6672  #define EXTI_EMR_MR3_Pos          (3U)
6673  #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
6674  #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
6675  #define EXTI_EMR_MR4_Pos          (4U)
6676  #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
6677  #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
6678  #define EXTI_EMR_MR5_Pos          (5U)
6679  #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
6680  #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
6681  #define EXTI_EMR_MR6_Pos          (6U)
6682  #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
6683  #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
6684  #define EXTI_EMR_MR7_Pos          (7U)
6685  #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
6686  #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
6687  #define EXTI_EMR_MR8_Pos          (8U)
6688  #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
6689  #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
6690  #define EXTI_EMR_MR9_Pos          (9U)
6691  #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
6692  #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
6693  #define EXTI_EMR_MR10_Pos         (10U)
6694  #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
6695  #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
6696  #define EXTI_EMR_MR11_Pos         (11U)
6697  #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
6698  #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
6699  #define EXTI_EMR_MR12_Pos         (12U)
6700  #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
6701  #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
6702  #define EXTI_EMR_MR13_Pos         (13U)
6703  #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
6704  #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
6705  #define EXTI_EMR_MR14_Pos         (14U)
6706  #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
6707  #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
6708  #define EXTI_EMR_MR15_Pos         (15U)
6709  #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
6710  #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
6711  #define EXTI_EMR_MR16_Pos         (16U)
6712  #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
6713  #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
6714  #define EXTI_EMR_MR17_Pos         (17U)
6715  #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
6716  #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
6717  #define EXTI_EMR_MR18_Pos         (18U)
6718  #define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
6719  #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
6720  #define EXTI_EMR_MR19_Pos         (19U)
6721  #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
6722  #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
6723  #define EXTI_EMR_MR20_Pos         (20U)
6724  #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
6725  #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
6726  #define EXTI_EMR_MR21_Pos         (21U)
6727  #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
6728  #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
6729  #define EXTI_EMR_MR22_Pos         (22U)
6730  #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
6731  #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
6732  
6733  /* Reference Defines */
6734  #define  EXTI_EMR_EM0                        EXTI_EMR_MR0
6735  #define  EXTI_EMR_EM1                        EXTI_EMR_MR1
6736  #define  EXTI_EMR_EM2                        EXTI_EMR_MR2
6737  #define  EXTI_EMR_EM3                        EXTI_EMR_MR3
6738  #define  EXTI_EMR_EM4                        EXTI_EMR_MR4
6739  #define  EXTI_EMR_EM5                        EXTI_EMR_MR5
6740  #define  EXTI_EMR_EM6                        EXTI_EMR_MR6
6741  #define  EXTI_EMR_EM7                        EXTI_EMR_MR7
6742  #define  EXTI_EMR_EM8                        EXTI_EMR_MR8
6743  #define  EXTI_EMR_EM9                        EXTI_EMR_MR9
6744  #define  EXTI_EMR_EM10                       EXTI_EMR_MR10
6745  #define  EXTI_EMR_EM11                       EXTI_EMR_MR11
6746  #define  EXTI_EMR_EM12                       EXTI_EMR_MR12
6747  #define  EXTI_EMR_EM13                       EXTI_EMR_MR13
6748  #define  EXTI_EMR_EM14                       EXTI_EMR_MR14
6749  #define  EXTI_EMR_EM15                       EXTI_EMR_MR15
6750  #define  EXTI_EMR_EM16                       EXTI_EMR_MR16
6751  #define  EXTI_EMR_EM17                       EXTI_EMR_MR17
6752  #define  EXTI_EMR_EM18                       EXTI_EMR_MR18
6753  #define  EXTI_EMR_EM19                       EXTI_EMR_MR19
6754  #define  EXTI_EMR_EM20                       EXTI_EMR_MR20
6755  #define  EXTI_EMR_EM21                       EXTI_EMR_MR21
6756  #define  EXTI_EMR_EM22                       EXTI_EMR_MR22
6757  
6758  /******************  Bit definition for EXTI_RTSR register  *******************/
6759  #define EXTI_RTSR_TR0_Pos         (0U)
6760  #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
6761  #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
6762  #define EXTI_RTSR_TR1_Pos         (1U)
6763  #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
6764  #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
6765  #define EXTI_RTSR_TR2_Pos         (2U)
6766  #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
6767  #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
6768  #define EXTI_RTSR_TR3_Pos         (3U)
6769  #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
6770  #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
6771  #define EXTI_RTSR_TR4_Pos         (4U)
6772  #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
6773  #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
6774  #define EXTI_RTSR_TR5_Pos         (5U)
6775  #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
6776  #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
6777  #define EXTI_RTSR_TR6_Pos         (6U)
6778  #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
6779  #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
6780  #define EXTI_RTSR_TR7_Pos         (7U)
6781  #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
6782  #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
6783  #define EXTI_RTSR_TR8_Pos         (8U)
6784  #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
6785  #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
6786  #define EXTI_RTSR_TR9_Pos         (9U)
6787  #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
6788  #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
6789  #define EXTI_RTSR_TR10_Pos        (10U)
6790  #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
6791  #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
6792  #define EXTI_RTSR_TR11_Pos        (11U)
6793  #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
6794  #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
6795  #define EXTI_RTSR_TR12_Pos        (12U)
6796  #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
6797  #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
6798  #define EXTI_RTSR_TR13_Pos        (13U)
6799  #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
6800  #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
6801  #define EXTI_RTSR_TR14_Pos        (14U)
6802  #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
6803  #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
6804  #define EXTI_RTSR_TR15_Pos        (15U)
6805  #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
6806  #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
6807  #define EXTI_RTSR_TR16_Pos        (16U)
6808  #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
6809  #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
6810  #define EXTI_RTSR_TR17_Pos        (17U)
6811  #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
6812  #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
6813  #define EXTI_RTSR_TR18_Pos        (18U)
6814  #define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
6815  #define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
6816  #define EXTI_RTSR_TR19_Pos        (19U)
6817  #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
6818  #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
6819  #define EXTI_RTSR_TR20_Pos        (20U)
6820  #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
6821  #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
6822  #define EXTI_RTSR_TR21_Pos        (21U)
6823  #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
6824  #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
6825  #define EXTI_RTSR_TR22_Pos        (22U)
6826  #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
6827  #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
6828  
6829  /******************  Bit definition for EXTI_FTSR register  *******************/
6830  #define EXTI_FTSR_TR0_Pos         (0U)
6831  #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
6832  #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
6833  #define EXTI_FTSR_TR1_Pos         (1U)
6834  #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
6835  #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
6836  #define EXTI_FTSR_TR2_Pos         (2U)
6837  #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
6838  #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
6839  #define EXTI_FTSR_TR3_Pos         (3U)
6840  #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
6841  #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
6842  #define EXTI_FTSR_TR4_Pos         (4U)
6843  #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
6844  #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
6845  #define EXTI_FTSR_TR5_Pos         (5U)
6846  #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
6847  #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
6848  #define EXTI_FTSR_TR6_Pos         (6U)
6849  #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
6850  #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
6851  #define EXTI_FTSR_TR7_Pos         (7U)
6852  #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
6853  #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
6854  #define EXTI_FTSR_TR8_Pos         (8U)
6855  #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
6856  #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
6857  #define EXTI_FTSR_TR9_Pos         (9U)
6858  #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
6859  #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
6860  #define EXTI_FTSR_TR10_Pos        (10U)
6861  #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
6862  #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
6863  #define EXTI_FTSR_TR11_Pos        (11U)
6864  #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
6865  #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
6866  #define EXTI_FTSR_TR12_Pos        (12U)
6867  #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
6868  #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
6869  #define EXTI_FTSR_TR13_Pos        (13U)
6870  #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
6871  #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
6872  #define EXTI_FTSR_TR14_Pos        (14U)
6873  #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
6874  #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
6875  #define EXTI_FTSR_TR15_Pos        (15U)
6876  #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
6877  #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
6878  #define EXTI_FTSR_TR16_Pos        (16U)
6879  #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
6880  #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
6881  #define EXTI_FTSR_TR17_Pos        (17U)
6882  #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
6883  #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
6884  #define EXTI_FTSR_TR18_Pos        (18U)
6885  #define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
6886  #define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
6887  #define EXTI_FTSR_TR19_Pos        (19U)
6888  #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
6889  #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
6890  #define EXTI_FTSR_TR20_Pos        (20U)
6891  #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
6892  #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
6893  #define EXTI_FTSR_TR21_Pos        (21U)
6894  #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
6895  #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
6896  #define EXTI_FTSR_TR22_Pos        (22U)
6897  #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
6898  #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
6899  
6900  /******************  Bit definition for EXTI_SWIER register  ******************/
6901  #define EXTI_SWIER_SWIER0_Pos     (0U)
6902  #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
6903  #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
6904  #define EXTI_SWIER_SWIER1_Pos     (1U)
6905  #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
6906  #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
6907  #define EXTI_SWIER_SWIER2_Pos     (2U)
6908  #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
6909  #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
6910  #define EXTI_SWIER_SWIER3_Pos     (3U)
6911  #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
6912  #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
6913  #define EXTI_SWIER_SWIER4_Pos     (4U)
6914  #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
6915  #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
6916  #define EXTI_SWIER_SWIER5_Pos     (5U)
6917  #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
6918  #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
6919  #define EXTI_SWIER_SWIER6_Pos     (6U)
6920  #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
6921  #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
6922  #define EXTI_SWIER_SWIER7_Pos     (7U)
6923  #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
6924  #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
6925  #define EXTI_SWIER_SWIER8_Pos     (8U)
6926  #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
6927  #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
6928  #define EXTI_SWIER_SWIER9_Pos     (9U)
6929  #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
6930  #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
6931  #define EXTI_SWIER_SWIER10_Pos    (10U)
6932  #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
6933  #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
6934  #define EXTI_SWIER_SWIER11_Pos    (11U)
6935  #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
6936  #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
6937  #define EXTI_SWIER_SWIER12_Pos    (12U)
6938  #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
6939  #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
6940  #define EXTI_SWIER_SWIER13_Pos    (13U)
6941  #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
6942  #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
6943  #define EXTI_SWIER_SWIER14_Pos    (14U)
6944  #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
6945  #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
6946  #define EXTI_SWIER_SWIER15_Pos    (15U)
6947  #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
6948  #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
6949  #define EXTI_SWIER_SWIER16_Pos    (16U)
6950  #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
6951  #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
6952  #define EXTI_SWIER_SWIER17_Pos    (17U)
6953  #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
6954  #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
6955  #define EXTI_SWIER_SWIER18_Pos    (18U)
6956  #define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
6957  #define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
6958  #define EXTI_SWIER_SWIER19_Pos    (19U)
6959  #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
6960  #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
6961  #define EXTI_SWIER_SWIER20_Pos    (20U)
6962  #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
6963  #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
6964  #define EXTI_SWIER_SWIER21_Pos    (21U)
6965  #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
6966  #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
6967  #define EXTI_SWIER_SWIER22_Pos    (22U)
6968  #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
6969  #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
6970  
6971  /*******************  Bit definition for EXTI_PR register  ********************/
6972  #define EXTI_PR_PR0_Pos           (0U)
6973  #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
6974  #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
6975  #define EXTI_PR_PR1_Pos           (1U)
6976  #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
6977  #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
6978  #define EXTI_PR_PR2_Pos           (2U)
6979  #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
6980  #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
6981  #define EXTI_PR_PR3_Pos           (3U)
6982  #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
6983  #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
6984  #define EXTI_PR_PR4_Pos           (4U)
6985  #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
6986  #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
6987  #define EXTI_PR_PR5_Pos           (5U)
6988  #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
6989  #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
6990  #define EXTI_PR_PR6_Pos           (6U)
6991  #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
6992  #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
6993  #define EXTI_PR_PR7_Pos           (7U)
6994  #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
6995  #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
6996  #define EXTI_PR_PR8_Pos           (8U)
6997  #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
6998  #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
6999  #define EXTI_PR_PR9_Pos           (9U)
7000  #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
7001  #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
7002  #define EXTI_PR_PR10_Pos          (10U)
7003  #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
7004  #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
7005  #define EXTI_PR_PR11_Pos          (11U)
7006  #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
7007  #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
7008  #define EXTI_PR_PR12_Pos          (12U)
7009  #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
7010  #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
7011  #define EXTI_PR_PR13_Pos          (13U)
7012  #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
7013  #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
7014  #define EXTI_PR_PR14_Pos          (14U)
7015  #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
7016  #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
7017  #define EXTI_PR_PR15_Pos          (15U)
7018  #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
7019  #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
7020  #define EXTI_PR_PR16_Pos          (16U)
7021  #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
7022  #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
7023  #define EXTI_PR_PR17_Pos          (17U)
7024  #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
7025  #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
7026  #define EXTI_PR_PR18_Pos          (18U)
7027  #define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
7028  #define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
7029  #define EXTI_PR_PR19_Pos          (19U)
7030  #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
7031  #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
7032  #define EXTI_PR_PR20_Pos          (20U)
7033  #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
7034  #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
7035  #define EXTI_PR_PR21_Pos          (21U)
7036  #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
7037  #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
7038  #define EXTI_PR_PR22_Pos          (22U)
7039  #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
7040  #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
7041  
7042  /******************************************************************************/
7043  /*                                                                            */
7044  /*                                    FLASH                                   */
7045  /*                                                                            */
7046  /******************************************************************************/
7047  /*******************  Bits definition for FLASH_ACR register  *****************/
7048  #define FLASH_ACR_LATENCY_Pos          (0U)
7049  #define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */
7050  #define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
7051  #define FLASH_ACR_LATENCY_0WS          0x00000000U
7052  #define FLASH_ACR_LATENCY_1WS          0x00000001U
7053  #define FLASH_ACR_LATENCY_2WS          0x00000002U
7054  #define FLASH_ACR_LATENCY_3WS          0x00000003U
7055  #define FLASH_ACR_LATENCY_4WS          0x00000004U
7056  #define FLASH_ACR_LATENCY_5WS          0x00000005U
7057  #define FLASH_ACR_LATENCY_6WS          0x00000006U
7058  #define FLASH_ACR_LATENCY_7WS          0x00000007U
7059  
7060  #define FLASH_ACR_LATENCY_8WS          0x00000008U
7061  #define FLASH_ACR_LATENCY_9WS          0x00000009U
7062  #define FLASH_ACR_LATENCY_10WS         0x0000000AU
7063  #define FLASH_ACR_LATENCY_11WS         0x0000000BU
7064  #define FLASH_ACR_LATENCY_12WS         0x0000000CU
7065  #define FLASH_ACR_LATENCY_13WS         0x0000000DU
7066  #define FLASH_ACR_LATENCY_14WS         0x0000000EU
7067  #define FLASH_ACR_LATENCY_15WS         0x0000000FU
7068  #define FLASH_ACR_PRFTEN_Pos           (8U)
7069  #define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
7070  #define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk
7071  #define FLASH_ACR_ICEN_Pos             (9U)
7072  #define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
7073  #define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk
7074  #define FLASH_ACR_DCEN_Pos             (10U)
7075  #define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
7076  #define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk
7077  #define FLASH_ACR_ICRST_Pos            (11U)
7078  #define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
7079  #define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk
7080  #define FLASH_ACR_DCRST_Pos            (12U)
7081  #define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
7082  #define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk
7083  #define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)
7084  #define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
7085  #define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk
7086  #define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)
7087  #define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
7088  #define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk
7089  
7090  /*******************  Bits definition for FLASH_SR register  ******************/
7091  #define FLASH_SR_EOP_Pos               (0U)
7092  #define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
7093  #define FLASH_SR_EOP                   FLASH_SR_EOP_Msk
7094  #define FLASH_SR_SOP_Pos               (1U)
7095  #define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
7096  #define FLASH_SR_SOP                   FLASH_SR_SOP_Msk
7097  #define FLASH_SR_WRPERR_Pos            (4U)
7098  #define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
7099  #define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk
7100  #define FLASH_SR_PGAERR_Pos            (5U)
7101  #define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
7102  #define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk
7103  #define FLASH_SR_PGPERR_Pos            (6U)
7104  #define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
7105  #define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk
7106  #define FLASH_SR_PGSERR_Pos            (7U)
7107  #define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
7108  #define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk
7109  #define FLASH_SR_RDERR_Pos            (8U)
7110  #define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */
7111  #define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk
7112  #define FLASH_SR_BSY_Pos               (16U)
7113  #define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
7114  #define FLASH_SR_BSY                   FLASH_SR_BSY_Msk
7115  
7116  /*******************  Bits definition for FLASH_CR register  ******************/
7117  #define FLASH_CR_PG_Pos                (0U)
7118  #define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
7119  #define FLASH_CR_PG                    FLASH_CR_PG_Msk
7120  #define FLASH_CR_SER_Pos               (1U)
7121  #define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
7122  #define FLASH_CR_SER                   FLASH_CR_SER_Msk
7123  #define FLASH_CR_MER_Pos               (2U)
7124  #define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
7125  #define FLASH_CR_MER                   FLASH_CR_MER_Msk
7126  #define FLASH_CR_MER1                        FLASH_CR_MER
7127  #define FLASH_CR_SNB_Pos               (3U)
7128  #define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
7129  #define FLASH_CR_SNB                   FLASH_CR_SNB_Msk
7130  #define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
7131  #define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
7132  #define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
7133  #define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
7134  #define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
7135  #define FLASH_CR_PSIZE_Pos             (8U)
7136  #define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
7137  #define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk
7138  #define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
7139  #define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
7140  #define FLASH_CR_MER2_Pos              (15U)
7141  #define FLASH_CR_MER2_Msk              (0x1UL << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */
7142  #define FLASH_CR_MER2                  FLASH_CR_MER2_Msk
7143  #define FLASH_CR_STRT_Pos              (16U)
7144  #define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
7145  #define FLASH_CR_STRT                  FLASH_CR_STRT_Msk
7146  #define FLASH_CR_EOPIE_Pos             (24U)
7147  #define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
7148  #define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk
7149  #define FLASH_CR_LOCK_Pos              (31U)
7150  #define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
7151  #define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk
7152  
7153  /*******************  Bits definition for FLASH_OPTCR register  ***************/
7154  #define FLASH_OPTCR_OPTLOCK_Pos        (0U)
7155  #define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
7156  #define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk
7157  #define FLASH_OPTCR_OPTSTRT_Pos        (1U)
7158  #define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
7159  #define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk
7160  
7161  #define FLASH_OPTCR_BOR_LEV_0          0x00000004U
7162  #define FLASH_OPTCR_BOR_LEV_1          0x00000008U
7163  #define FLASH_OPTCR_BOR_LEV_Pos        (2U)
7164  #define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
7165  #define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk
7166  #define FLASH_OPTCR_BFB2_Pos           (4U)
7167  #define FLASH_OPTCR_BFB2_Msk           (0x1UL << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */
7168  #define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk
7169  #define FLASH_OPTCR_WDG_SW_Pos         (5U)
7170  #define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
7171  #define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk
7172  #define FLASH_OPTCR_nRST_STOP_Pos      (6U)
7173  #define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
7174  #define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk
7175  #define FLASH_OPTCR_nRST_STDBY_Pos     (7U)
7176  #define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
7177  #define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk
7178  #define FLASH_OPTCR_RDP_Pos            (8U)
7179  #define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
7180  #define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk
7181  #define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
7182  #define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
7183  #define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
7184  #define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
7185  #define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
7186  #define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
7187  #define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
7188  #define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
7189  #define FLASH_OPTCR_nWRP_Pos           (16U)
7190  #define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
7191  #define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk
7192  #define FLASH_OPTCR_nWRP_0             0x00010000U
7193  #define FLASH_OPTCR_nWRP_1             0x00020000U
7194  #define FLASH_OPTCR_nWRP_2             0x00040000U
7195  #define FLASH_OPTCR_nWRP_3             0x00080000U
7196  #define FLASH_OPTCR_nWRP_4             0x00100000U
7197  #define FLASH_OPTCR_nWRP_5             0x00200000U
7198  #define FLASH_OPTCR_nWRP_6             0x00400000U
7199  #define FLASH_OPTCR_nWRP_7             0x00800000U
7200  #define FLASH_OPTCR_nWRP_8             0x01000000U
7201  #define FLASH_OPTCR_nWRP_9             0x02000000U
7202  #define FLASH_OPTCR_nWRP_10            0x04000000U
7203  #define FLASH_OPTCR_nWRP_11            0x08000000U
7204  #define FLASH_OPTCR_DB1M_Pos           (30U)
7205  #define FLASH_OPTCR_DB1M_Msk           (0x1UL << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */
7206  #define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk
7207  #define FLASH_OPTCR_SPRMOD_Pos         (31U)
7208  #define FLASH_OPTCR_SPRMOD_Msk         (0x1UL << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */
7209  #define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk
7210  
7211  /******************  Bits definition for FLASH_OPTCR1 register  ***************/
7212  #define FLASH_OPTCR1_nWRP_Pos          (16U)
7213  #define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
7214  #define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk
7215  #define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
7216  #define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
7217  #define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
7218  #define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
7219  #define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
7220  #define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
7221  #define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
7222  #define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
7223  #define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
7224  #define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
7225  #define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
7226  #define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
7227  
7228  /******************************************************************************/
7229  /*                                                                            */
7230  /*                          Flexible Memory Controller                        */
7231  /*                                                                            */
7232  /******************************************************************************/
7233  /******************  Bit definition for FMC_BCR1 register  *******************/
7234  #define FMC_BCR1_MBKEN_Pos          (0U)
7235  #define FMC_BCR1_MBKEN_Msk          (0x1UL << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */
7236  #define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7237  #define FMC_BCR1_MUXEN_Pos          (1U)
7238  #define FMC_BCR1_MUXEN_Msk          (0x1UL << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */
7239  #define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7240  
7241  #define FMC_BCR1_MTYP_Pos           (2U)
7242  #define FMC_BCR1_MTYP_Msk           (0x3UL << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */
7243  #define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7244  #define FMC_BCR1_MTYP_0             (0x1UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */
7245  #define FMC_BCR1_MTYP_1             (0x2UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */
7246  
7247  #define FMC_BCR1_MWID_Pos           (4U)
7248  #define FMC_BCR1_MWID_Msk           (0x3UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */
7249  #define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7250  #define FMC_BCR1_MWID_0             (0x1UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */
7251  #define FMC_BCR1_MWID_1             (0x2UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */
7252  
7253  #define FMC_BCR1_FACCEN_Pos         (6U)
7254  #define FMC_BCR1_FACCEN_Msk         (0x1UL << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */
7255  #define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */
7256  #define FMC_BCR1_BURSTEN_Pos        (8U)
7257  #define FMC_BCR1_BURSTEN_Msk        (0x1UL << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */
7258  #define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */
7259  #define FMC_BCR1_WAITPOL_Pos        (9U)
7260  #define FMC_BCR1_WAITPOL_Msk        (0x1UL << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */
7261  #define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7262  #define FMC_BCR1_WRAPMOD_Pos        (10U)
7263  #define FMC_BCR1_WRAPMOD_Msk        (0x1UL << FMC_BCR1_WRAPMOD_Pos)             /*!< 0x00000400 */
7264  #define FMC_BCR1_WRAPMOD            FMC_BCR1_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
7265  #define FMC_BCR1_WAITCFG_Pos        (11U)
7266  #define FMC_BCR1_WAITCFG_Msk        (0x1UL << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */
7267  #define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */
7268  #define FMC_BCR1_WREN_Pos           (12U)
7269  #define FMC_BCR1_WREN_Msk           (0x1UL << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */
7270  #define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */
7271  #define FMC_BCR1_WAITEN_Pos         (13U)
7272  #define FMC_BCR1_WAITEN_Msk         (0x1UL << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */
7273  #define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */
7274  #define FMC_BCR1_EXTMOD_Pos         (14U)
7275  #define FMC_BCR1_EXTMOD_Msk         (0x1UL << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */
7276  #define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */
7277  #define FMC_BCR1_ASYNCWAIT_Pos      (15U)
7278  #define FMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7279  #define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7280  #define FMC_BCR1_CPSIZE_Pos         (16U)
7281  #define FMC_BCR1_CPSIZE_Msk         (0x7UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */
7282  #define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */
7283  #define FMC_BCR1_CPSIZE_0           (0x1UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */
7284  #define FMC_BCR1_CPSIZE_1           (0x2UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */
7285  #define FMC_BCR1_CPSIZE_2           (0x4UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */
7286  #define FMC_BCR1_CBURSTRW_Pos       (19U)
7287  #define FMC_BCR1_CBURSTRW_Msk       (0x1UL << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */
7288  #define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */
7289  #define FMC_BCR1_CCLKEN_Pos         (20U)
7290  #define FMC_BCR1_CCLKEN_Msk         (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
7291  #define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */
7292  
7293  /******************  Bit definition for FMC_BCR2 register  *******************/
7294  #define FMC_BCR2_MBKEN_Pos          (0U)
7295  #define FMC_BCR2_MBKEN_Msk          (0x1UL << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */
7296  #define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7297  #define FMC_BCR2_MUXEN_Pos          (1U)
7298  #define FMC_BCR2_MUXEN_Msk          (0x1UL << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */
7299  #define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7300  
7301  #define FMC_BCR2_MTYP_Pos           (2U)
7302  #define FMC_BCR2_MTYP_Msk           (0x3UL << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */
7303  #define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7304  #define FMC_BCR2_MTYP_0             (0x1UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */
7305  #define FMC_BCR2_MTYP_1             (0x2UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */
7306  
7307  #define FMC_BCR2_MWID_Pos           (4U)
7308  #define FMC_BCR2_MWID_Msk           (0x3UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */
7309  #define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7310  #define FMC_BCR2_MWID_0             (0x1UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */
7311  #define FMC_BCR2_MWID_1             (0x2UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */
7312  
7313  #define FMC_BCR2_FACCEN_Pos         (6U)
7314  #define FMC_BCR2_FACCEN_Msk         (0x1UL << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */
7315  #define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */
7316  #define FMC_BCR2_BURSTEN_Pos        (8U)
7317  #define FMC_BCR2_BURSTEN_Msk        (0x1UL << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */
7318  #define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */
7319  #define FMC_BCR2_WAITPOL_Pos        (9U)
7320  #define FMC_BCR2_WAITPOL_Msk        (0x1UL << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */
7321  #define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7322  #define FMC_BCR2_WRAPMOD_Pos        (10U)
7323  #define FMC_BCR2_WRAPMOD_Msk        (0x1UL << FMC_BCR2_WRAPMOD_Pos)             /*!< 0x00000400 */
7324  #define FMC_BCR2_WRAPMOD            FMC_BCR2_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
7325  #define FMC_BCR2_WAITCFG_Pos        (11U)
7326  #define FMC_BCR2_WAITCFG_Msk        (0x1UL << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */
7327  #define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */
7328  #define FMC_BCR2_WREN_Pos           (12U)
7329  #define FMC_BCR2_WREN_Msk           (0x1UL << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */
7330  #define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */
7331  #define FMC_BCR2_WAITEN_Pos         (13U)
7332  #define FMC_BCR2_WAITEN_Msk         (0x1UL << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */
7333  #define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */
7334  #define FMC_BCR2_EXTMOD_Pos         (14U)
7335  #define FMC_BCR2_EXTMOD_Msk         (0x1UL << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */
7336  #define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */
7337  #define FMC_BCR2_ASYNCWAIT_Pos      (15U)
7338  #define FMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7339  #define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7340  #define FMC_BCR2_CPSIZE_Pos         (16U)
7341  #define FMC_BCR2_CPSIZE_Msk         (0x7UL << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00070000 */
7342  #define FMC_BCR2_CPSIZE             FMC_BCR2_CPSIZE_Msk                        /*!<CRAM page size */
7343  #define FMC_BCR2_CPSIZE_0           (0x1UL << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00010000 */
7344  #define FMC_BCR2_CPSIZE_1           (0x2UL << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00020000 */
7345  #define FMC_BCR2_CPSIZE_2           (0x4UL << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00040000 */
7346  #define FMC_BCR2_CBURSTRW_Pos       (19U)
7347  #define FMC_BCR2_CBURSTRW_Msk       (0x1UL << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */
7348  #define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */
7349  
7350  /******************  Bit definition for FMC_BCR3 register  *******************/
7351  #define FMC_BCR3_MBKEN_Pos          (0U)
7352  #define FMC_BCR3_MBKEN_Msk          (0x1UL << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */
7353  #define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7354  #define FMC_BCR3_MUXEN_Pos          (1U)
7355  #define FMC_BCR3_MUXEN_Msk          (0x1UL << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */
7356  #define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7357  
7358  #define FMC_BCR3_MTYP_Pos           (2U)
7359  #define FMC_BCR3_MTYP_Msk           (0x3UL << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */
7360  #define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7361  #define FMC_BCR3_MTYP_0             (0x1UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */
7362  #define FMC_BCR3_MTYP_1             (0x2UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */
7363  
7364  #define FMC_BCR3_MWID_Pos           (4U)
7365  #define FMC_BCR3_MWID_Msk           (0x3UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */
7366  #define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7367  #define FMC_BCR3_MWID_0             (0x1UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */
7368  #define FMC_BCR3_MWID_1             (0x2UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */
7369  
7370  #define FMC_BCR3_FACCEN_Pos         (6U)
7371  #define FMC_BCR3_FACCEN_Msk         (0x1UL << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */
7372  #define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */
7373  #define FMC_BCR3_BURSTEN_Pos        (8U)
7374  #define FMC_BCR3_BURSTEN_Msk        (0x1UL << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */
7375  #define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */
7376  #define FMC_BCR3_WAITPOL_Pos        (9U)
7377  #define FMC_BCR3_WAITPOL_Msk        (0x1UL << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */
7378  #define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7379  #define FMC_BCR3_WRAPMOD_Pos        (10U)
7380  #define FMC_BCR3_WRAPMOD_Msk        (0x1UL << FMC_BCR3_WRAPMOD_Pos)             /*!< 0x00000400 */
7381  #define FMC_BCR3_WRAPMOD            FMC_BCR3_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
7382  #define FMC_BCR3_WAITCFG_Pos        (11U)
7383  #define FMC_BCR3_WAITCFG_Msk        (0x1UL << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */
7384  #define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */
7385  #define FMC_BCR3_WREN_Pos           (12U)
7386  #define FMC_BCR3_WREN_Msk           (0x1UL << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */
7387  #define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */
7388  #define FMC_BCR3_WAITEN_Pos         (13U)
7389  #define FMC_BCR3_WAITEN_Msk         (0x1UL << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */
7390  #define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */
7391  #define FMC_BCR3_EXTMOD_Pos         (14U)
7392  #define FMC_BCR3_EXTMOD_Msk         (0x1UL << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */
7393  #define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */
7394  #define FMC_BCR3_ASYNCWAIT_Pos      (15U)
7395  #define FMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7396  #define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7397  #define FMC_BCR3_CPSIZE_Pos         (16U)
7398  #define FMC_BCR3_CPSIZE_Msk         (0x7UL << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00070000 */
7399  #define FMC_BCR3_CPSIZE             FMC_BCR3_CPSIZE_Msk                        /*!<CRAM page size */
7400  #define FMC_BCR3_CPSIZE_0           (0x1UL << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00010000 */
7401  #define FMC_BCR3_CPSIZE_1           (0x2UL << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00020000 */
7402  #define FMC_BCR3_CPSIZE_2           (0x4UL << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00040000 */
7403  #define FMC_BCR3_CBURSTRW_Pos       (19U)
7404  #define FMC_BCR3_CBURSTRW_Msk       (0x1UL << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */
7405  #define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */
7406  
7407  /******************  Bit definition for FMC_BCR4 register  *******************/
7408  #define FMC_BCR4_MBKEN_Pos          (0U)
7409  #define FMC_BCR4_MBKEN_Msk          (0x1UL << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */
7410  #define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7411  #define FMC_BCR4_MUXEN_Pos          (1U)
7412  #define FMC_BCR4_MUXEN_Msk          (0x1UL << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */
7413  #define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7414  
7415  #define FMC_BCR4_MTYP_Pos           (2U)
7416  #define FMC_BCR4_MTYP_Msk           (0x3UL << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */
7417  #define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7418  #define FMC_BCR4_MTYP_0             (0x1UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */
7419  #define FMC_BCR4_MTYP_1             (0x2UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */
7420  
7421  #define FMC_BCR4_MWID_Pos           (4U)
7422  #define FMC_BCR4_MWID_Msk           (0x3UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */
7423  #define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7424  #define FMC_BCR4_MWID_0             (0x1UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */
7425  #define FMC_BCR4_MWID_1             (0x2UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */
7426  
7427  #define FMC_BCR4_FACCEN_Pos         (6U)
7428  #define FMC_BCR4_FACCEN_Msk         (0x1UL << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */
7429  #define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */
7430  #define FMC_BCR4_BURSTEN_Pos        (8U)
7431  #define FMC_BCR4_BURSTEN_Msk        (0x1UL << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */
7432  #define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */
7433  #define FMC_BCR4_WAITPOL_Pos        (9U)
7434  #define FMC_BCR4_WAITPOL_Msk        (0x1UL << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */
7435  #define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7436  #define FMC_BCR4_WRAPMOD_Pos        (10U)
7437  #define FMC_BCR4_WRAPMOD_Msk        (0x1UL << FMC_BCR4_WRAPMOD_Pos)             /*!< 0x00000400 */
7438  #define FMC_BCR4_WRAPMOD            FMC_BCR4_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
7439  #define FMC_BCR4_WAITCFG_Pos        (11U)
7440  #define FMC_BCR4_WAITCFG_Msk        (0x1UL << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */
7441  #define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */
7442  #define FMC_BCR4_WREN_Pos           (12U)
7443  #define FMC_BCR4_WREN_Msk           (0x1UL << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */
7444  #define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */
7445  #define FMC_BCR4_WAITEN_Pos         (13U)
7446  #define FMC_BCR4_WAITEN_Msk         (0x1UL << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */
7447  #define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */
7448  #define FMC_BCR4_EXTMOD_Pos         (14U)
7449  #define FMC_BCR4_EXTMOD_Msk         (0x1UL << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */
7450  #define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */
7451  #define FMC_BCR4_ASYNCWAIT_Pos      (15U)
7452  #define FMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7453  #define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7454  #define FMC_BCR4_CPSIZE_Pos         (16U)
7455  #define FMC_BCR4_CPSIZE_Msk         (0x7UL << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00070000 */
7456  #define FMC_BCR4_CPSIZE             FMC_BCR4_CPSIZE_Msk                        /*!<CRAM page size */
7457  #define FMC_BCR4_CPSIZE_0           (0x1UL << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00010000 */
7458  #define FMC_BCR4_CPSIZE_1           (0x2UL << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00020000 */
7459  #define FMC_BCR4_CPSIZE_2           (0x4UL << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00040000 */
7460  #define FMC_BCR4_CBURSTRW_Pos       (19U)
7461  #define FMC_BCR4_CBURSTRW_Msk       (0x1UL << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */
7462  #define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */
7463  
7464  /******************  Bit definition for FMC_BTR1 register  ******************/
7465  #define FMC_BTR1_ADDSET_Pos         (0U)
7466  #define FMC_BTR1_ADDSET_Msk         (0xFUL << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */
7467  #define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7468  #define FMC_BTR1_ADDSET_0           (0x1UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */
7469  #define FMC_BTR1_ADDSET_1           (0x2UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */
7470  #define FMC_BTR1_ADDSET_2           (0x4UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */
7471  #define FMC_BTR1_ADDSET_3           (0x8UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */
7472  
7473  #define FMC_BTR1_ADDHLD_Pos         (4U)
7474  #define FMC_BTR1_ADDHLD_Msk         (0xFUL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
7475  #define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
7476  #define FMC_BTR1_ADDHLD_0           (0x1UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */
7477  #define FMC_BTR1_ADDHLD_1           (0x2UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */
7478  #define FMC_BTR1_ADDHLD_2           (0x4UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */
7479  #define FMC_BTR1_ADDHLD_3           (0x8UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */
7480  
7481  #define FMC_BTR1_DATAST_Pos         (8U)
7482  #define FMC_BTR1_DATAST_Msk         (0xFFUL << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */
7483  #define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7484  #define FMC_BTR1_DATAST_0           (0x01UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */
7485  #define FMC_BTR1_DATAST_1           (0x02UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */
7486  #define FMC_BTR1_DATAST_2           (0x04UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */
7487  #define FMC_BTR1_DATAST_3           (0x08UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */
7488  #define FMC_BTR1_DATAST_4           (0x10UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */
7489  #define FMC_BTR1_DATAST_5           (0x20UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */
7490  #define FMC_BTR1_DATAST_6           (0x40UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */
7491  #define FMC_BTR1_DATAST_7           (0x80UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */
7492  
7493  #define FMC_BTR1_BUSTURN_Pos        (16U)
7494  #define FMC_BTR1_BUSTURN_Msk        (0xFUL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
7495  #define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7496  #define FMC_BTR1_BUSTURN_0          (0x1UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */
7497  #define FMC_BTR1_BUSTURN_1          (0x2UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */
7498  #define FMC_BTR1_BUSTURN_2          (0x4UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */
7499  #define FMC_BTR1_BUSTURN_3          (0x8UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */
7500  
7501  #define FMC_BTR1_CLKDIV_Pos         (20U)
7502  #define FMC_BTR1_CLKDIV_Msk         (0xFUL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */
7503  #define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7504  #define FMC_BTR1_CLKDIV_0           (0x1UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */
7505  #define FMC_BTR1_CLKDIV_1           (0x2UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */
7506  #define FMC_BTR1_CLKDIV_2           (0x4UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */
7507  #define FMC_BTR1_CLKDIV_3           (0x8UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */
7508  
7509  #define FMC_BTR1_DATLAT_Pos         (24U)
7510  #define FMC_BTR1_DATLAT_Msk         (0xFUL << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */
7511  #define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7512  #define FMC_BTR1_DATLAT_0           (0x1UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */
7513  #define FMC_BTR1_DATLAT_1           (0x2UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */
7514  #define FMC_BTR1_DATLAT_2           (0x4UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */
7515  #define FMC_BTR1_DATLAT_3           (0x8UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */
7516  
7517  #define FMC_BTR1_ACCMOD_Pos         (28U)
7518  #define FMC_BTR1_ACCMOD_Msk         (0x3UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */
7519  #define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7520  #define FMC_BTR1_ACCMOD_0           (0x1UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */
7521  #define FMC_BTR1_ACCMOD_1           (0x2UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */
7522  
7523  /******************  Bit definition for FMC_BTR2 register  *******************/
7524  #define FMC_BTR2_ADDSET_Pos         (0U)
7525  #define FMC_BTR2_ADDSET_Msk         (0xFUL << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */
7526  #define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7527  #define FMC_BTR2_ADDSET_0           (0x1UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */
7528  #define FMC_BTR2_ADDSET_1           (0x2UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */
7529  #define FMC_BTR2_ADDSET_2           (0x4UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */
7530  #define FMC_BTR2_ADDSET_3           (0x8UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */
7531  
7532  #define FMC_BTR2_ADDHLD_Pos         (4U)
7533  #define FMC_BTR2_ADDHLD_Msk         (0xFUL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
7534  #define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7535  #define FMC_BTR2_ADDHLD_0           (0x1UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */
7536  #define FMC_BTR2_ADDHLD_1           (0x2UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */
7537  #define FMC_BTR2_ADDHLD_2           (0x4UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */
7538  #define FMC_BTR2_ADDHLD_3           (0x8UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */
7539  
7540  #define FMC_BTR2_DATAST_Pos         (8U)
7541  #define FMC_BTR2_DATAST_Msk         (0xFFUL << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */
7542  #define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7543  #define FMC_BTR2_DATAST_0           (0x01UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */
7544  #define FMC_BTR2_DATAST_1           (0x02UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */
7545  #define FMC_BTR2_DATAST_2           (0x04UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */
7546  #define FMC_BTR2_DATAST_3           (0x08UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */
7547  #define FMC_BTR2_DATAST_4           (0x10UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */
7548  #define FMC_BTR2_DATAST_5           (0x20UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */
7549  #define FMC_BTR2_DATAST_6           (0x40UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */
7550  #define FMC_BTR2_DATAST_7           (0x80UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */
7551  
7552  #define FMC_BTR2_BUSTURN_Pos        (16U)
7553  #define FMC_BTR2_BUSTURN_Msk        (0xFUL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */
7554  #define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7555  #define FMC_BTR2_BUSTURN_0          (0x1UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */
7556  #define FMC_BTR2_BUSTURN_1          (0x2UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */
7557  #define FMC_BTR2_BUSTURN_2          (0x4UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */
7558  #define FMC_BTR2_BUSTURN_3          (0x8UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */
7559  
7560  #define FMC_BTR2_CLKDIV_Pos         (20U)
7561  #define FMC_BTR2_CLKDIV_Msk         (0xFUL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */
7562  #define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7563  #define FMC_BTR2_CLKDIV_0           (0x1UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */
7564  #define FMC_BTR2_CLKDIV_1           (0x2UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */
7565  #define FMC_BTR2_CLKDIV_2           (0x4UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */
7566  #define FMC_BTR2_CLKDIV_3           (0x8UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */
7567  
7568  #define FMC_BTR2_DATLAT_Pos         (24U)
7569  #define FMC_BTR2_DATLAT_Msk         (0xFUL << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */
7570  #define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7571  #define FMC_BTR2_DATLAT_0           (0x1UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */
7572  #define FMC_BTR2_DATLAT_1           (0x2UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */
7573  #define FMC_BTR2_DATLAT_2           (0x4UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */
7574  #define FMC_BTR2_DATLAT_3           (0x8UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */
7575  
7576  #define FMC_BTR2_ACCMOD_Pos         (28U)
7577  #define FMC_BTR2_ACCMOD_Msk         (0x3UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */
7578  #define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7579  #define FMC_BTR2_ACCMOD_0           (0x1UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */
7580  #define FMC_BTR2_ACCMOD_1           (0x2UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */
7581  
7582  /*******************  Bit definition for FMC_BTR3 register  *******************/
7583  #define FMC_BTR3_ADDSET_Pos         (0U)
7584  #define FMC_BTR3_ADDSET_Msk         (0xFUL << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */
7585  #define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7586  #define FMC_BTR3_ADDSET_0           (0x1UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */
7587  #define FMC_BTR3_ADDSET_1           (0x2UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */
7588  #define FMC_BTR3_ADDSET_2           (0x4UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */
7589  #define FMC_BTR3_ADDSET_3           (0x8UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */
7590  
7591  #define FMC_BTR3_ADDHLD_Pos         (4U)
7592  #define FMC_BTR3_ADDHLD_Msk         (0xFUL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
7593  #define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7594  #define FMC_BTR3_ADDHLD_0           (0x1UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */
7595  #define FMC_BTR3_ADDHLD_1           (0x2UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */
7596  #define FMC_BTR3_ADDHLD_2           (0x4UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */
7597  #define FMC_BTR3_ADDHLD_3           (0x8UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */
7598  
7599  #define FMC_BTR3_DATAST_Pos         (8U)
7600  #define FMC_BTR3_DATAST_Msk         (0xFFUL << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */
7601  #define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7602  #define FMC_BTR3_DATAST_0           (0x01UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */
7603  #define FMC_BTR3_DATAST_1           (0x02UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */
7604  #define FMC_BTR3_DATAST_2           (0x04UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */
7605  #define FMC_BTR3_DATAST_3           (0x08UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */
7606  #define FMC_BTR3_DATAST_4           (0x10UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */
7607  #define FMC_BTR3_DATAST_5           (0x20UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */
7608  #define FMC_BTR3_DATAST_6           (0x40UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */
7609  #define FMC_BTR3_DATAST_7           (0x80UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */
7610  
7611  #define FMC_BTR3_BUSTURN_Pos        (16U)
7612  #define FMC_BTR3_BUSTURN_Msk        (0xFUL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */
7613  #define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7614  #define FMC_BTR3_BUSTURN_0          (0x1UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */
7615  #define FMC_BTR3_BUSTURN_1          (0x2UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */
7616  #define FMC_BTR3_BUSTURN_2          (0x4UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */
7617  #define FMC_BTR3_BUSTURN_3          (0x8UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */
7618  
7619  #define FMC_BTR3_CLKDIV_Pos         (20U)
7620  #define FMC_BTR3_CLKDIV_Msk         (0xFUL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */
7621  #define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7622  #define FMC_BTR3_CLKDIV_0           (0x1UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */
7623  #define FMC_BTR3_CLKDIV_1           (0x2UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */
7624  #define FMC_BTR3_CLKDIV_2           (0x4UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */
7625  #define FMC_BTR3_CLKDIV_3           (0x8UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */
7626  
7627  #define FMC_BTR3_DATLAT_Pos         (24U)
7628  #define FMC_BTR3_DATLAT_Msk         (0xFUL << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */
7629  #define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7630  #define FMC_BTR3_DATLAT_0           (0x1UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */
7631  #define FMC_BTR3_DATLAT_1           (0x2UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */
7632  #define FMC_BTR3_DATLAT_2           (0x4UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */
7633  #define FMC_BTR3_DATLAT_3           (0x8UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */
7634  
7635  #define FMC_BTR3_ACCMOD_Pos         (28U)
7636  #define FMC_BTR3_ACCMOD_Msk         (0x3UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */
7637  #define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7638  #define FMC_BTR3_ACCMOD_0           (0x1UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */
7639  #define FMC_BTR3_ACCMOD_1           (0x2UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */
7640  
7641  /******************  Bit definition for FMC_BTR4 register  *******************/
7642  #define FMC_BTR4_ADDSET_Pos         (0U)
7643  #define FMC_BTR4_ADDSET_Msk         (0xFUL << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */
7644  #define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7645  #define FMC_BTR4_ADDSET_0           (0x1UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */
7646  #define FMC_BTR4_ADDSET_1           (0x2UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */
7647  #define FMC_BTR4_ADDSET_2           (0x4UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */
7648  #define FMC_BTR4_ADDSET_3           (0x8UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */
7649  
7650  #define FMC_BTR4_ADDHLD_Pos         (4U)
7651  #define FMC_BTR4_ADDHLD_Msk         (0xFUL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
7652  #define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7653  #define FMC_BTR4_ADDHLD_0           (0x1UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */
7654  #define FMC_BTR4_ADDHLD_1           (0x2UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */
7655  #define FMC_BTR4_ADDHLD_2           (0x4UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */
7656  #define FMC_BTR4_ADDHLD_3           (0x8UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */
7657  
7658  #define FMC_BTR4_DATAST_Pos         (8U)
7659  #define FMC_BTR4_DATAST_Msk         (0xFFUL << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */
7660  #define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7661  #define FMC_BTR4_DATAST_0           (0x01UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */
7662  #define FMC_BTR4_DATAST_1           (0x02UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */
7663  #define FMC_BTR4_DATAST_2           (0x04UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */
7664  #define FMC_BTR4_DATAST_3           (0x08UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */
7665  #define FMC_BTR4_DATAST_4           (0x10UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */
7666  #define FMC_BTR4_DATAST_5           (0x20UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */
7667  #define FMC_BTR4_DATAST_6           (0x40UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */
7668  #define FMC_BTR4_DATAST_7           (0x80UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */
7669  
7670  #define FMC_BTR4_BUSTURN_Pos        (16U)
7671  #define FMC_BTR4_BUSTURN_Msk        (0xFUL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */
7672  #define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7673  #define FMC_BTR4_BUSTURN_0          (0x1UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */
7674  #define FMC_BTR4_BUSTURN_1          (0x2UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */
7675  #define FMC_BTR4_BUSTURN_2          (0x4UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */
7676  #define FMC_BTR4_BUSTURN_3          (0x8UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */
7677  
7678  #define FMC_BTR4_CLKDIV_Pos         (20U)
7679  #define FMC_BTR4_CLKDIV_Msk         (0xFUL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */
7680  #define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7681  #define FMC_BTR4_CLKDIV_0           (0x1UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */
7682  #define FMC_BTR4_CLKDIV_1           (0x2UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */
7683  #define FMC_BTR4_CLKDIV_2           (0x4UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */
7684  #define FMC_BTR4_CLKDIV_3           (0x8UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */
7685  
7686  #define FMC_BTR4_DATLAT_Pos         (24U)
7687  #define FMC_BTR4_DATLAT_Msk         (0xFUL << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */
7688  #define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7689  #define FMC_BTR4_DATLAT_0           (0x1UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */
7690  #define FMC_BTR4_DATLAT_1           (0x2UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */
7691  #define FMC_BTR4_DATLAT_2           (0x4UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */
7692  #define FMC_BTR4_DATLAT_3           (0x8UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */
7693  
7694  #define FMC_BTR4_ACCMOD_Pos         (28U)
7695  #define FMC_BTR4_ACCMOD_Msk         (0x3UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */
7696  #define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7697  #define FMC_BTR4_ACCMOD_0           (0x1UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */
7698  #define FMC_BTR4_ACCMOD_1           (0x2UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */
7699  
7700  /******************  Bit definition for FMC_BWTR1 register  ******************/
7701  #define FMC_BWTR1_ADDSET_Pos        (0U)
7702  #define FMC_BWTR1_ADDSET_Msk        (0xFUL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */
7703  #define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7704  #define FMC_BWTR1_ADDSET_0          (0x1UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */
7705  #define FMC_BWTR1_ADDSET_1          (0x2UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */
7706  #define FMC_BWTR1_ADDSET_2          (0x4UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */
7707  #define FMC_BWTR1_ADDSET_3          (0x8UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */
7708  
7709  #define FMC_BWTR1_ADDHLD_Pos        (4U)
7710  #define FMC_BWTR1_ADDHLD_Msk        (0xFUL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */
7711  #define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7712  #define FMC_BWTR1_ADDHLD_0          (0x1UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */
7713  #define FMC_BWTR1_ADDHLD_1          (0x2UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */
7714  #define FMC_BWTR1_ADDHLD_2          (0x4UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */
7715  #define FMC_BWTR1_ADDHLD_3          (0x8UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */
7716  
7717  #define FMC_BWTR1_DATAST_Pos        (8U)
7718  #define FMC_BWTR1_DATAST_Msk        (0xFFUL << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */
7719  #define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7720  #define FMC_BWTR1_DATAST_0          (0x01UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */
7721  #define FMC_BWTR1_DATAST_1          (0x02UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */
7722  #define FMC_BWTR1_DATAST_2          (0x04UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */
7723  #define FMC_BWTR1_DATAST_3          (0x08UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */
7724  #define FMC_BWTR1_DATAST_4          (0x10UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */
7725  #define FMC_BWTR1_DATAST_5          (0x20UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */
7726  #define FMC_BWTR1_DATAST_6          (0x40UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */
7727  #define FMC_BWTR1_DATAST_7          (0x80UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */
7728  
7729  #define FMC_BWTR1_BUSTURN_Pos       (16U)
7730  #define FMC_BWTR1_BUSTURN_Msk       (0xFUL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */
7731  #define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7732  #define FMC_BWTR1_BUSTURN_0         (0x1UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */
7733  #define FMC_BWTR1_BUSTURN_1         (0x2UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */
7734  #define FMC_BWTR1_BUSTURN_2         (0x4UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */
7735  #define FMC_BWTR1_BUSTURN_3         (0x8UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */
7736  
7737  #define FMC_BWTR1_ACCMOD_Pos        (28U)
7738  #define FMC_BWTR1_ACCMOD_Msk        (0x3UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */
7739  #define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7740  #define FMC_BWTR1_ACCMOD_0          (0x1UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */
7741  #define FMC_BWTR1_ACCMOD_1          (0x2UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */
7742  
7743  /******************  Bit definition for FMC_BWTR2 register  ******************/
7744  #define FMC_BWTR2_ADDSET_Pos        (0U)
7745  #define FMC_BWTR2_ADDSET_Msk        (0xFUL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */
7746  #define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7747  #define FMC_BWTR2_ADDSET_0          (0x1UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */
7748  #define FMC_BWTR2_ADDSET_1          (0x2UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */
7749  #define FMC_BWTR2_ADDSET_2          (0x4UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */
7750  #define FMC_BWTR2_ADDSET_3          (0x8UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */
7751  
7752  #define FMC_BWTR2_ADDHLD_Pos        (4U)
7753  #define FMC_BWTR2_ADDHLD_Msk        (0xFUL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */
7754  #define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7755  #define FMC_BWTR2_ADDHLD_0          (0x1UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */
7756  #define FMC_BWTR2_ADDHLD_1          (0x2UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */
7757  #define FMC_BWTR2_ADDHLD_2          (0x4UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */
7758  #define FMC_BWTR2_ADDHLD_3          (0x8UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */
7759  
7760  #define FMC_BWTR2_DATAST_Pos        (8U)
7761  #define FMC_BWTR2_DATAST_Msk        (0xFFUL << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */
7762  #define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7763  #define FMC_BWTR2_DATAST_0          (0x01UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */
7764  #define FMC_BWTR2_DATAST_1          (0x02UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */
7765  #define FMC_BWTR2_DATAST_2          (0x04UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */
7766  #define FMC_BWTR2_DATAST_3          (0x08UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */
7767  #define FMC_BWTR2_DATAST_4          (0x10UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */
7768  #define FMC_BWTR2_DATAST_5          (0x20UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */
7769  #define FMC_BWTR2_DATAST_6          (0x40UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */
7770  #define FMC_BWTR2_DATAST_7          (0x80UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */
7771  
7772  #define FMC_BWTR2_BUSTURN_Pos       (16U)
7773  #define FMC_BWTR2_BUSTURN_Msk       (0xFUL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */
7774  #define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7775  #define FMC_BWTR2_BUSTURN_0         (0x1UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */
7776  #define FMC_BWTR2_BUSTURN_1         (0x2UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */
7777  #define FMC_BWTR2_BUSTURN_2         (0x4UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */
7778  #define FMC_BWTR2_BUSTURN_3         (0x8UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */
7779  
7780  #define FMC_BWTR2_ACCMOD_Pos        (28U)
7781  #define FMC_BWTR2_ACCMOD_Msk        (0x3UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */
7782  #define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7783  #define FMC_BWTR2_ACCMOD_0          (0x1UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */
7784  #define FMC_BWTR2_ACCMOD_1          (0x2UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */
7785  
7786  /******************  Bit definition for FMC_BWTR3 register  ******************/
7787  #define FMC_BWTR3_ADDSET_Pos        (0U)
7788  #define FMC_BWTR3_ADDSET_Msk        (0xFUL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */
7789  #define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7790  #define FMC_BWTR3_ADDSET_0          (0x1UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */
7791  #define FMC_BWTR3_ADDSET_1          (0x2UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */
7792  #define FMC_BWTR3_ADDSET_2          (0x4UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */
7793  #define FMC_BWTR3_ADDSET_3          (0x8UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */
7794  
7795  #define FMC_BWTR3_ADDHLD_Pos        (4U)
7796  #define FMC_BWTR3_ADDHLD_Msk        (0xFUL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */
7797  #define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7798  #define FMC_BWTR3_ADDHLD_0          (0x1UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */
7799  #define FMC_BWTR3_ADDHLD_1          (0x2UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */
7800  #define FMC_BWTR3_ADDHLD_2          (0x4UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */
7801  #define FMC_BWTR3_ADDHLD_3          (0x8UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */
7802  
7803  #define FMC_BWTR3_DATAST_Pos        (8U)
7804  #define FMC_BWTR3_DATAST_Msk        (0xFFUL << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */
7805  #define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7806  #define FMC_BWTR3_DATAST_0          (0x01UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */
7807  #define FMC_BWTR3_DATAST_1          (0x02UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */
7808  #define FMC_BWTR3_DATAST_2          (0x04UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */
7809  #define FMC_BWTR3_DATAST_3          (0x08UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */
7810  #define FMC_BWTR3_DATAST_4          (0x10UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */
7811  #define FMC_BWTR3_DATAST_5          (0x20UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */
7812  #define FMC_BWTR3_DATAST_6          (0x40UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */
7813  #define FMC_BWTR3_DATAST_7          (0x80UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */
7814  
7815  #define FMC_BWTR3_BUSTURN_Pos       (16U)
7816  #define FMC_BWTR3_BUSTURN_Msk       (0xFUL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */
7817  #define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7818  #define FMC_BWTR3_BUSTURN_0         (0x1UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */
7819  #define FMC_BWTR3_BUSTURN_1         (0x2UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */
7820  #define FMC_BWTR3_BUSTURN_2         (0x4UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */
7821  #define FMC_BWTR3_BUSTURN_3         (0x8UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */
7822  
7823  #define FMC_BWTR3_ACCMOD_Pos        (28U)
7824  #define FMC_BWTR3_ACCMOD_Msk        (0x3UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */
7825  #define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7826  #define FMC_BWTR3_ACCMOD_0          (0x1UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */
7827  #define FMC_BWTR3_ACCMOD_1          (0x2UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */
7828  
7829  /******************  Bit definition for FMC_BWTR4 register  ******************/
7830  #define FMC_BWTR4_ADDSET_Pos        (0U)
7831  #define FMC_BWTR4_ADDSET_Msk        (0xFUL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */
7832  #define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7833  #define FMC_BWTR4_ADDSET_0          (0x1UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */
7834  #define FMC_BWTR4_ADDSET_1          (0x2UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */
7835  #define FMC_BWTR4_ADDSET_2          (0x4UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */
7836  #define FMC_BWTR4_ADDSET_3          (0x8UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */
7837  
7838  #define FMC_BWTR4_ADDHLD_Pos        (4U)
7839  #define FMC_BWTR4_ADDHLD_Msk        (0xFUL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */
7840  #define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7841  #define FMC_BWTR4_ADDHLD_0          (0x1UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */
7842  #define FMC_BWTR4_ADDHLD_1          (0x2UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */
7843  #define FMC_BWTR4_ADDHLD_2          (0x4UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */
7844  #define FMC_BWTR4_ADDHLD_3          (0x8UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */
7845  
7846  #define FMC_BWTR4_DATAST_Pos        (8U)
7847  #define FMC_BWTR4_DATAST_Msk        (0xFFUL << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */
7848  #define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7849  #define FMC_BWTR4_DATAST_0          (0x01UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */
7850  #define FMC_BWTR4_DATAST_1          (0x02UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */
7851  #define FMC_BWTR4_DATAST_2          (0x04UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */
7852  #define FMC_BWTR4_DATAST_3          (0x08UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */
7853  #define FMC_BWTR4_DATAST_4          (0x10UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */
7854  #define FMC_BWTR4_DATAST_5          (0x20UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */
7855  #define FMC_BWTR4_DATAST_6          (0x40UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */
7856  #define FMC_BWTR4_DATAST_7          (0x80UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */
7857  
7858  #define FMC_BWTR4_BUSTURN_Pos       (16U)
7859  #define FMC_BWTR4_BUSTURN_Msk       (0xFUL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */
7860  #define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7861  #define FMC_BWTR4_BUSTURN_0         (0x1UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */
7862  #define FMC_BWTR4_BUSTURN_1         (0x2UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */
7863  #define FMC_BWTR4_BUSTURN_2         (0x4UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */
7864  #define FMC_BWTR4_BUSTURN_3         (0x8UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */
7865  
7866  #define FMC_BWTR4_ACCMOD_Pos        (28U)
7867  #define FMC_BWTR4_ACCMOD_Msk        (0x3UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */
7868  #define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7869  #define FMC_BWTR4_ACCMOD_0          (0x1UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */
7870  #define FMC_BWTR4_ACCMOD_1          (0x2UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */
7871  
7872  /******************  Bit definition for FMC_PCR2 register  *******************/
7873  
7874  #define FMC_PCR2_PWAITEN_Pos        (1U)
7875  #define FMC_PCR2_PWAITEN_Msk        (0x1UL << FMC_PCR2_PWAITEN_Pos)             /*!< 0x00000002 */
7876  #define FMC_PCR2_PWAITEN            FMC_PCR2_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
7877  #define FMC_PCR2_PBKEN_Pos          (2U)
7878  #define FMC_PCR2_PBKEN_Msk          (0x1UL << FMC_PCR2_PBKEN_Pos)               /*!< 0x00000004 */
7879  #define FMC_PCR2_PBKEN              FMC_PCR2_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
7880  #define FMC_PCR2_PTYP_Pos           (3U)
7881  #define FMC_PCR2_PTYP_Msk           (0x1UL << FMC_PCR2_PTYP_Pos)                /*!< 0x00000008 */
7882  #define FMC_PCR2_PTYP               FMC_PCR2_PTYP_Msk                          /*!<Memory type                               */
7883  
7884  #define FMC_PCR2_PWID_Pos           (4U)
7885  #define FMC_PCR2_PWID_Msk           (0x3UL << FMC_PCR2_PWID_Pos)                /*!< 0x00000030 */
7886  #define FMC_PCR2_PWID               FMC_PCR2_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
7887  #define FMC_PCR2_PWID_0             (0x1UL << FMC_PCR2_PWID_Pos)                /*!< 0x00000010 */
7888  #define FMC_PCR2_PWID_1             (0x2UL << FMC_PCR2_PWID_Pos)                /*!< 0x00000020 */
7889  
7890  #define FMC_PCR2_ECCEN_Pos          (6U)
7891  #define FMC_PCR2_ECCEN_Msk          (0x1UL << FMC_PCR2_ECCEN_Pos)               /*!< 0x00000040 */
7892  #define FMC_PCR2_ECCEN              FMC_PCR2_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
7893  
7894  #define FMC_PCR2_TCLR_Pos           (9U)
7895  #define FMC_PCR2_TCLR_Msk           (0xFUL << FMC_PCR2_TCLR_Pos)                /*!< 0x00001E00 */
7896  #define FMC_PCR2_TCLR               FMC_PCR2_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
7897  #define FMC_PCR2_TCLR_0             (0x1UL << FMC_PCR2_TCLR_Pos)                /*!< 0x00000200 */
7898  #define FMC_PCR2_TCLR_1             (0x2UL << FMC_PCR2_TCLR_Pos)                /*!< 0x00000400 */
7899  #define FMC_PCR2_TCLR_2             (0x4UL << FMC_PCR2_TCLR_Pos)                /*!< 0x00000800 */
7900  #define FMC_PCR2_TCLR_3             (0x8UL << FMC_PCR2_TCLR_Pos)                /*!< 0x00001000 */
7901  
7902  #define FMC_PCR2_TAR_Pos            (13U)
7903  #define FMC_PCR2_TAR_Msk            (0xFUL << FMC_PCR2_TAR_Pos)                 /*!< 0x0001E000 */
7904  #define FMC_PCR2_TAR                FMC_PCR2_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
7905  #define FMC_PCR2_TAR_0              (0x1UL << FMC_PCR2_TAR_Pos)                 /*!< 0x00002000 */
7906  #define FMC_PCR2_TAR_1              (0x2UL << FMC_PCR2_TAR_Pos)                 /*!< 0x00004000 */
7907  #define FMC_PCR2_TAR_2              (0x4UL << FMC_PCR2_TAR_Pos)                 /*!< 0x00008000 */
7908  #define FMC_PCR2_TAR_3              (0x8UL << FMC_PCR2_TAR_Pos)                 /*!< 0x00010000 */
7909  
7910  #define FMC_PCR2_ECCPS_Pos          (17U)
7911  #define FMC_PCR2_ECCPS_Msk          (0x7UL << FMC_PCR2_ECCPS_Pos)               /*!< 0x000E0000 */
7912  #define FMC_PCR2_ECCPS              FMC_PCR2_ECCPS_Msk                         /*!<ECCPS[1:0] bits (ECC page size)           */
7913  #define FMC_PCR2_ECCPS_0            (0x1UL << FMC_PCR2_ECCPS_Pos)               /*!< 0x00020000 */
7914  #define FMC_PCR2_ECCPS_1            (0x2UL << FMC_PCR2_ECCPS_Pos)               /*!< 0x00040000 */
7915  #define FMC_PCR2_ECCPS_2            (0x4UL << FMC_PCR2_ECCPS_Pos)               /*!< 0x00080000 */
7916  
7917  /******************  Bit definition for FMC_PCR3 register  *******************/
7918  #define FMC_PCR3_PWAITEN_Pos        (1U)
7919  #define FMC_PCR3_PWAITEN_Msk        (0x1UL << FMC_PCR3_PWAITEN_Pos)             /*!< 0x00000002 */
7920  #define FMC_PCR3_PWAITEN            FMC_PCR3_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
7921  #define FMC_PCR3_PBKEN_Pos          (2U)
7922  #define FMC_PCR3_PBKEN_Msk          (0x1UL << FMC_PCR3_PBKEN_Pos)               /*!< 0x00000004 */
7923  #define FMC_PCR3_PBKEN              FMC_PCR3_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
7924  #define FMC_PCR3_PTYP_Pos           (3U)
7925  #define FMC_PCR3_PTYP_Msk           (0x1UL << FMC_PCR3_PTYP_Pos)                /*!< 0x00000008 */
7926  #define FMC_PCR3_PTYP               FMC_PCR3_PTYP_Msk                          /*!<Memory type                               */
7927  
7928  #define FMC_PCR3_PWID_Pos           (4U)
7929  #define FMC_PCR3_PWID_Msk           (0x3UL << FMC_PCR3_PWID_Pos)                /*!< 0x00000030 */
7930  #define FMC_PCR3_PWID               FMC_PCR3_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
7931  #define FMC_PCR3_PWID_0             (0x1UL << FMC_PCR3_PWID_Pos)                /*!< 0x00000010 */
7932  #define FMC_PCR3_PWID_1             (0x2UL << FMC_PCR3_PWID_Pos)                /*!< 0x00000020 */
7933  
7934  #define FMC_PCR3_ECCEN_Pos          (6U)
7935  #define FMC_PCR3_ECCEN_Msk          (0x1UL << FMC_PCR3_ECCEN_Pos)               /*!< 0x00000040 */
7936  #define FMC_PCR3_ECCEN              FMC_PCR3_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
7937  
7938  #define FMC_PCR3_TCLR_Pos           (9U)
7939  #define FMC_PCR3_TCLR_Msk           (0xFUL << FMC_PCR3_TCLR_Pos)                /*!< 0x00001E00 */
7940  #define FMC_PCR3_TCLR               FMC_PCR3_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
7941  #define FMC_PCR3_TCLR_0             (0x1UL << FMC_PCR3_TCLR_Pos)                /*!< 0x00000200 */
7942  #define FMC_PCR3_TCLR_1             (0x2UL << FMC_PCR3_TCLR_Pos)                /*!< 0x00000400 */
7943  #define FMC_PCR3_TCLR_2             (0x4UL << FMC_PCR3_TCLR_Pos)                /*!< 0x00000800 */
7944  #define FMC_PCR3_TCLR_3             (0x8UL << FMC_PCR3_TCLR_Pos)                /*!< 0x00001000 */
7945  
7946  #define FMC_PCR3_TAR_Pos            (13U)
7947  #define FMC_PCR3_TAR_Msk            (0xFUL << FMC_PCR3_TAR_Pos)                 /*!< 0x0001E000 */
7948  #define FMC_PCR3_TAR                FMC_PCR3_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
7949  #define FMC_PCR3_TAR_0              (0x1UL << FMC_PCR3_TAR_Pos)                 /*!< 0x00002000 */
7950  #define FMC_PCR3_TAR_1              (0x2UL << FMC_PCR3_TAR_Pos)                 /*!< 0x00004000 */
7951  #define FMC_PCR3_TAR_2              (0x4UL << FMC_PCR3_TAR_Pos)                 /*!< 0x00008000 */
7952  #define FMC_PCR3_TAR_3              (0x8UL << FMC_PCR3_TAR_Pos)                 /*!< 0x00010000 */
7953  
7954  #define FMC_PCR3_ECCPS_Pos          (17U)
7955  #define FMC_PCR3_ECCPS_Msk          (0x7UL << FMC_PCR3_ECCPS_Pos)               /*!< 0x000E0000 */
7956  #define FMC_PCR3_ECCPS              FMC_PCR3_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */
7957  #define FMC_PCR3_ECCPS_0            (0x1UL << FMC_PCR3_ECCPS_Pos)               /*!< 0x00020000 */
7958  #define FMC_PCR3_ECCPS_1            (0x2UL << FMC_PCR3_ECCPS_Pos)               /*!< 0x00040000 */
7959  #define FMC_PCR3_ECCPS_2            (0x4UL << FMC_PCR3_ECCPS_Pos)               /*!< 0x00080000 */
7960  
7961  /******************  Bit definition for FMC_PCR4 register  *******************/
7962  #define FMC_PCR4_PWAITEN_Pos        (1U)
7963  #define FMC_PCR4_PWAITEN_Msk        (0x1UL << FMC_PCR4_PWAITEN_Pos)             /*!< 0x00000002 */
7964  #define FMC_PCR4_PWAITEN            FMC_PCR4_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
7965  #define FMC_PCR4_PBKEN_Pos          (2U)
7966  #define FMC_PCR4_PBKEN_Msk          (0x1UL << FMC_PCR4_PBKEN_Pos)               /*!< 0x00000004 */
7967  #define FMC_PCR4_PBKEN              FMC_PCR4_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
7968  #define FMC_PCR4_PTYP_Pos           (3U)
7969  #define FMC_PCR4_PTYP_Msk           (0x1UL << FMC_PCR4_PTYP_Pos)                /*!< 0x00000008 */
7970  #define FMC_PCR4_PTYP               FMC_PCR4_PTYP_Msk                          /*!<Memory type                               */
7971  
7972  #define FMC_PCR4_PWID_Pos           (4U)
7973  #define FMC_PCR4_PWID_Msk           (0x3UL << FMC_PCR4_PWID_Pos)                /*!< 0x00000030 */
7974  #define FMC_PCR4_PWID               FMC_PCR4_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
7975  #define FMC_PCR4_PWID_0             (0x1UL << FMC_PCR4_PWID_Pos)                /*!< 0x00000010 */
7976  #define FMC_PCR4_PWID_1             (0x2UL << FMC_PCR4_PWID_Pos)                /*!< 0x00000020 */
7977  
7978  #define FMC_PCR4_ECCEN_Pos          (6U)
7979  #define FMC_PCR4_ECCEN_Msk          (0x1UL << FMC_PCR4_ECCEN_Pos)               /*!< 0x00000040 */
7980  #define FMC_PCR4_ECCEN              FMC_PCR4_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
7981  
7982  #define FMC_PCR4_TCLR_Pos           (9U)
7983  #define FMC_PCR4_TCLR_Msk           (0xFUL << FMC_PCR4_TCLR_Pos)                /*!< 0x00001E00 */
7984  #define FMC_PCR4_TCLR               FMC_PCR4_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
7985  #define FMC_PCR4_TCLR_0             (0x1UL << FMC_PCR4_TCLR_Pos)                /*!< 0x00000200 */
7986  #define FMC_PCR4_TCLR_1             (0x2UL << FMC_PCR4_TCLR_Pos)                /*!< 0x00000400 */
7987  #define FMC_PCR4_TCLR_2             (0x4UL << FMC_PCR4_TCLR_Pos)                /*!< 0x00000800 */
7988  #define FMC_PCR4_TCLR_3             (0x8UL << FMC_PCR4_TCLR_Pos)                /*!< 0x00001000 */
7989  
7990  #define FMC_PCR4_TAR_Pos            (13U)
7991  #define FMC_PCR4_TAR_Msk            (0xFUL << FMC_PCR4_TAR_Pos)                 /*!< 0x0001E000 */
7992  #define FMC_PCR4_TAR                FMC_PCR4_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
7993  #define FMC_PCR4_TAR_0              (0x1UL << FMC_PCR4_TAR_Pos)                 /*!< 0x00002000 */
7994  #define FMC_PCR4_TAR_1              (0x2UL << FMC_PCR4_TAR_Pos)                 /*!< 0x00004000 */
7995  #define FMC_PCR4_TAR_2              (0x4UL << FMC_PCR4_TAR_Pos)                 /*!< 0x00008000 */
7996  #define FMC_PCR4_TAR_3              (0x8UL << FMC_PCR4_TAR_Pos)                 /*!< 0x00010000 */
7997  
7998  #define FMC_PCR4_ECCPS_Pos          (17U)
7999  #define FMC_PCR4_ECCPS_Msk          (0x7UL << FMC_PCR4_ECCPS_Pos)               /*!< 0x000E0000 */
8000  #define FMC_PCR4_ECCPS              FMC_PCR4_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */
8001  #define FMC_PCR4_ECCPS_0            (0x1UL << FMC_PCR4_ECCPS_Pos)               /*!< 0x00020000 */
8002  #define FMC_PCR4_ECCPS_1            (0x2UL << FMC_PCR4_ECCPS_Pos)               /*!< 0x00040000 */
8003  #define FMC_PCR4_ECCPS_2            (0x4UL << FMC_PCR4_ECCPS_Pos)               /*!< 0x00080000 */
8004  
8005  /*******************  Bit definition for FMC_SR2 register  *******************/
8006  #define FMC_SR2_IRS_Pos             (0U)
8007  #define FMC_SR2_IRS_Msk             (0x1UL << FMC_SR2_IRS_Pos)                  /*!< 0x00000001 */
8008  #define FMC_SR2_IRS                 FMC_SR2_IRS_Msk                            /*!<Interrupt Rising Edge status                */
8009  #define FMC_SR2_ILS_Pos             (1U)
8010  #define FMC_SR2_ILS_Msk             (0x1UL << FMC_SR2_ILS_Pos)                  /*!< 0x00000002 */
8011  #define FMC_SR2_ILS                 FMC_SR2_ILS_Msk                            /*!<Interrupt Level status                      */
8012  #define FMC_SR2_IFS_Pos             (2U)
8013  #define FMC_SR2_IFS_Msk             (0x1UL << FMC_SR2_IFS_Pos)                  /*!< 0x00000004 */
8014  #define FMC_SR2_IFS                 FMC_SR2_IFS_Msk                            /*!<Interrupt Falling Edge status               */
8015  #define FMC_SR2_IREN_Pos            (3U)
8016  #define FMC_SR2_IREN_Msk            (0x1UL << FMC_SR2_IREN_Pos)                 /*!< 0x00000008 */
8017  #define FMC_SR2_IREN                FMC_SR2_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
8018  #define FMC_SR2_ILEN_Pos            (4U)
8019  #define FMC_SR2_ILEN_Msk            (0x1UL << FMC_SR2_ILEN_Pos)                 /*!< 0x00000010 */
8020  #define FMC_SR2_ILEN                FMC_SR2_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
8021  #define FMC_SR2_IFEN_Pos            (5U)
8022  #define FMC_SR2_IFEN_Msk            (0x1UL << FMC_SR2_IFEN_Pos)                 /*!< 0x00000020 */
8023  #define FMC_SR2_IFEN                FMC_SR2_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
8024  #define FMC_SR2_FEMPT_Pos           (6U)
8025  #define FMC_SR2_FEMPT_Msk           (0x1UL << FMC_SR2_FEMPT_Pos)                /*!< 0x00000040 */
8026  #define FMC_SR2_FEMPT               FMC_SR2_FEMPT_Msk                          /*!<FIFO empty                                  */
8027  
8028  /*******************  Bit definition for FMC_SR3 register  *******************/
8029  #define FMC_SR3_IRS_Pos             (0U)
8030  #define FMC_SR3_IRS_Msk             (0x1UL << FMC_SR3_IRS_Pos)                  /*!< 0x00000001 */
8031  #define FMC_SR3_IRS                 FMC_SR3_IRS_Msk                            /*!<Interrupt Rising Edge status                */
8032  #define FMC_SR3_ILS_Pos             (1U)
8033  #define FMC_SR3_ILS_Msk             (0x1UL << FMC_SR3_ILS_Pos)                  /*!< 0x00000002 */
8034  #define FMC_SR3_ILS                 FMC_SR3_ILS_Msk                            /*!<Interrupt Level status                      */
8035  #define FMC_SR3_IFS_Pos             (2U)
8036  #define FMC_SR3_IFS_Msk             (0x1UL << FMC_SR3_IFS_Pos)                  /*!< 0x00000004 */
8037  #define FMC_SR3_IFS                 FMC_SR3_IFS_Msk                            /*!<Interrupt Falling Edge status               */
8038  #define FMC_SR3_IREN_Pos            (3U)
8039  #define FMC_SR3_IREN_Msk            (0x1UL << FMC_SR3_IREN_Pos)                 /*!< 0x00000008 */
8040  #define FMC_SR3_IREN                FMC_SR3_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
8041  #define FMC_SR3_ILEN_Pos            (4U)
8042  #define FMC_SR3_ILEN_Msk            (0x1UL << FMC_SR3_ILEN_Pos)                 /*!< 0x00000010 */
8043  #define FMC_SR3_ILEN                FMC_SR3_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
8044  #define FMC_SR3_IFEN_Pos            (5U)
8045  #define FMC_SR3_IFEN_Msk            (0x1UL << FMC_SR3_IFEN_Pos)                 /*!< 0x00000020 */
8046  #define FMC_SR3_IFEN                FMC_SR3_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
8047  #define FMC_SR3_FEMPT_Pos           (6U)
8048  #define FMC_SR3_FEMPT_Msk           (0x1UL << FMC_SR3_FEMPT_Pos)                /*!< 0x00000040 */
8049  #define FMC_SR3_FEMPT               FMC_SR3_FEMPT_Msk                          /*!<FIFO empty                                  */
8050  
8051  /*******************  Bit definition for FMC_SR4 register  *******************/
8052  #define FMC_SR4_IRS_Pos             (0U)
8053  #define FMC_SR4_IRS_Msk             (0x1UL << FMC_SR4_IRS_Pos)                  /*!< 0x00000001 */
8054  #define FMC_SR4_IRS                 FMC_SR4_IRS_Msk                            /*!<Interrupt Rising Edge status                */
8055  #define FMC_SR4_ILS_Pos             (1U)
8056  #define FMC_SR4_ILS_Msk             (0x1UL << FMC_SR4_ILS_Pos)                  /*!< 0x00000002 */
8057  #define FMC_SR4_ILS                 FMC_SR4_ILS_Msk                            /*!<Interrupt Level status                      */
8058  #define FMC_SR4_IFS_Pos             (2U)
8059  #define FMC_SR4_IFS_Msk             (0x1UL << FMC_SR4_IFS_Pos)                  /*!< 0x00000004 */
8060  #define FMC_SR4_IFS                 FMC_SR4_IFS_Msk                            /*!<Interrupt Falling Edge status               */
8061  #define FMC_SR4_IREN_Pos            (3U)
8062  #define FMC_SR4_IREN_Msk            (0x1UL << FMC_SR4_IREN_Pos)                 /*!< 0x00000008 */
8063  #define FMC_SR4_IREN                FMC_SR4_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
8064  #define FMC_SR4_ILEN_Pos            (4U)
8065  #define FMC_SR4_ILEN_Msk            (0x1UL << FMC_SR4_ILEN_Pos)                 /*!< 0x00000010 */
8066  #define FMC_SR4_ILEN                FMC_SR4_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
8067  #define FMC_SR4_IFEN_Pos            (5U)
8068  #define FMC_SR4_IFEN_Msk            (0x1UL << FMC_SR4_IFEN_Pos)                 /*!< 0x00000020 */
8069  #define FMC_SR4_IFEN                FMC_SR4_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
8070  #define FMC_SR4_FEMPT_Pos           (6U)
8071  #define FMC_SR4_FEMPT_Msk           (0x1UL << FMC_SR4_FEMPT_Pos)                /*!< 0x00000040 */
8072  #define FMC_SR4_FEMPT               FMC_SR4_FEMPT_Msk                          /*!<FIFO empty                                  */
8073  
8074  /******************  Bit definition for FMC_PMEM2 register  ******************/
8075  #define FMC_PMEM2_MEMSET2_Pos       (0U)
8076  #define FMC_PMEM2_MEMSET2_Msk       (0xFFUL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x000000FF */
8077  #define FMC_PMEM2_MEMSET2           FMC_PMEM2_MEMSET2_Msk                      /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
8078  #define FMC_PMEM2_MEMSET2_0         (0x01UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000001 */
8079  #define FMC_PMEM2_MEMSET2_1         (0x02UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000002 */
8080  #define FMC_PMEM2_MEMSET2_2         (0x04UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000004 */
8081  #define FMC_PMEM2_MEMSET2_3         (0x08UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000008 */
8082  #define FMC_PMEM2_MEMSET2_4         (0x10UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000010 */
8083  #define FMC_PMEM2_MEMSET2_5         (0x20UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000020 */
8084  #define FMC_PMEM2_MEMSET2_6         (0x40UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000040 */
8085  #define FMC_PMEM2_MEMSET2_7         (0x80UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000080 */
8086  
8087  #define FMC_PMEM2_MEMWAIT2_Pos      (8U)
8088  #define FMC_PMEM2_MEMWAIT2_Msk      (0xFFUL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x0000FF00 */
8089  #define FMC_PMEM2_MEMWAIT2          FMC_PMEM2_MEMWAIT2_Msk                     /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
8090  #define FMC_PMEM2_MEMWAIT2_0        (0x01UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000100 */
8091  #define FMC_PMEM2_MEMWAIT2_1        (0x02UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000200 */
8092  #define FMC_PMEM2_MEMWAIT2_2        (0x04UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000400 */
8093  #define FMC_PMEM2_MEMWAIT2_3        (0x08UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000800 */
8094  #define FMC_PMEM2_MEMWAIT2_4        (0x10UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00001000 */
8095  #define FMC_PMEM2_MEMWAIT2_5        (0x20UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00002000 */
8096  #define FMC_PMEM2_MEMWAIT2_6        (0x40UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00004000 */
8097  #define FMC_PMEM2_MEMWAIT2_7        (0x80UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00008000 */
8098  
8099  #define FMC_PMEM2_MEMHOLD2_Pos      (16U)
8100  #define FMC_PMEM2_MEMHOLD2_Msk      (0xFFUL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00FF0000 */
8101  #define FMC_PMEM2_MEMHOLD2          FMC_PMEM2_MEMHOLD2_Msk                     /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
8102  #define FMC_PMEM2_MEMHOLD2_0        (0x01UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00010000 */
8103  #define FMC_PMEM2_MEMHOLD2_1        (0x02UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00020000 */
8104  #define FMC_PMEM2_MEMHOLD2_2        (0x04UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00040000 */
8105  #define FMC_PMEM2_MEMHOLD2_3        (0x08UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00080000 */
8106  #define FMC_PMEM2_MEMHOLD2_4        (0x10UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00100000 */
8107  #define FMC_PMEM2_MEMHOLD2_5        (0x20UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00200000 */
8108  #define FMC_PMEM2_MEMHOLD2_6        (0x40UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00400000 */
8109  #define FMC_PMEM2_MEMHOLD2_7        (0x80UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00800000 */
8110  
8111  #define FMC_PMEM2_MEMHIZ2_Pos       (24U)
8112  #define FMC_PMEM2_MEMHIZ2_Msk       (0xFFUL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0xFF000000 */
8113  #define FMC_PMEM2_MEMHIZ2           FMC_PMEM2_MEMHIZ2_Msk                      /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
8114  #define FMC_PMEM2_MEMHIZ2_0         (0x01UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x01000000 */
8115  #define FMC_PMEM2_MEMHIZ2_1         (0x02UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x02000000 */
8116  #define FMC_PMEM2_MEMHIZ2_2         (0x04UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x04000000 */
8117  #define FMC_PMEM2_MEMHIZ2_3         (0x08UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x08000000 */
8118  #define FMC_PMEM2_MEMHIZ2_4         (0x10UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x10000000 */
8119  #define FMC_PMEM2_MEMHIZ2_5         (0x20UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x20000000 */
8120  #define FMC_PMEM2_MEMHIZ2_6         (0x40UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x40000000 */
8121  #define FMC_PMEM2_MEMHIZ2_7         (0x80UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x80000000 */
8122  
8123  /******************  Bit definition for FMC_PMEM3 register  ******************/
8124  #define FMC_PMEM3_MEMSET3_Pos       (0U)
8125  #define FMC_PMEM3_MEMSET3_Msk       (0xFFUL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x000000FF */
8126  #define FMC_PMEM3_MEMSET3           FMC_PMEM3_MEMSET3_Msk                      /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
8127  #define FMC_PMEM3_MEMSET3_0         (0x01UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000001 */
8128  #define FMC_PMEM3_MEMSET3_1         (0x02UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000002 */
8129  #define FMC_PMEM3_MEMSET3_2         (0x04UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000004 */
8130  #define FMC_PMEM3_MEMSET3_3         (0x08UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000008 */
8131  #define FMC_PMEM3_MEMSET3_4         (0x10UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000010 */
8132  #define FMC_PMEM3_MEMSET3_5         (0x20UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000020 */
8133  #define FMC_PMEM3_MEMSET3_6         (0x40UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000040 */
8134  #define FMC_PMEM3_MEMSET3_7         (0x80UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000080 */
8135  
8136  #define FMC_PMEM3_MEMWAIT3_Pos      (8U)
8137  #define FMC_PMEM3_MEMWAIT3_Msk      (0xFFUL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x0000FF00 */
8138  #define FMC_PMEM3_MEMWAIT3          FMC_PMEM3_MEMWAIT3_Msk                     /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
8139  #define FMC_PMEM3_MEMWAIT3_0        (0x01UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000100 */
8140  #define FMC_PMEM3_MEMWAIT3_1        (0x02UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000200 */
8141  #define FMC_PMEM3_MEMWAIT3_2        (0x04UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000400 */
8142  #define FMC_PMEM3_MEMWAIT3_3        (0x08UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000800 */
8143  #define FMC_PMEM3_MEMWAIT3_4        (0x10UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00001000 */
8144  #define FMC_PMEM3_MEMWAIT3_5        (0x20UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00002000 */
8145  #define FMC_PMEM3_MEMWAIT3_6        (0x40UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00004000 */
8146  #define FMC_PMEM3_MEMWAIT3_7        (0x80UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00008000 */
8147  
8148  #define FMC_PMEM3_MEMHOLD3_Pos      (16U)
8149  #define FMC_PMEM3_MEMHOLD3_Msk      (0xFFUL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00FF0000 */
8150  #define FMC_PMEM3_MEMHOLD3          FMC_PMEM3_MEMHOLD3_Msk                     /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
8151  #define FMC_PMEM3_MEMHOLD3_0        (0x01UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00010000 */
8152  #define FMC_PMEM3_MEMHOLD3_1        (0x02UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00020000 */
8153  #define FMC_PMEM3_MEMHOLD3_2        (0x04UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00040000 */
8154  #define FMC_PMEM3_MEMHOLD3_3        (0x08UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00080000 */
8155  #define FMC_PMEM3_MEMHOLD3_4        (0x10UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00100000 */
8156  #define FMC_PMEM3_MEMHOLD3_5        (0x20UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00200000 */
8157  #define FMC_PMEM3_MEMHOLD3_6        (0x40UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00400000 */
8158  #define FMC_PMEM3_MEMHOLD3_7        (0x80UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00800000 */
8159  
8160  #define FMC_PMEM3_MEMHIZ3_Pos       (24U)
8161  #define FMC_PMEM3_MEMHIZ3_Msk       (0xFFUL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0xFF000000 */
8162  #define FMC_PMEM3_MEMHIZ3           FMC_PMEM3_MEMHIZ3_Msk                      /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
8163  #define FMC_PMEM3_MEMHIZ3_0         (0x01UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x01000000 */
8164  #define FMC_PMEM3_MEMHIZ3_1         (0x02UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x02000000 */
8165  #define FMC_PMEM3_MEMHIZ3_2         (0x04UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x04000000 */
8166  #define FMC_PMEM3_MEMHIZ3_3         (0x08UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x08000000 */
8167  #define FMC_PMEM3_MEMHIZ3_4         (0x10UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x10000000 */
8168  #define FMC_PMEM3_MEMHIZ3_5         (0x20UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x20000000 */
8169  #define FMC_PMEM3_MEMHIZ3_6         (0x40UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x40000000 */
8170  #define FMC_PMEM3_MEMHIZ3_7         (0x80UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x80000000 */
8171  
8172  /******************  Bit definition for FMC_PMEM4 register  ******************/
8173  #define FMC_PMEM4_MEMSET4_Pos       (0U)
8174  #define FMC_PMEM4_MEMSET4_Msk       (0xFFUL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x000000FF */
8175  #define FMC_PMEM4_MEMSET4           FMC_PMEM4_MEMSET4_Msk                      /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
8176  #define FMC_PMEM4_MEMSET4_0         (0x01UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000001 */
8177  #define FMC_PMEM4_MEMSET4_1         (0x02UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000002 */
8178  #define FMC_PMEM4_MEMSET4_2         (0x04UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000004 */
8179  #define FMC_PMEM4_MEMSET4_3         (0x08UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000008 */
8180  #define FMC_PMEM4_MEMSET4_4         (0x10UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000010 */
8181  #define FMC_PMEM4_MEMSET4_5         (0x20UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000020 */
8182  #define FMC_PMEM4_MEMSET4_6         (0x40UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000040 */
8183  #define FMC_PMEM4_MEMSET4_7         (0x80UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000080 */
8184  
8185  #define FMC_PMEM4_MEMWAIT4_Pos      (8U)
8186  #define FMC_PMEM4_MEMWAIT4_Msk      (0xFFUL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x0000FF00 */
8187  #define FMC_PMEM4_MEMWAIT4          FMC_PMEM4_MEMWAIT4_Msk                     /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
8188  #define FMC_PMEM4_MEMWAIT4_0        (0x01UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000100 */
8189  #define FMC_PMEM4_MEMWAIT4_1        (0x02UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000200 */
8190  #define FMC_PMEM4_MEMWAIT4_2        (0x04UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000400 */
8191  #define FMC_PMEM4_MEMWAIT4_3        (0x08UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000800 */
8192  #define FMC_PMEM4_MEMWAIT4_4        (0x10UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00001000 */
8193  #define FMC_PMEM4_MEMWAIT4_5        (0x20UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00002000 */
8194  #define FMC_PMEM4_MEMWAIT4_6        (0x40UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00004000 */
8195  #define FMC_PMEM4_MEMWAIT4_7        (0x80UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00008000 */
8196  
8197  #define FMC_PMEM4_MEMHOLD4_Pos      (16U)
8198  #define FMC_PMEM4_MEMHOLD4_Msk      (0xFFUL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00FF0000 */
8199  #define FMC_PMEM4_MEMHOLD4          FMC_PMEM4_MEMHOLD4_Msk                     /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
8200  #define FMC_PMEM4_MEMHOLD4_0        (0x01UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00010000 */
8201  #define FMC_PMEM4_MEMHOLD4_1        (0x02UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00020000 */
8202  #define FMC_PMEM4_MEMHOLD4_2        (0x04UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00040000 */
8203  #define FMC_PMEM4_MEMHOLD4_3        (0x08UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00080000 */
8204  #define FMC_PMEM4_MEMHOLD4_4        (0x10UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00100000 */
8205  #define FMC_PMEM4_MEMHOLD4_5        (0x20UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00200000 */
8206  #define FMC_PMEM4_MEMHOLD4_6        (0x40UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00400000 */
8207  #define FMC_PMEM4_MEMHOLD4_7        (0x80UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00800000 */
8208  
8209  #define FMC_PMEM4_MEMHIZ4_Pos       (24U)
8210  #define FMC_PMEM4_MEMHIZ4_Msk       (0xFFUL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0xFF000000 */
8211  #define FMC_PMEM4_MEMHIZ4           FMC_PMEM4_MEMHIZ4_Msk                      /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
8212  #define FMC_PMEM4_MEMHIZ4_0         (0x01UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x01000000 */
8213  #define FMC_PMEM4_MEMHIZ4_1         (0x02UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x02000000 */
8214  #define FMC_PMEM4_MEMHIZ4_2         (0x04UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x04000000 */
8215  #define FMC_PMEM4_MEMHIZ4_3         (0x08UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x08000000 */
8216  #define FMC_PMEM4_MEMHIZ4_4         (0x10UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x10000000 */
8217  #define FMC_PMEM4_MEMHIZ4_5         (0x20UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x20000000 */
8218  #define FMC_PMEM4_MEMHIZ4_6         (0x40UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x40000000 */
8219  #define FMC_PMEM4_MEMHIZ4_7         (0x80UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x80000000 */
8220  
8221  /******************  Bit definition for FMC_PATT2 register  ******************/
8222  #define FMC_PATT2_ATTSET2_Pos       (0U)
8223  #define FMC_PATT2_ATTSET2_Msk       (0xFFUL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x000000FF */
8224  #define FMC_PATT2_ATTSET2           FMC_PATT2_ATTSET2_Msk                      /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
8225  #define FMC_PATT2_ATTSET2_0         (0x01UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000001 */
8226  #define FMC_PATT2_ATTSET2_1         (0x02UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000002 */
8227  #define FMC_PATT2_ATTSET2_2         (0x04UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000004 */
8228  #define FMC_PATT2_ATTSET2_3         (0x08UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000008 */
8229  #define FMC_PATT2_ATTSET2_4         (0x10UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000010 */
8230  #define FMC_PATT2_ATTSET2_5         (0x20UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000020 */
8231  #define FMC_PATT2_ATTSET2_6         (0x40UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000040 */
8232  #define FMC_PATT2_ATTSET2_7         (0x80UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000080 */
8233  
8234  #define FMC_PATT2_ATTWAIT2_Pos      (8U)
8235  #define FMC_PATT2_ATTWAIT2_Msk      (0xFFUL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x0000FF00 */
8236  #define FMC_PATT2_ATTWAIT2          FMC_PATT2_ATTWAIT2_Msk                     /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
8237  #define FMC_PATT2_ATTWAIT2_0        (0x01UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000100 */
8238  #define FMC_PATT2_ATTWAIT2_1        (0x02UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000200 */
8239  #define FMC_PATT2_ATTWAIT2_2        (0x04UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000400 */
8240  #define FMC_PATT2_ATTWAIT2_3        (0x08UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000800 */
8241  #define FMC_PATT2_ATTWAIT2_4        (0x10UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00001000 */
8242  #define FMC_PATT2_ATTWAIT2_5        (0x20UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00002000 */
8243  #define FMC_PATT2_ATTWAIT2_6        (0x40UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00004000 */
8244  #define FMC_PATT2_ATTWAIT2_7        (0x80UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00008000 */
8245  
8246  #define FMC_PATT2_ATTHOLD2_Pos      (16U)
8247  #define FMC_PATT2_ATTHOLD2_Msk      (0xFFUL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00FF0000 */
8248  #define FMC_PATT2_ATTHOLD2          FMC_PATT2_ATTHOLD2_Msk                     /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
8249  #define FMC_PATT2_ATTHOLD2_0        (0x01UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00010000 */
8250  #define FMC_PATT2_ATTHOLD2_1        (0x02UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00020000 */
8251  #define FMC_PATT2_ATTHOLD2_2        (0x04UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00040000 */
8252  #define FMC_PATT2_ATTHOLD2_3        (0x08UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00080000 */
8253  #define FMC_PATT2_ATTHOLD2_4        (0x10UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00100000 */
8254  #define FMC_PATT2_ATTHOLD2_5        (0x20UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00200000 */
8255  #define FMC_PATT2_ATTHOLD2_6        (0x40UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00400000 */
8256  #define FMC_PATT2_ATTHOLD2_7        (0x80UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00800000 */
8257  
8258  #define FMC_PATT2_ATTHIZ2_Pos       (24U)
8259  #define FMC_PATT2_ATTHIZ2_Msk       (0xFFUL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0xFF000000 */
8260  #define FMC_PATT2_ATTHIZ2           FMC_PATT2_ATTHIZ2_Msk                      /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
8261  #define FMC_PATT2_ATTHIZ2_0         (0x01UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x01000000 */
8262  #define FMC_PATT2_ATTHIZ2_1         (0x02UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x02000000 */
8263  #define FMC_PATT2_ATTHIZ2_2         (0x04UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x04000000 */
8264  #define FMC_PATT2_ATTHIZ2_3         (0x08UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x08000000 */
8265  #define FMC_PATT2_ATTHIZ2_4         (0x10UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x10000000 */
8266  #define FMC_PATT2_ATTHIZ2_5         (0x20UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x20000000 */
8267  #define FMC_PATT2_ATTHIZ2_6         (0x40UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x40000000 */
8268  #define FMC_PATT2_ATTHIZ2_7         (0x80UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x80000000 */
8269  
8270  /******************  Bit definition for FMC_PATT3 register  ******************/
8271  #define FMC_PATT3_ATTSET3_Pos       (0U)
8272  #define FMC_PATT3_ATTSET3_Msk       (0xFFUL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x000000FF */
8273  #define FMC_PATT3_ATTSET3           FMC_PATT3_ATTSET3_Msk                      /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
8274  #define FMC_PATT3_ATTSET3_0         (0x01UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000001 */
8275  #define FMC_PATT3_ATTSET3_1         (0x02UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000002 */
8276  #define FMC_PATT3_ATTSET3_2         (0x04UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000004 */
8277  #define FMC_PATT3_ATTSET3_3         (0x08UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000008 */
8278  #define FMC_PATT3_ATTSET3_4         (0x10UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000010 */
8279  #define FMC_PATT3_ATTSET3_5         (0x20UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000020 */
8280  #define FMC_PATT3_ATTSET3_6         (0x40UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000040 */
8281  #define FMC_PATT3_ATTSET3_7         (0x80UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000080 */
8282  
8283  #define FMC_PATT3_ATTWAIT3_Pos      (8U)
8284  #define FMC_PATT3_ATTWAIT3_Msk      (0xFFUL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x0000FF00 */
8285  #define FMC_PATT3_ATTWAIT3          FMC_PATT3_ATTWAIT3_Msk                     /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
8286  #define FMC_PATT3_ATTWAIT3_0        (0x01UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000100 */
8287  #define FMC_PATT3_ATTWAIT3_1        (0x02UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000200 */
8288  #define FMC_PATT3_ATTWAIT3_2        (0x04UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000400 */
8289  #define FMC_PATT3_ATTWAIT3_3        (0x08UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000800 */
8290  #define FMC_PATT3_ATTWAIT3_4        (0x10UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00001000 */
8291  #define FMC_PATT3_ATTWAIT3_5        (0x20UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00002000 */
8292  #define FMC_PATT3_ATTWAIT3_6        (0x40UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00004000 */
8293  #define FMC_PATT3_ATTWAIT3_7        (0x80UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00008000 */
8294  
8295  #define FMC_PATT3_ATTHOLD3_Pos      (16U)
8296  #define FMC_PATT3_ATTHOLD3_Msk      (0xFFUL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00FF0000 */
8297  #define FMC_PATT3_ATTHOLD3          FMC_PATT3_ATTHOLD3_Msk                     /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
8298  #define FMC_PATT3_ATTHOLD3_0        (0x01UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00010000 */
8299  #define FMC_PATT3_ATTHOLD3_1        (0x02UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00020000 */
8300  #define FMC_PATT3_ATTHOLD3_2        (0x04UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00040000 */
8301  #define FMC_PATT3_ATTHOLD3_3        (0x08UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00080000 */
8302  #define FMC_PATT3_ATTHOLD3_4        (0x10UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00100000 */
8303  #define FMC_PATT3_ATTHOLD3_5        (0x20UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00200000 */
8304  #define FMC_PATT3_ATTHOLD3_6        (0x40UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00400000 */
8305  #define FMC_PATT3_ATTHOLD3_7        (0x80UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00800000 */
8306  
8307  #define FMC_PATT3_ATTHIZ3_Pos       (24U)
8308  #define FMC_PATT3_ATTHIZ3_Msk       (0xFFUL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0xFF000000 */
8309  #define FMC_PATT3_ATTHIZ3           FMC_PATT3_ATTHIZ3_Msk                      /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
8310  #define FMC_PATT3_ATTHIZ3_0         (0x01UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x01000000 */
8311  #define FMC_PATT3_ATTHIZ3_1         (0x02UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x02000000 */
8312  #define FMC_PATT3_ATTHIZ3_2         (0x04UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x04000000 */
8313  #define FMC_PATT3_ATTHIZ3_3         (0x08UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x08000000 */
8314  #define FMC_PATT3_ATTHIZ3_4         (0x10UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x10000000 */
8315  #define FMC_PATT3_ATTHIZ3_5         (0x20UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x20000000 */
8316  #define FMC_PATT3_ATTHIZ3_6         (0x40UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x40000000 */
8317  #define FMC_PATT3_ATTHIZ3_7         (0x80UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x80000000 */
8318  
8319  /******************  Bit definition for FMC_PATT4 register  ******************/
8320  #define FMC_PATT4_ATTSET4_Pos       (0U)
8321  #define FMC_PATT4_ATTSET4_Msk       (0xFFUL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x000000FF */
8322  #define FMC_PATT4_ATTSET4           FMC_PATT4_ATTSET4_Msk                      /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
8323  #define FMC_PATT4_ATTSET4_0         (0x01UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000001 */
8324  #define FMC_PATT4_ATTSET4_1         (0x02UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000002 */
8325  #define FMC_PATT4_ATTSET4_2         (0x04UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000004 */
8326  #define FMC_PATT4_ATTSET4_3         (0x08UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000008 */
8327  #define FMC_PATT4_ATTSET4_4         (0x10UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000010 */
8328  #define FMC_PATT4_ATTSET4_5         (0x20UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000020 */
8329  #define FMC_PATT4_ATTSET4_6         (0x40UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000040 */
8330  #define FMC_PATT4_ATTSET4_7         (0x80UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000080 */
8331  
8332  #define FMC_PATT4_ATTWAIT4_Pos      (8U)
8333  #define FMC_PATT4_ATTWAIT4_Msk      (0xFFUL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x0000FF00 */
8334  #define FMC_PATT4_ATTWAIT4          FMC_PATT4_ATTWAIT4_Msk                     /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
8335  #define FMC_PATT4_ATTWAIT4_0        (0x01UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000100 */
8336  #define FMC_PATT4_ATTWAIT4_1        (0x02UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000200 */
8337  #define FMC_PATT4_ATTWAIT4_2        (0x04UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000400 */
8338  #define FMC_PATT4_ATTWAIT4_3        (0x08UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000800 */
8339  #define FMC_PATT4_ATTWAIT4_4        (0x10UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00001000 */
8340  #define FMC_PATT4_ATTWAIT4_5        (0x20UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00002000 */
8341  #define FMC_PATT4_ATTWAIT4_6        (0x40UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00004000 */
8342  #define FMC_PATT4_ATTWAIT4_7        (0x80UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00008000 */
8343  
8344  #define FMC_PATT4_ATTHOLD4_Pos      (16U)
8345  #define FMC_PATT4_ATTHOLD4_Msk      (0xFFUL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00FF0000 */
8346  #define FMC_PATT4_ATTHOLD4          FMC_PATT4_ATTHOLD4_Msk                     /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
8347  #define FMC_PATT4_ATTHOLD4_0        (0x01UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00010000 */
8348  #define FMC_PATT4_ATTHOLD4_1        (0x02UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00020000 */
8349  #define FMC_PATT4_ATTHOLD4_2        (0x04UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00040000 */
8350  #define FMC_PATT4_ATTHOLD4_3        (0x08UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00080000 */
8351  #define FMC_PATT4_ATTHOLD4_4        (0x10UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00100000 */
8352  #define FMC_PATT4_ATTHOLD4_5        (0x20UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00200000 */
8353  #define FMC_PATT4_ATTHOLD4_6        (0x40UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00400000 */
8354  #define FMC_PATT4_ATTHOLD4_7        (0x80UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00800000 */
8355  
8356  #define FMC_PATT4_ATTHIZ4_Pos       (24U)
8357  #define FMC_PATT4_ATTHIZ4_Msk       (0xFFUL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0xFF000000 */
8358  #define FMC_PATT4_ATTHIZ4           FMC_PATT4_ATTHIZ4_Msk                      /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
8359  #define FMC_PATT4_ATTHIZ4_0         (0x01UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x01000000 */
8360  #define FMC_PATT4_ATTHIZ4_1         (0x02UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x02000000 */
8361  #define FMC_PATT4_ATTHIZ4_2         (0x04UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x04000000 */
8362  #define FMC_PATT4_ATTHIZ4_3         (0x08UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x08000000 */
8363  #define FMC_PATT4_ATTHIZ4_4         (0x10UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x10000000 */
8364  #define FMC_PATT4_ATTHIZ4_5         (0x20UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x20000000 */
8365  #define FMC_PATT4_ATTHIZ4_6         (0x40UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x40000000 */
8366  #define FMC_PATT4_ATTHIZ4_7         (0x80UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x80000000 */
8367  
8368  /******************  Bit definition for FMC_PIO4 register  *******************/
8369  #define FMC_PIO4_IOSET4_Pos         (0U)
8370  #define FMC_PIO4_IOSET4_Msk         (0xFFUL << FMC_PIO4_IOSET4_Pos)             /*!< 0x000000FF */
8371  #define FMC_PIO4_IOSET4             FMC_PIO4_IOSET4_Msk                        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
8372  #define FMC_PIO4_IOSET4_0           (0x01UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000001 */
8373  #define FMC_PIO4_IOSET4_1           (0x02UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000002 */
8374  #define FMC_PIO4_IOSET4_2           (0x04UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000004 */
8375  #define FMC_PIO4_IOSET4_3           (0x08UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000008 */
8376  #define FMC_PIO4_IOSET4_4           (0x10UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000010 */
8377  #define FMC_PIO4_IOSET4_5           (0x20UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000020 */
8378  #define FMC_PIO4_IOSET4_6           (0x40UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000040 */
8379  #define FMC_PIO4_IOSET4_7           (0x80UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000080 */
8380  
8381  #define FMC_PIO4_IOWAIT4_Pos        (8U)
8382  #define FMC_PIO4_IOWAIT4_Msk        (0xFFUL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x0000FF00 */
8383  #define FMC_PIO4_IOWAIT4            FMC_PIO4_IOWAIT4_Msk                       /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
8384  #define FMC_PIO4_IOWAIT4_0          (0x01UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000100 */
8385  #define FMC_PIO4_IOWAIT4_1          (0x02UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000200 */
8386  #define FMC_PIO4_IOWAIT4_2          (0x04UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000400 */
8387  #define FMC_PIO4_IOWAIT4_3          (0x08UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000800 */
8388  #define FMC_PIO4_IOWAIT4_4          (0x10UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00001000 */
8389  #define FMC_PIO4_IOWAIT4_5          (0x20UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00002000 */
8390  #define FMC_PIO4_IOWAIT4_6          (0x40UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00004000 */
8391  #define FMC_PIO4_IOWAIT4_7          (0x80UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00008000 */
8392  
8393  #define FMC_PIO4_IOHOLD4_Pos        (16U)
8394  #define FMC_PIO4_IOHOLD4_Msk        (0xFFUL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00FF0000 */
8395  #define FMC_PIO4_IOHOLD4            FMC_PIO4_IOHOLD4_Msk                       /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
8396  #define FMC_PIO4_IOHOLD4_0          (0x01UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00010000 */
8397  #define FMC_PIO4_IOHOLD4_1          (0x02UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00020000 */
8398  #define FMC_PIO4_IOHOLD4_2          (0x04UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00040000 */
8399  #define FMC_PIO4_IOHOLD4_3          (0x08UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00080000 */
8400  #define FMC_PIO4_IOHOLD4_4          (0x10UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00100000 */
8401  #define FMC_PIO4_IOHOLD4_5          (0x20UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00200000 */
8402  #define FMC_PIO4_IOHOLD4_6          (0x40UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00400000 */
8403  #define FMC_PIO4_IOHOLD4_7          (0x80UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00800000 */
8404  
8405  #define FMC_PIO4_IOHIZ4_Pos         (24U)
8406  #define FMC_PIO4_IOHIZ4_Msk         (0xFFUL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0xFF000000 */
8407  #define FMC_PIO4_IOHIZ4             FMC_PIO4_IOHIZ4_Msk                        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
8408  #define FMC_PIO4_IOHIZ4_0           (0x01UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x01000000 */
8409  #define FMC_PIO4_IOHIZ4_1           (0x02UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x02000000 */
8410  #define FMC_PIO4_IOHIZ4_2           (0x04UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x04000000 */
8411  #define FMC_PIO4_IOHIZ4_3           (0x08UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x08000000 */
8412  #define FMC_PIO4_IOHIZ4_4           (0x10UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x10000000 */
8413  #define FMC_PIO4_IOHIZ4_5           (0x20UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x20000000 */
8414  #define FMC_PIO4_IOHIZ4_6           (0x40UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x40000000 */
8415  #define FMC_PIO4_IOHIZ4_7           (0x80UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x80000000 */
8416  
8417  
8418  /******************  Bit definition for FMC_ECCR2 register  ******************/
8419  #define FMC_ECCR2_ECC2_Pos          (0U)
8420  #define FMC_ECCR2_ECC2_Msk          (0xFFFFFFFFUL << FMC_ECCR2_ECC2_Pos)        /*!< 0xFFFFFFFF */
8421  #define FMC_ECCR2_ECC2              FMC_ECCR2_ECC2_Msk                         /*!<ECC result */
8422  
8423  /******************  Bit definition for FMC_ECCR3 register  ******************/
8424  #define FMC_ECCR3_ECC3_Pos          (0U)
8425  #define FMC_ECCR3_ECC3_Msk          (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
8426  #define FMC_ECCR3_ECC3              FMC_ECCR3_ECC3_Msk                         /*!<ECC result */
8427  
8428  /******************  Bit definition for FMC_SDCR1 register  ******************/
8429  #define FMC_SDCR1_NC_Pos            (0U)
8430  #define FMC_SDCR1_NC_Msk            (0x3UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */
8431  #define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
8432  #define FMC_SDCR1_NC_0              (0x1UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */
8433  #define FMC_SDCR1_NC_1              (0x2UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */
8434  
8435  #define FMC_SDCR1_NR_Pos            (2U)
8436  #define FMC_SDCR1_NR_Msk            (0x3UL << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */
8437  #define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
8438  #define FMC_SDCR1_NR_0              (0x1UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */
8439  #define FMC_SDCR1_NR_1              (0x2UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */
8440  
8441  #define FMC_SDCR1_MWID_Pos          (4U)
8442  #define FMC_SDCR1_MWID_Msk          (0x3UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */
8443  #define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
8444  #define FMC_SDCR1_MWID_0            (0x1UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */
8445  #define FMC_SDCR1_MWID_1            (0x2UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */
8446  
8447  #define FMC_SDCR1_NB_Pos            (6U)
8448  #define FMC_SDCR1_NB_Msk            (0x1UL << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */
8449  #define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */
8450  
8451  #define FMC_SDCR1_CAS_Pos           (7U)
8452  #define FMC_SDCR1_CAS_Msk           (0x3UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */
8453  #define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
8454  #define FMC_SDCR1_CAS_0             (0x1UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */
8455  #define FMC_SDCR1_CAS_1             (0x2UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */
8456  
8457  #define FMC_SDCR1_WP_Pos            (9U)
8458  #define FMC_SDCR1_WP_Msk            (0x1UL << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */
8459  #define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */
8460  
8461  #define FMC_SDCR1_SDCLK_Pos         (10U)
8462  #define FMC_SDCR1_SDCLK_Msk         (0x3UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */
8463  #define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */
8464  #define FMC_SDCR1_SDCLK_0           (0x1UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */
8465  #define FMC_SDCR1_SDCLK_1           (0x2UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */
8466  
8467  #define FMC_SDCR1_RBURST_Pos        (12U)
8468  #define FMC_SDCR1_RBURST_Msk        (0x1UL << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */
8469  #define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */
8470  
8471  #define FMC_SDCR1_RPIPE_Pos         (13U)
8472  #define FMC_SDCR1_RPIPE_Msk         (0x3UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */
8473  #define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */
8474  #define FMC_SDCR1_RPIPE_0           (0x1UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */
8475  #define FMC_SDCR1_RPIPE_1           (0x2UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */
8476  
8477  /******************  Bit definition for FMC_SDCR2 register  ******************/
8478  #define FMC_SDCR2_NC_Pos            (0U)
8479  #define FMC_SDCR2_NC_Msk            (0x3UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */
8480  #define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
8481  #define FMC_SDCR2_NC_0              (0x1UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */
8482  #define FMC_SDCR2_NC_1              (0x2UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */
8483  
8484  #define FMC_SDCR2_NR_Pos            (2U)
8485  #define FMC_SDCR2_NR_Msk            (0x3UL << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */
8486  #define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
8487  #define FMC_SDCR2_NR_0              (0x1UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */
8488  #define FMC_SDCR2_NR_1              (0x2UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */
8489  
8490  #define FMC_SDCR2_MWID_Pos          (4U)
8491  #define FMC_SDCR2_MWID_Msk          (0x3UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */
8492  #define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
8493  #define FMC_SDCR2_MWID_0            (0x1UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */
8494  #define FMC_SDCR2_MWID_1            (0x2UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */
8495  
8496  #define FMC_SDCR2_NB_Pos            (6U)
8497  #define FMC_SDCR2_NB_Msk            (0x1UL << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */
8498  #define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */
8499  
8500  #define FMC_SDCR2_CAS_Pos           (7U)
8501  #define FMC_SDCR2_CAS_Msk           (0x3UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */
8502  #define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
8503  #define FMC_SDCR2_CAS_0             (0x1UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */
8504  #define FMC_SDCR2_CAS_1             (0x2UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */
8505  
8506  #define FMC_SDCR2_WP_Pos            (9U)
8507  #define FMC_SDCR2_WP_Msk            (0x1UL << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */
8508  #define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */
8509  
8510  #define FMC_SDCR2_SDCLK_Pos         (10U)
8511  #define FMC_SDCR2_SDCLK_Msk         (0x3UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */
8512  #define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */
8513  #define FMC_SDCR2_SDCLK_0           (0x1UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */
8514  #define FMC_SDCR2_SDCLK_1           (0x2UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */
8515  
8516  #define FMC_SDCR2_RBURST_Pos        (12U)
8517  #define FMC_SDCR2_RBURST_Msk        (0x1UL << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */
8518  #define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */
8519  
8520  #define FMC_SDCR2_RPIPE_Pos         (13U)
8521  #define FMC_SDCR2_RPIPE_Msk         (0x3UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */
8522  #define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */
8523  #define FMC_SDCR2_RPIPE_0           (0x1UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */
8524  #define FMC_SDCR2_RPIPE_1           (0x2UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */
8525  
8526  /******************  Bit definition for FMC_SDTR1 register  ******************/
8527  #define FMC_SDTR1_TMRD_Pos          (0U)
8528  #define FMC_SDTR1_TMRD_Msk          (0xFUL << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */
8529  #define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
8530  #define FMC_SDTR1_TMRD_0            (0x1UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */
8531  #define FMC_SDTR1_TMRD_1            (0x2UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */
8532  #define FMC_SDTR1_TMRD_2            (0x4UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */
8533  #define FMC_SDTR1_TMRD_3            (0x8UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */
8534  
8535  #define FMC_SDTR1_TXSR_Pos          (4U)
8536  #define FMC_SDTR1_TXSR_Msk          (0xFUL << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */
8537  #define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
8538  #define FMC_SDTR1_TXSR_0            (0x1UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */
8539  #define FMC_SDTR1_TXSR_1            (0x2UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */
8540  #define FMC_SDTR1_TXSR_2            (0x4UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */
8541  #define FMC_SDTR1_TXSR_3            (0x8UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */
8542  
8543  #define FMC_SDTR1_TRAS_Pos          (8U)
8544  #define FMC_SDTR1_TRAS_Msk          (0xFUL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */
8545  #define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
8546  #define FMC_SDTR1_TRAS_0            (0x1UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */
8547  #define FMC_SDTR1_TRAS_1            (0x2UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */
8548  #define FMC_SDTR1_TRAS_2            (0x4UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */
8549  #define FMC_SDTR1_TRAS_3            (0x8UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */
8550  
8551  #define FMC_SDTR1_TRC_Pos           (12U)
8552  #define FMC_SDTR1_TRC_Msk           (0xFUL << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */
8553  #define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
8554  #define FMC_SDTR1_TRC_0             (0x1UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */
8555  #define FMC_SDTR1_TRC_1             (0x2UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */
8556  #define FMC_SDTR1_TRC_2             (0x4UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */
8557  
8558  #define FMC_SDTR1_TWR_Pos           (16U)
8559  #define FMC_SDTR1_TWR_Msk           (0xFUL << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */
8560  #define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
8561  #define FMC_SDTR1_TWR_0             (0x1UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */
8562  #define FMC_SDTR1_TWR_1             (0x2UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */
8563  #define FMC_SDTR1_TWR_2             (0x4UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */
8564  
8565  #define FMC_SDTR1_TRP_Pos           (20U)
8566  #define FMC_SDTR1_TRP_Msk           (0xFUL << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */
8567  #define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
8568  #define FMC_SDTR1_TRP_0             (0x1UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */
8569  #define FMC_SDTR1_TRP_1             (0x2UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */
8570  #define FMC_SDTR1_TRP_2             (0x4UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */
8571  
8572  #define FMC_SDTR1_TRCD_Pos          (24U)
8573  #define FMC_SDTR1_TRCD_Msk          (0xFUL << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */
8574  #define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
8575  #define FMC_SDTR1_TRCD_0            (0x1UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */
8576  #define FMC_SDTR1_TRCD_1            (0x2UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */
8577  #define FMC_SDTR1_TRCD_2            (0x4UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */
8578  
8579  /******************  Bit definition for FMC_SDTR2 register  ******************/
8580  #define FMC_SDTR2_TMRD_Pos          (0U)
8581  #define FMC_SDTR2_TMRD_Msk          (0xFUL << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */
8582  #define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
8583  #define FMC_SDTR2_TMRD_0            (0x1UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */
8584  #define FMC_SDTR2_TMRD_1            (0x2UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */
8585  #define FMC_SDTR2_TMRD_2            (0x4UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */
8586  #define FMC_SDTR2_TMRD_3            (0x8UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */
8587  
8588  #define FMC_SDTR2_TXSR_Pos          (4U)
8589  #define FMC_SDTR2_TXSR_Msk          (0xFUL << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */
8590  #define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
8591  #define FMC_SDTR2_TXSR_0            (0x1UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */
8592  #define FMC_SDTR2_TXSR_1            (0x2UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */
8593  #define FMC_SDTR2_TXSR_2            (0x4UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */
8594  #define FMC_SDTR2_TXSR_3            (0x8UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */
8595  
8596  #define FMC_SDTR2_TRAS_Pos          (8U)
8597  #define FMC_SDTR2_TRAS_Msk          (0xFUL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */
8598  #define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
8599  #define FMC_SDTR2_TRAS_0            (0x1UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */
8600  #define FMC_SDTR2_TRAS_1            (0x2UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */
8601  #define FMC_SDTR2_TRAS_2            (0x4UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */
8602  #define FMC_SDTR2_TRAS_3            (0x8UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */
8603  
8604  #define FMC_SDTR2_TRC_Pos           (12U)
8605  #define FMC_SDTR2_TRC_Msk           (0xFUL << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */
8606  #define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
8607  #define FMC_SDTR2_TRC_0             (0x1UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */
8608  #define FMC_SDTR2_TRC_1             (0x2UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */
8609  #define FMC_SDTR2_TRC_2             (0x4UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */
8610  
8611  #define FMC_SDTR2_TWR_Pos           (16U)
8612  #define FMC_SDTR2_TWR_Msk           (0xFUL << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */
8613  #define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
8614  #define FMC_SDTR2_TWR_0             (0x1UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */
8615  #define FMC_SDTR2_TWR_1             (0x2UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */
8616  #define FMC_SDTR2_TWR_2             (0x4UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */
8617  
8618  #define FMC_SDTR2_TRP_Pos           (20U)
8619  #define FMC_SDTR2_TRP_Msk           (0xFUL << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */
8620  #define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
8621  #define FMC_SDTR2_TRP_0             (0x1UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */
8622  #define FMC_SDTR2_TRP_1             (0x2UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */
8623  #define FMC_SDTR2_TRP_2             (0x4UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */
8624  
8625  #define FMC_SDTR2_TRCD_Pos          (24U)
8626  #define FMC_SDTR2_TRCD_Msk          (0xFUL << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */
8627  #define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
8628  #define FMC_SDTR2_TRCD_0            (0x1UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */
8629  #define FMC_SDTR2_TRCD_1            (0x2UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */
8630  #define FMC_SDTR2_TRCD_2            (0x4UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */
8631  
8632  /******************  Bit definition for FMC_SDCMR register  ******************/
8633  #define FMC_SDCMR_MODE_Pos          (0U)
8634  #define FMC_SDCMR_MODE_Msk          (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
8635  #define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */
8636  #define FMC_SDCMR_MODE_0            (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
8637  #define FMC_SDCMR_MODE_1            (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
8638  #define FMC_SDCMR_MODE_2            (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
8639  
8640  #define FMC_SDCMR_CTB2_Pos          (3U)
8641  #define FMC_SDCMR_CTB2_Msk          (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
8642  #define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */
8643  
8644  #define FMC_SDCMR_CTB1_Pos          (4U)
8645  #define FMC_SDCMR_CTB1_Msk          (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
8646  #define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */
8647  
8648  #define FMC_SDCMR_NRFS_Pos          (5U)
8649  #define FMC_SDCMR_NRFS_Msk          (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
8650  #define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */
8651  #define FMC_SDCMR_NRFS_0            (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
8652  #define FMC_SDCMR_NRFS_1            (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
8653  #define FMC_SDCMR_NRFS_2            (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
8654  #define FMC_SDCMR_NRFS_3            (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
8655  
8656  #define FMC_SDCMR_MRD_Pos           (9U)
8657  #define FMC_SDCMR_MRD_Msk           (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
8658  #define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */
8659  
8660  /******************  Bit definition for FMC_SDRTR register  ******************/
8661  #define FMC_SDRTR_CRE_Pos           (0U)
8662  #define FMC_SDRTR_CRE_Msk           (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
8663  #define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */
8664  
8665  #define FMC_SDRTR_COUNT_Pos         (1U)
8666  #define FMC_SDRTR_COUNT_Msk         (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
8667  #define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */
8668  
8669  #define FMC_SDRTR_REIE_Pos          (14U)
8670  #define FMC_SDRTR_REIE_Msk          (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
8671  #define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interupt enable */
8672  
8673  /******************  Bit definition for FMC_SDSR register  ******************/
8674  #define FMC_SDSR_RE_Pos             (0U)
8675  #define FMC_SDSR_RE_Msk             (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
8676  #define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */
8677  
8678  #define FMC_SDSR_MODES1_Pos         (1U)
8679  #define FMC_SDSR_MODES1_Msk         (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
8680  #define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */
8681  #define FMC_SDSR_MODES1_0           (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
8682  #define FMC_SDSR_MODES1_1           (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
8683  
8684  #define FMC_SDSR_MODES2_Pos         (3U)
8685  #define FMC_SDSR_MODES2_Msk         (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
8686  #define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */
8687  #define FMC_SDSR_MODES2_0           (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
8688  #define FMC_SDSR_MODES2_1           (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
8689  #define FMC_SDSR_BUSY_Pos           (5U)
8690  #define FMC_SDSR_BUSY_Msk           (0x1UL << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */
8691  #define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */
8692  
8693  /******************************************************************************/
8694  /*                                                                            */
8695  /*                            General Purpose I/O                             */
8696  /*                                                                            */
8697  /******************************************************************************/
8698  /******************  Bits definition for GPIO_MODER register  *****************/
8699  #define GPIO_MODER_MODER0_Pos            (0U)
8700  #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
8701  #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
8702  #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
8703  #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
8704  #define GPIO_MODER_MODER1_Pos            (2U)
8705  #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
8706  #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
8707  #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
8708  #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
8709  #define GPIO_MODER_MODER2_Pos            (4U)
8710  #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
8711  #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
8712  #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
8713  #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
8714  #define GPIO_MODER_MODER3_Pos            (6U)
8715  #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
8716  #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
8717  #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
8718  #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
8719  #define GPIO_MODER_MODER4_Pos            (8U)
8720  #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
8721  #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
8722  #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
8723  #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
8724  #define GPIO_MODER_MODER5_Pos            (10U)
8725  #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
8726  #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
8727  #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
8728  #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
8729  #define GPIO_MODER_MODER6_Pos            (12U)
8730  #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
8731  #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
8732  #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
8733  #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
8734  #define GPIO_MODER_MODER7_Pos            (14U)
8735  #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
8736  #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
8737  #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
8738  #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
8739  #define GPIO_MODER_MODER8_Pos            (16U)
8740  #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
8741  #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
8742  #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
8743  #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
8744  #define GPIO_MODER_MODER9_Pos            (18U)
8745  #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
8746  #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
8747  #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
8748  #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
8749  #define GPIO_MODER_MODER10_Pos           (20U)
8750  #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
8751  #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
8752  #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
8753  #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
8754  #define GPIO_MODER_MODER11_Pos           (22U)
8755  #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
8756  #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
8757  #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
8758  #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
8759  #define GPIO_MODER_MODER12_Pos           (24U)
8760  #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
8761  #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
8762  #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
8763  #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
8764  #define GPIO_MODER_MODER13_Pos           (26U)
8765  #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
8766  #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
8767  #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
8768  #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
8769  #define GPIO_MODER_MODER14_Pos           (28U)
8770  #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
8771  #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
8772  #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
8773  #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
8774  #define GPIO_MODER_MODER15_Pos           (30U)
8775  #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
8776  #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
8777  #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
8778  #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
8779  
8780  /* Legacy defines */
8781  #define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos
8782  #define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk
8783  #define GPIO_MODER_MODE0                 GPIO_MODER_MODER0
8784  #define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0
8785  #define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1
8786  #define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos
8787  #define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk
8788  #define GPIO_MODER_MODE1                 GPIO_MODER_MODER1
8789  #define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0
8790  #define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1
8791  #define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_PoS
8792  #define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk
8793  #define GPIO_MODER_MODE2                 GPIO_MODER_MODER2
8794  #define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0
8795  #define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1
8796  #define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos
8797  #define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk
8798  #define GPIO_MODER_MODE3                 GPIO_MODER_MODER3
8799  #define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0
8800  #define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1
8801  #define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos
8802  #define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk
8803  #define GPIO_MODER_MODE4                 GPIO_MODER_MODER4
8804  #define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0
8805  #define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1
8806  #define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos
8807  #define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk
8808  #define GPIO_MODER_MODE5                 GPIO_MODER_MODER5
8809  #define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0
8810  #define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1
8811  #define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos
8812  #define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk
8813  #define GPIO_MODER_MODE6                 GPIO_MODER_MODER6
8814  #define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0
8815  #define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1
8816  #define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos
8817  #define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk
8818  #define GPIO_MODER_MODE7                 GPIO_MODER_MODER7
8819  #define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0
8820  #define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1
8821  #define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos
8822  #define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk
8823  #define GPIO_MODER_MODE8                 GPIO_MODER_MODER8
8824  #define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0
8825  #define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1
8826  #define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos
8827  #define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk
8828  #define GPIO_MODER_MODE9                 GPIO_MODER_MODER9
8829  #define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0
8830  #define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1
8831  #define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos
8832  #define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk
8833  #define GPIO_MODER_MODE10                GPIO_MODER_MODER10
8834  #define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0
8835  #define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1
8836  #define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos
8837  #define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk
8838  #define GPIO_MODER_MODE11                GPIO_MODER_MODER11
8839  #define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0
8840  #define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1
8841  #define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos
8842  #define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk
8843  #define GPIO_MODER_MODE12                GPIO_MODER_MODER12
8844  #define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0
8845  #define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1
8846  #define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos
8847  #define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk
8848  #define GPIO_MODER_MODE13                GPIO_MODER_MODER13
8849  #define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0
8850  #define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1
8851  #define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos
8852  #define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk
8853  #define GPIO_MODER_MODE14                GPIO_MODER_MODER14
8854  #define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0
8855  #define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1
8856  #define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos
8857  #define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk
8858  #define GPIO_MODER_MODE15                GPIO_MODER_MODER15
8859  #define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0
8860  #define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1
8861  
8862  /******************  Bits definition for GPIO_OTYPER register  ****************/
8863  #define GPIO_OTYPER_OT0_Pos              (0U)
8864  #define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
8865  #define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk
8866  #define GPIO_OTYPER_OT1_Pos              (1U)
8867  #define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
8868  #define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk
8869  #define GPIO_OTYPER_OT2_Pos              (2U)
8870  #define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
8871  #define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk
8872  #define GPIO_OTYPER_OT3_Pos              (3U)
8873  #define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
8874  #define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk
8875  #define GPIO_OTYPER_OT4_Pos              (4U)
8876  #define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
8877  #define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk
8878  #define GPIO_OTYPER_OT5_Pos              (5U)
8879  #define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
8880  #define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk
8881  #define GPIO_OTYPER_OT6_Pos              (6U)
8882  #define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
8883  #define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk
8884  #define GPIO_OTYPER_OT7_Pos              (7U)
8885  #define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
8886  #define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk
8887  #define GPIO_OTYPER_OT8_Pos              (8U)
8888  #define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
8889  #define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk
8890  #define GPIO_OTYPER_OT9_Pos              (9U)
8891  #define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
8892  #define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk
8893  #define GPIO_OTYPER_OT10_Pos             (10U)
8894  #define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
8895  #define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk
8896  #define GPIO_OTYPER_OT11_Pos             (11U)
8897  #define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
8898  #define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk
8899  #define GPIO_OTYPER_OT12_Pos             (12U)
8900  #define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
8901  #define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk
8902  #define GPIO_OTYPER_OT13_Pos             (13U)
8903  #define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
8904  #define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk
8905  #define GPIO_OTYPER_OT14_Pos             (14U)
8906  #define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
8907  #define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk
8908  #define GPIO_OTYPER_OT15_Pos             (15U)
8909  #define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
8910  #define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk
8911  
8912  /* Legacy defines */
8913  #define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
8914  #define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
8915  #define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
8916  #define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
8917  #define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
8918  #define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
8919  #define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
8920  #define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
8921  #define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
8922  #define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
8923  #define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
8924  #define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
8925  #define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
8926  #define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
8927  #define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
8928  #define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
8929  
8930  /******************  Bits definition for GPIO_OSPEEDR register  ***************/
8931  #define GPIO_OSPEEDR_OSPEED0_Pos         (0U)
8932  #define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
8933  #define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk
8934  #define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
8935  #define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
8936  #define GPIO_OSPEEDR_OSPEED1_Pos         (2U)
8937  #define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
8938  #define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk
8939  #define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
8940  #define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
8941  #define GPIO_OSPEEDR_OSPEED2_Pos         (4U)
8942  #define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
8943  #define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk
8944  #define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
8945  #define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
8946  #define GPIO_OSPEEDR_OSPEED3_Pos         (6U)
8947  #define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
8948  #define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk
8949  #define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
8950  #define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
8951  #define GPIO_OSPEEDR_OSPEED4_Pos         (8U)
8952  #define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
8953  #define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk
8954  #define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
8955  #define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
8956  #define GPIO_OSPEEDR_OSPEED5_Pos         (10U)
8957  #define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
8958  #define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk
8959  #define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
8960  #define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
8961  #define GPIO_OSPEEDR_OSPEED6_Pos         (12U)
8962  #define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
8963  #define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk
8964  #define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
8965  #define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
8966  #define GPIO_OSPEEDR_OSPEED7_Pos         (14U)
8967  #define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
8968  #define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk
8969  #define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
8970  #define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
8971  #define GPIO_OSPEEDR_OSPEED8_Pos         (16U)
8972  #define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
8973  #define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk
8974  #define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
8975  #define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
8976  #define GPIO_OSPEEDR_OSPEED9_Pos         (18U)
8977  #define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
8978  #define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk
8979  #define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
8980  #define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
8981  #define GPIO_OSPEEDR_OSPEED10_Pos        (20U)
8982  #define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
8983  #define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk
8984  #define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
8985  #define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
8986  #define GPIO_OSPEEDR_OSPEED11_Pos        (22U)
8987  #define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
8988  #define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk
8989  #define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
8990  #define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
8991  #define GPIO_OSPEEDR_OSPEED12_Pos        (24U)
8992  #define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
8993  #define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk
8994  #define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
8995  #define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
8996  #define GPIO_OSPEEDR_OSPEED13_Pos        (26U)
8997  #define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
8998  #define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk
8999  #define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
9000  #define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
9001  #define GPIO_OSPEEDR_OSPEED14_Pos        (28U)
9002  #define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
9003  #define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk
9004  #define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
9005  #define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
9006  #define GPIO_OSPEEDR_OSPEED15_Pos        (30U)
9007  #define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
9008  #define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk
9009  #define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
9010  #define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
9011  
9012  /* Legacy defines */
9013  #define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
9014  #define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
9015  #define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
9016  #define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
9017  #define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
9018  #define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
9019  #define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
9020  #define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
9021  #define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
9022  #define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
9023  #define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
9024  #define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
9025  #define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
9026  #define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
9027  #define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
9028  #define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
9029  #define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
9030  #define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
9031  #define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
9032  #define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
9033  #define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
9034  #define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
9035  #define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
9036  #define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
9037  #define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
9038  #define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
9039  #define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
9040  #define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
9041  #define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
9042  #define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
9043  #define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
9044  #define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
9045  #define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
9046  #define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
9047  #define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
9048  #define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
9049  #define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
9050  #define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
9051  #define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
9052  #define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
9053  #define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
9054  #define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
9055  #define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
9056  #define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
9057  #define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
9058  #define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
9059  #define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
9060  #define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
9061  
9062  /******************  Bits definition for GPIO_PUPDR register  *****************/
9063  #define GPIO_PUPDR_PUPD0_Pos             (0U)
9064  #define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
9065  #define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk
9066  #define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
9067  #define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
9068  #define GPIO_PUPDR_PUPD1_Pos             (2U)
9069  #define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
9070  #define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk
9071  #define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
9072  #define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
9073  #define GPIO_PUPDR_PUPD2_Pos             (4U)
9074  #define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
9075  #define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk
9076  #define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
9077  #define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
9078  #define GPIO_PUPDR_PUPD3_Pos             (6U)
9079  #define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
9080  #define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk
9081  #define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
9082  #define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
9083  #define GPIO_PUPDR_PUPD4_Pos             (8U)
9084  #define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
9085  #define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk
9086  #define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
9087  #define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
9088  #define GPIO_PUPDR_PUPD5_Pos             (10U)
9089  #define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
9090  #define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk
9091  #define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
9092  #define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
9093  #define GPIO_PUPDR_PUPD6_Pos             (12U)
9094  #define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
9095  #define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk
9096  #define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
9097  #define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
9098  #define GPIO_PUPDR_PUPD7_Pos             (14U)
9099  #define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
9100  #define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk
9101  #define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
9102  #define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
9103  #define GPIO_PUPDR_PUPD8_Pos             (16U)
9104  #define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
9105  #define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk
9106  #define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
9107  #define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
9108  #define GPIO_PUPDR_PUPD9_Pos             (18U)
9109  #define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
9110  #define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk
9111  #define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
9112  #define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
9113  #define GPIO_PUPDR_PUPD10_Pos            (20U)
9114  #define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
9115  #define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk
9116  #define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
9117  #define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
9118  #define GPIO_PUPDR_PUPD11_Pos            (22U)
9119  #define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
9120  #define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk
9121  #define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
9122  #define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
9123  #define GPIO_PUPDR_PUPD12_Pos            (24U)
9124  #define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
9125  #define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk
9126  #define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
9127  #define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
9128  #define GPIO_PUPDR_PUPD13_Pos            (26U)
9129  #define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
9130  #define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk
9131  #define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
9132  #define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
9133  #define GPIO_PUPDR_PUPD14_Pos            (28U)
9134  #define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
9135  #define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk
9136  #define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
9137  #define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
9138  #define GPIO_PUPDR_PUPD15_Pos            (30U)
9139  #define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
9140  #define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk
9141  #define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
9142  #define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
9143  
9144  /* Legacy defines */
9145  #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
9146  #define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
9147  #define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
9148  #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
9149  #define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
9150  #define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
9151  #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
9152  #define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
9153  #define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
9154  #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
9155  #define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
9156  #define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
9157  #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
9158  #define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
9159  #define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
9160  #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
9161  #define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
9162  #define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
9163  #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
9164  #define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
9165  #define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
9166  #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
9167  #define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
9168  #define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
9169  #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
9170  #define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
9171  #define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
9172  #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
9173  #define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
9174  #define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
9175  #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
9176  #define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
9177  #define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
9178  #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
9179  #define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
9180  #define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
9181  #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
9182  #define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
9183  #define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
9184  #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
9185  #define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
9186  #define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
9187  #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
9188  #define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
9189  #define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
9190  #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
9191  #define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
9192  #define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
9193  
9194  /******************  Bits definition for GPIO_IDR register  *******************/
9195  #define GPIO_IDR_ID0_Pos                 (0U)
9196  #define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
9197  #define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk
9198  #define GPIO_IDR_ID1_Pos                 (1U)
9199  #define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
9200  #define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk
9201  #define GPIO_IDR_ID2_Pos                 (2U)
9202  #define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
9203  #define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk
9204  #define GPIO_IDR_ID3_Pos                 (3U)
9205  #define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
9206  #define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk
9207  #define GPIO_IDR_ID4_Pos                 (4U)
9208  #define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
9209  #define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk
9210  #define GPIO_IDR_ID5_Pos                 (5U)
9211  #define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
9212  #define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk
9213  #define GPIO_IDR_ID6_Pos                 (6U)
9214  #define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
9215  #define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk
9216  #define GPIO_IDR_ID7_Pos                 (7U)
9217  #define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
9218  #define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk
9219  #define GPIO_IDR_ID8_Pos                 (8U)
9220  #define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
9221  #define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk
9222  #define GPIO_IDR_ID9_Pos                 (9U)
9223  #define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
9224  #define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk
9225  #define GPIO_IDR_ID10_Pos                (10U)
9226  #define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
9227  #define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk
9228  #define GPIO_IDR_ID11_Pos                (11U)
9229  #define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
9230  #define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk
9231  #define GPIO_IDR_ID12_Pos                (12U)
9232  #define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
9233  #define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk
9234  #define GPIO_IDR_ID13_Pos                (13U)
9235  #define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
9236  #define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk
9237  #define GPIO_IDR_ID14_Pos                (14U)
9238  #define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
9239  #define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk
9240  #define GPIO_IDR_ID15_Pos                (15U)
9241  #define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
9242  #define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk
9243  
9244  /* Legacy defines */
9245  #define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
9246  #define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
9247  #define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
9248  #define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
9249  #define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
9250  #define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
9251  #define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
9252  #define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
9253  #define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
9254  #define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
9255  #define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
9256  #define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
9257  #define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
9258  #define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
9259  #define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
9260  #define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
9261  
9262  /******************  Bits definition for GPIO_ODR register  *******************/
9263  #define GPIO_ODR_OD0_Pos                 (0U)
9264  #define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
9265  #define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk
9266  #define GPIO_ODR_OD1_Pos                 (1U)
9267  #define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
9268  #define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk
9269  #define GPIO_ODR_OD2_Pos                 (2U)
9270  #define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
9271  #define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk
9272  #define GPIO_ODR_OD3_Pos                 (3U)
9273  #define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
9274  #define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk
9275  #define GPIO_ODR_OD4_Pos                 (4U)
9276  #define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
9277  #define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk
9278  #define GPIO_ODR_OD5_Pos                 (5U)
9279  #define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
9280  #define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk
9281  #define GPIO_ODR_OD6_Pos                 (6U)
9282  #define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
9283  #define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk
9284  #define GPIO_ODR_OD7_Pos                 (7U)
9285  #define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
9286  #define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk
9287  #define GPIO_ODR_OD8_Pos                 (8U)
9288  #define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
9289  #define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk
9290  #define GPIO_ODR_OD9_Pos                 (9U)
9291  #define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
9292  #define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk
9293  #define GPIO_ODR_OD10_Pos                (10U)
9294  #define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
9295  #define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk
9296  #define GPIO_ODR_OD11_Pos                (11U)
9297  #define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
9298  #define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk
9299  #define GPIO_ODR_OD12_Pos                (12U)
9300  #define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
9301  #define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk
9302  #define GPIO_ODR_OD13_Pos                (13U)
9303  #define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
9304  #define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk
9305  #define GPIO_ODR_OD14_Pos                (14U)
9306  #define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
9307  #define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk
9308  #define GPIO_ODR_OD15_Pos                (15U)
9309  #define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
9310  #define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk
9311  /* Legacy defines */
9312  #define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
9313  #define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
9314  #define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
9315  #define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
9316  #define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
9317  #define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
9318  #define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
9319  #define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
9320  #define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
9321  #define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
9322  #define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
9323  #define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
9324  #define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
9325  #define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
9326  #define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
9327  #define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
9328  
9329  /******************  Bits definition for GPIO_BSRR register  ******************/
9330  #define GPIO_BSRR_BS0_Pos                (0U)
9331  #define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
9332  #define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk
9333  #define GPIO_BSRR_BS1_Pos                (1U)
9334  #define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
9335  #define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk
9336  #define GPIO_BSRR_BS2_Pos                (2U)
9337  #define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
9338  #define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk
9339  #define GPIO_BSRR_BS3_Pos                (3U)
9340  #define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
9341  #define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk
9342  #define GPIO_BSRR_BS4_Pos                (4U)
9343  #define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
9344  #define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk
9345  #define GPIO_BSRR_BS5_Pos                (5U)
9346  #define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
9347  #define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk
9348  #define GPIO_BSRR_BS6_Pos                (6U)
9349  #define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
9350  #define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk
9351  #define GPIO_BSRR_BS7_Pos                (7U)
9352  #define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
9353  #define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk
9354  #define GPIO_BSRR_BS8_Pos                (8U)
9355  #define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
9356  #define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk
9357  #define GPIO_BSRR_BS9_Pos                (9U)
9358  #define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
9359  #define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk
9360  #define GPIO_BSRR_BS10_Pos               (10U)
9361  #define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
9362  #define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk
9363  #define GPIO_BSRR_BS11_Pos               (11U)
9364  #define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
9365  #define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk
9366  #define GPIO_BSRR_BS12_Pos               (12U)
9367  #define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
9368  #define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk
9369  #define GPIO_BSRR_BS13_Pos               (13U)
9370  #define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
9371  #define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk
9372  #define GPIO_BSRR_BS14_Pos               (14U)
9373  #define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
9374  #define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk
9375  #define GPIO_BSRR_BS15_Pos               (15U)
9376  #define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
9377  #define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk
9378  #define GPIO_BSRR_BR0_Pos                (16U)
9379  #define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
9380  #define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk
9381  #define GPIO_BSRR_BR1_Pos                (17U)
9382  #define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
9383  #define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk
9384  #define GPIO_BSRR_BR2_Pos                (18U)
9385  #define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
9386  #define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk
9387  #define GPIO_BSRR_BR3_Pos                (19U)
9388  #define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
9389  #define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk
9390  #define GPIO_BSRR_BR4_Pos                (20U)
9391  #define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
9392  #define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk
9393  #define GPIO_BSRR_BR5_Pos                (21U)
9394  #define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
9395  #define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk
9396  #define GPIO_BSRR_BR6_Pos                (22U)
9397  #define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
9398  #define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk
9399  #define GPIO_BSRR_BR7_Pos                (23U)
9400  #define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
9401  #define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk
9402  #define GPIO_BSRR_BR8_Pos                (24U)
9403  #define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
9404  #define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk
9405  #define GPIO_BSRR_BR9_Pos                (25U)
9406  #define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
9407  #define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk
9408  #define GPIO_BSRR_BR10_Pos               (26U)
9409  #define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
9410  #define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk
9411  #define GPIO_BSRR_BR11_Pos               (27U)
9412  #define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
9413  #define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk
9414  #define GPIO_BSRR_BR12_Pos               (28U)
9415  #define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
9416  #define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk
9417  #define GPIO_BSRR_BR13_Pos               (29U)
9418  #define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
9419  #define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk
9420  #define GPIO_BSRR_BR14_Pos               (30U)
9421  #define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
9422  #define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk
9423  #define GPIO_BSRR_BR15_Pos               (31U)
9424  #define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
9425  #define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk
9426  
9427  /* Legacy defines */
9428  #define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
9429  #define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
9430  #define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
9431  #define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
9432  #define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
9433  #define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
9434  #define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
9435  #define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
9436  #define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
9437  #define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
9438  #define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
9439  #define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
9440  #define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
9441  #define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
9442  #define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
9443  #define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
9444  #define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
9445  #define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
9446  #define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
9447  #define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
9448  #define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
9449  #define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
9450  #define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
9451  #define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
9452  #define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
9453  #define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
9454  #define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
9455  #define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
9456  #define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
9457  #define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
9458  #define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
9459  #define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
9460  #define GPIO_BRR_BR0                     GPIO_BSRR_BR0
9461  #define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
9462  #define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
9463  #define GPIO_BRR_BR1                     GPIO_BSRR_BR1
9464  #define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
9465  #define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
9466  #define GPIO_BRR_BR2                     GPIO_BSRR_BR2
9467  #define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
9468  #define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
9469  #define GPIO_BRR_BR3                     GPIO_BSRR_BR3
9470  #define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
9471  #define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
9472  #define GPIO_BRR_BR4                     GPIO_BSRR_BR4
9473  #define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
9474  #define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
9475  #define GPIO_BRR_BR5                     GPIO_BSRR_BR5
9476  #define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
9477  #define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
9478  #define GPIO_BRR_BR6                     GPIO_BSRR_BR6
9479  #define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
9480  #define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
9481  #define GPIO_BRR_BR7                     GPIO_BSRR_BR7
9482  #define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
9483  #define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
9484  #define GPIO_BRR_BR8                     GPIO_BSRR_BR8
9485  #define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
9486  #define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
9487  #define GPIO_BRR_BR9                     GPIO_BSRR_BR9
9488  #define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
9489  #define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
9490  #define GPIO_BRR_BR10                    GPIO_BSRR_BR10
9491  #define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
9492  #define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
9493  #define GPIO_BRR_BR11                    GPIO_BSRR_BR11
9494  #define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
9495  #define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
9496  #define GPIO_BRR_BR12                    GPIO_BSRR_BR12
9497  #define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
9498  #define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
9499  #define GPIO_BRR_BR13                    GPIO_BSRR_BR13
9500  #define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
9501  #define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
9502  #define GPIO_BRR_BR14                    GPIO_BSRR_BR14
9503  #define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
9504  #define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
9505  #define GPIO_BRR_BR15                    GPIO_BSRR_BR15
9506  #define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
9507  #define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk
9508  /****************** Bit definition for GPIO_LCKR register *********************/
9509  #define GPIO_LCKR_LCK0_Pos               (0U)
9510  #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
9511  #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
9512  #define GPIO_LCKR_LCK1_Pos               (1U)
9513  #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
9514  #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
9515  #define GPIO_LCKR_LCK2_Pos               (2U)
9516  #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
9517  #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
9518  #define GPIO_LCKR_LCK3_Pos               (3U)
9519  #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
9520  #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
9521  #define GPIO_LCKR_LCK4_Pos               (4U)
9522  #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
9523  #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
9524  #define GPIO_LCKR_LCK5_Pos               (5U)
9525  #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
9526  #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
9527  #define GPIO_LCKR_LCK6_Pos               (6U)
9528  #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
9529  #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
9530  #define GPIO_LCKR_LCK7_Pos               (7U)
9531  #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
9532  #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
9533  #define GPIO_LCKR_LCK8_Pos               (8U)
9534  #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
9535  #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
9536  #define GPIO_LCKR_LCK9_Pos               (9U)
9537  #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
9538  #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
9539  #define GPIO_LCKR_LCK10_Pos              (10U)
9540  #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
9541  #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
9542  #define GPIO_LCKR_LCK11_Pos              (11U)
9543  #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
9544  #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
9545  #define GPIO_LCKR_LCK12_Pos              (12U)
9546  #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
9547  #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
9548  #define GPIO_LCKR_LCK13_Pos              (13U)
9549  #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
9550  #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
9551  #define GPIO_LCKR_LCK14_Pos              (14U)
9552  #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
9553  #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
9554  #define GPIO_LCKR_LCK15_Pos              (15U)
9555  #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
9556  #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
9557  #define GPIO_LCKR_LCKK_Pos               (16U)
9558  #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
9559  #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
9560  /****************** Bit definition for GPIO_AFRL register *********************/
9561  #define GPIO_AFRL_AFSEL0_Pos             (0U)
9562  #define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
9563  #define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk
9564  #define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
9565  #define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
9566  #define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
9567  #define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
9568  #define GPIO_AFRL_AFSEL1_Pos             (4U)
9569  #define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
9570  #define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk
9571  #define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
9572  #define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
9573  #define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
9574  #define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
9575  #define GPIO_AFRL_AFSEL2_Pos             (8U)
9576  #define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
9577  #define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk
9578  #define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
9579  #define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
9580  #define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
9581  #define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
9582  #define GPIO_AFRL_AFSEL3_Pos             (12U)
9583  #define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
9584  #define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk
9585  #define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
9586  #define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
9587  #define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
9588  #define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
9589  #define GPIO_AFRL_AFSEL4_Pos             (16U)
9590  #define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
9591  #define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk
9592  #define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
9593  #define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
9594  #define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
9595  #define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
9596  #define GPIO_AFRL_AFSEL5_Pos             (20U)
9597  #define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
9598  #define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk
9599  #define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
9600  #define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
9601  #define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
9602  #define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
9603  #define GPIO_AFRL_AFSEL6_Pos             (24U)
9604  #define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
9605  #define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk
9606  #define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
9607  #define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
9608  #define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
9609  #define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
9610  #define GPIO_AFRL_AFSEL7_Pos             (28U)
9611  #define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
9612  #define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk
9613  #define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
9614  #define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
9615  #define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
9616  #define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
9617  
9618  /* Legacy defines */
9619  #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
9620  #define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
9621  #define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
9622  #define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
9623  #define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
9624  #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
9625  #define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
9626  #define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
9627  #define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
9628  #define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
9629  #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
9630  #define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
9631  #define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
9632  #define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
9633  #define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
9634  #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
9635  #define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
9636  #define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
9637  #define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
9638  #define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
9639  #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
9640  #define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
9641  #define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
9642  #define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
9643  #define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
9644  #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
9645  #define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
9646  #define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
9647  #define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
9648  #define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
9649  #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
9650  #define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
9651  #define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
9652  #define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
9653  #define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
9654  #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
9655  #define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
9656  #define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
9657  #define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
9658  #define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
9659  
9660  /****************** Bit definition for GPIO_AFRH register *********************/
9661  #define GPIO_AFRH_AFSEL8_Pos             (0U)
9662  #define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
9663  #define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk
9664  #define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
9665  #define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
9666  #define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
9667  #define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
9668  #define GPIO_AFRH_AFSEL9_Pos             (4U)
9669  #define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
9670  #define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk
9671  #define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
9672  #define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
9673  #define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
9674  #define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
9675  #define GPIO_AFRH_AFSEL10_Pos            (8U)
9676  #define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
9677  #define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk
9678  #define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
9679  #define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
9680  #define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
9681  #define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
9682  #define GPIO_AFRH_AFSEL11_Pos            (12U)
9683  #define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
9684  #define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk
9685  #define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
9686  #define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
9687  #define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
9688  #define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
9689  #define GPIO_AFRH_AFSEL12_Pos            (16U)
9690  #define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
9691  #define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk
9692  #define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
9693  #define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
9694  #define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
9695  #define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
9696  #define GPIO_AFRH_AFSEL13_Pos            (20U)
9697  #define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
9698  #define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk
9699  #define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
9700  #define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
9701  #define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
9702  #define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
9703  #define GPIO_AFRH_AFSEL14_Pos            (24U)
9704  #define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
9705  #define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk
9706  #define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
9707  #define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
9708  #define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
9709  #define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
9710  #define GPIO_AFRH_AFSEL15_Pos            (28U)
9711  #define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
9712  #define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk
9713  #define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
9714  #define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
9715  #define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
9716  #define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
9717  
9718  /* Legacy defines */
9719  #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
9720  #define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
9721  #define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
9722  #define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
9723  #define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
9724  #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
9725  #define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
9726  #define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
9727  #define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
9728  #define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
9729  #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
9730  #define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
9731  #define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
9732  #define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
9733  #define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
9734  #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
9735  #define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
9736  #define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
9737  #define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
9738  #define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
9739  #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
9740  #define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
9741  #define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
9742  #define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
9743  #define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
9744  #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
9745  #define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
9746  #define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
9747  #define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
9748  #define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
9749  #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
9750  #define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
9751  #define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
9752  #define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
9753  #define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
9754  #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
9755  #define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
9756  #define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
9757  #define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
9758  #define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
9759  
9760  
9761  /******************************************************************************/
9762  /*                                                                            */
9763  /*                      Inter-integrated Circuit Interface                    */
9764  /*                                                                            */
9765  /******************************************************************************/
9766  /*******************  Bit definition for I2C_CR1 register  ********************/
9767  #define I2C_CR1_PE_Pos            (0U)
9768  #define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
9769  #define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
9770  #define I2C_CR1_SMBUS_Pos         (1U)
9771  #define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
9772  #define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
9773  #define I2C_CR1_SMBTYPE_Pos       (3U)
9774  #define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
9775  #define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
9776  #define I2C_CR1_ENARP_Pos         (4U)
9777  #define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
9778  #define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
9779  #define I2C_CR1_ENPEC_Pos         (5U)
9780  #define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
9781  #define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
9782  #define I2C_CR1_ENGC_Pos          (6U)
9783  #define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
9784  #define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
9785  #define I2C_CR1_NOSTRETCH_Pos     (7U)
9786  #define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
9787  #define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
9788  #define I2C_CR1_START_Pos         (8U)
9789  #define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
9790  #define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
9791  #define I2C_CR1_STOP_Pos          (9U)
9792  #define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
9793  #define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
9794  #define I2C_CR1_ACK_Pos           (10U)
9795  #define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
9796  #define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
9797  #define I2C_CR1_POS_Pos           (11U)
9798  #define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
9799  #define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
9800  #define I2C_CR1_PEC_Pos           (12U)
9801  #define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
9802  #define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
9803  #define I2C_CR1_ALERT_Pos         (13U)
9804  #define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
9805  #define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
9806  #define I2C_CR1_SWRST_Pos         (15U)
9807  #define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
9808  #define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
9809  
9810  /*******************  Bit definition for I2C_CR2 register  ********************/
9811  #define I2C_CR2_FREQ_Pos          (0U)
9812  #define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
9813  #define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
9814  #define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
9815  #define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
9816  #define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
9817  #define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
9818  #define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
9819  #define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
9820  
9821  #define I2C_CR2_ITERREN_Pos       (8U)
9822  #define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
9823  #define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
9824  #define I2C_CR2_ITEVTEN_Pos       (9U)
9825  #define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
9826  #define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
9827  #define I2C_CR2_ITBUFEN_Pos       (10U)
9828  #define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
9829  #define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
9830  #define I2C_CR2_DMAEN_Pos         (11U)
9831  #define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
9832  #define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
9833  #define I2C_CR2_LAST_Pos          (12U)
9834  #define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
9835  #define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
9836  
9837  /*******************  Bit definition for I2C_OAR1 register  *******************/
9838  #define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
9839  #define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
9840  
9841  #define I2C_OAR1_ADD0_Pos         (0U)
9842  #define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
9843  #define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
9844  #define I2C_OAR1_ADD1_Pos         (1U)
9845  #define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
9846  #define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
9847  #define I2C_OAR1_ADD2_Pos         (2U)
9848  #define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
9849  #define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
9850  #define I2C_OAR1_ADD3_Pos         (3U)
9851  #define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
9852  #define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
9853  #define I2C_OAR1_ADD4_Pos         (4U)
9854  #define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
9855  #define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
9856  #define I2C_OAR1_ADD5_Pos         (5U)
9857  #define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
9858  #define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
9859  #define I2C_OAR1_ADD6_Pos         (6U)
9860  #define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
9861  #define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
9862  #define I2C_OAR1_ADD7_Pos         (7U)
9863  #define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
9864  #define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
9865  #define I2C_OAR1_ADD8_Pos         (8U)
9866  #define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
9867  #define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
9868  #define I2C_OAR1_ADD9_Pos         (9U)
9869  #define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
9870  #define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
9871  
9872  #define I2C_OAR1_ADDMODE_Pos      (15U)
9873  #define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
9874  #define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
9875  
9876  /*******************  Bit definition for I2C_OAR2 register  *******************/
9877  #define I2C_OAR2_ENDUAL_Pos       (0U)
9878  #define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
9879  #define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
9880  #define I2C_OAR2_ADD2_Pos         (1U)
9881  #define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
9882  #define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
9883  
9884  /********************  Bit definition for I2C_DR register  ********************/
9885  #define I2C_DR_DR_Pos             (0U)
9886  #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
9887  #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
9888  
9889  /*******************  Bit definition for I2C_SR1 register  ********************/
9890  #define I2C_SR1_SB_Pos            (0U)
9891  #define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
9892  #define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
9893  #define I2C_SR1_ADDR_Pos          (1U)
9894  #define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
9895  #define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
9896  #define I2C_SR1_BTF_Pos           (2U)
9897  #define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
9898  #define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
9899  #define I2C_SR1_ADD10_Pos         (3U)
9900  #define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
9901  #define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
9902  #define I2C_SR1_STOPF_Pos         (4U)
9903  #define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
9904  #define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
9905  #define I2C_SR1_RXNE_Pos          (6U)
9906  #define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
9907  #define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
9908  #define I2C_SR1_TXE_Pos           (7U)
9909  #define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
9910  #define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
9911  #define I2C_SR1_BERR_Pos          (8U)
9912  #define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
9913  #define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
9914  #define I2C_SR1_ARLO_Pos          (9U)
9915  #define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
9916  #define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
9917  #define I2C_SR1_AF_Pos            (10U)
9918  #define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
9919  #define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
9920  #define I2C_SR1_OVR_Pos           (11U)
9921  #define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
9922  #define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
9923  #define I2C_SR1_PECERR_Pos        (12U)
9924  #define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
9925  #define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
9926  #define I2C_SR1_TIMEOUT_Pos       (14U)
9927  #define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
9928  #define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
9929  #define I2C_SR1_SMBALERT_Pos      (15U)
9930  #define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
9931  #define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
9932  
9933  /*******************  Bit definition for I2C_SR2 register  ********************/
9934  #define I2C_SR2_MSL_Pos           (0U)
9935  #define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
9936  #define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
9937  #define I2C_SR2_BUSY_Pos          (1U)
9938  #define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
9939  #define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
9940  #define I2C_SR2_TRA_Pos           (2U)
9941  #define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
9942  #define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
9943  #define I2C_SR2_GENCALL_Pos       (4U)
9944  #define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
9945  #define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
9946  #define I2C_SR2_SMBDEFAULT_Pos    (5U)
9947  #define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
9948  #define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
9949  #define I2C_SR2_SMBHOST_Pos       (6U)
9950  #define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
9951  #define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
9952  #define I2C_SR2_DUALF_Pos         (7U)
9953  #define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
9954  #define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
9955  #define I2C_SR2_PEC_Pos           (8U)
9956  #define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
9957  #define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
9958  
9959  /*******************  Bit definition for I2C_CCR register  ********************/
9960  #define I2C_CCR_CCR_Pos           (0U)
9961  #define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
9962  #define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
9963  #define I2C_CCR_DUTY_Pos          (14U)
9964  #define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
9965  #define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
9966  #define I2C_CCR_FS_Pos            (15U)
9967  #define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
9968  #define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
9969  
9970  /******************  Bit definition for I2C_TRISE register  *******************/
9971  #define I2C_TRISE_TRISE_Pos       (0U)
9972  #define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
9973  #define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
9974  
9975  /******************  Bit definition for I2C_FLTR register  *******************/
9976  #define I2C_FLTR_DNF_Pos          (0U)
9977  #define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */
9978  #define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */
9979  #define I2C_FLTR_ANOFF_Pos        (4U)
9980  #define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */
9981  #define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */
9982  
9983  /******************************************************************************/
9984  /*                                                                            */
9985  /*                           Independent WATCHDOG                             */
9986  /*                                                                            */
9987  /******************************************************************************/
9988  /*******************  Bit definition for IWDG_KR register  ********************/
9989  #define IWDG_KR_KEY_Pos     (0U)
9990  #define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
9991  #define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
9992  
9993  /*******************  Bit definition for IWDG_PR register  ********************/
9994  #define IWDG_PR_PR_Pos      (0U)
9995  #define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
9996  #define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
9997  #define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
9998  #define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
9999  #define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
10000  
10001  /*******************  Bit definition for IWDG_RLR register  *******************/
10002  #define IWDG_RLR_RL_Pos     (0U)
10003  #define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
10004  #define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
10005  
10006  /*******************  Bit definition for IWDG_SR register  ********************/
10007  #define IWDG_SR_PVU_Pos     (0U)
10008  #define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
10009  #define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
10010  #define IWDG_SR_RVU_Pos     (1U)
10011  #define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
10012  #define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
10013  
10014  
10015  
10016  /******************************************************************************/
10017  /*                                                                            */
10018  /*                             Power Control                                  */
10019  /*                                                                            */
10020  /******************************************************************************/
10021  /********************  Bit definition for PWR_CR register  ********************/
10022  #define PWR_CR_LPDS_Pos        (0U)
10023  #define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
10024  #define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
10025  #define PWR_CR_PDDS_Pos        (1U)
10026  #define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
10027  #define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
10028  #define PWR_CR_CWUF_Pos        (2U)
10029  #define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
10030  #define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
10031  #define PWR_CR_CSBF_Pos        (3U)
10032  #define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
10033  #define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
10034  #define PWR_CR_PVDE_Pos        (4U)
10035  #define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
10036  #define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
10037  
10038  #define PWR_CR_PLS_Pos         (5U)
10039  #define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
10040  #define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
10041  #define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
10042  #define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
10043  #define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
10044  
10045  /*!< PVD level configuration */
10046  #define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
10047  #define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
10048  #define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
10049  #define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
10050  #define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
10051  #define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
10052  #define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
10053  #define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
10054  #define PWR_CR_DBP_Pos         (8U)
10055  #define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
10056  #define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
10057  #define PWR_CR_FPDS_Pos        (9U)
10058  #define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
10059  #define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
10060  #define PWR_CR_LPLVDS_Pos      (10U)
10061  #define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */
10062  #define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
10063  #define PWR_CR_MRLVDS_Pos      (11U)
10064  #define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */
10065  #define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */
10066  #define PWR_CR_ADCDC1_Pos      (13U)
10067  #define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */
10068  #define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */
10069  #define PWR_CR_VOS_Pos         (14U)
10070  #define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */
10071  #define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10072  #define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */
10073  #define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */
10074  #define PWR_CR_ODEN_Pos        (16U)
10075  #define PWR_CR_ODEN_Msk        (0x1UL << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */
10076  #define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */
10077  #define PWR_CR_ODSWEN_Pos      (17U)
10078  #define PWR_CR_ODSWEN_Msk      (0x1UL << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */
10079  #define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */
10080  #define PWR_CR_UDEN_Pos        (18U)
10081  #define PWR_CR_UDEN_Msk        (0x3UL << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */
10082  #define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */
10083  #define PWR_CR_UDEN_0          (0x1UL << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */
10084  #define PWR_CR_UDEN_1          (0x2UL << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */
10085  
10086  /* Legacy define */
10087  #define  PWR_CR_PMODE                        PWR_CR_VOS
10088  #define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
10089  #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
10090  
10091  /*******************  Bit definition for PWR_CSR register  ********************/
10092  #define PWR_CSR_WUF_Pos        (0U)
10093  #define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
10094  #define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
10095  #define PWR_CSR_SBF_Pos        (1U)
10096  #define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
10097  #define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
10098  #define PWR_CSR_PVDO_Pos       (2U)
10099  #define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
10100  #define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
10101  #define PWR_CSR_BRR_Pos        (3U)
10102  #define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
10103  #define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
10104  #define PWR_CSR_EWUP_Pos       (8U)
10105  #define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */
10106  #define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */
10107  #define PWR_CSR_BRE_Pos        (9U)
10108  #define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
10109  #define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
10110  #define PWR_CSR_VOSRDY_Pos     (14U)
10111  #define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
10112  #define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
10113  #define PWR_CSR_ODRDY_Pos      (16U)
10114  #define PWR_CSR_ODRDY_Msk      (0x1UL << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */
10115  #define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */
10116  #define PWR_CSR_ODSWRDY_Pos    (17U)
10117  #define PWR_CSR_ODSWRDY_Msk    (0x1UL << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */
10118  #define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */
10119  #define PWR_CSR_UDRDY_Pos      (18U)
10120  #define PWR_CSR_UDRDY_Msk      (0x3UL << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */
10121  #define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */
10122  /* Legacy define */
10123  #define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY
10124  
10125  /* Legacy define */
10126  #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
10127  
10128  /******************************************************************************/
10129  /*                                                                            */
10130  /*                         Reset and Clock Control                            */
10131  /*                                                                            */
10132  /******************************************************************************/
10133  /********************  Bit definition for RCC_CR register  ********************/
10134  #define RCC_CR_HSION_Pos                   (0U)
10135  #define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
10136  #define RCC_CR_HSION                       RCC_CR_HSION_Msk
10137  #define RCC_CR_HSIRDY_Pos                  (1U)
10138  #define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
10139  #define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk
10140  
10141  #define RCC_CR_HSITRIM_Pos                 (3U)
10142  #define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
10143  #define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk
10144  #define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
10145  #define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
10146  #define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
10147  #define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
10148  #define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
10149  
10150  #define RCC_CR_HSICAL_Pos                  (8U)
10151  #define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
10152  #define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk
10153  #define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
10154  #define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
10155  #define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
10156  #define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
10157  #define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
10158  #define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
10159  #define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
10160  #define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
10161  
10162  #define RCC_CR_HSEON_Pos                   (16U)
10163  #define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
10164  #define RCC_CR_HSEON                       RCC_CR_HSEON_Msk
10165  #define RCC_CR_HSERDY_Pos                  (17U)
10166  #define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
10167  #define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk
10168  #define RCC_CR_HSEBYP_Pos                  (18U)
10169  #define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
10170  #define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk
10171  #define RCC_CR_CSSON_Pos                   (19U)
10172  #define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
10173  #define RCC_CR_CSSON                       RCC_CR_CSSON_Msk
10174  #define RCC_CR_PLLON_Pos                   (24U)
10175  #define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
10176  #define RCC_CR_PLLON                       RCC_CR_PLLON_Msk
10177  #define RCC_CR_PLLRDY_Pos                  (25U)
10178  #define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
10179  #define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk
10180  /*
10181   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10182   */
10183  #define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */
10184  
10185  #define RCC_CR_PLLI2SON_Pos                (26U)
10186  #define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
10187  #define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk
10188  #define RCC_CR_PLLI2SRDY_Pos               (27U)
10189  #define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
10190  #define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk
10191  /*
10192   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10193   */
10194  #define RCC_PLLSAI_SUPPORT                                                     /*!< Support PLLSAI oscillator */
10195  
10196  #define RCC_CR_PLLSAION_Pos                (28U)
10197  #define RCC_CR_PLLSAION_Msk                (0x1UL << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */
10198  #define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk
10199  #define RCC_CR_PLLSAIRDY_Pos               (29U)
10200  #define RCC_CR_PLLSAIRDY_Msk               (0x1UL << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */
10201  #define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk
10202  
10203  /********************  Bit definition for RCC_PLLCFGR register  ***************/
10204  #define RCC_PLLCFGR_PLLM_Pos               (0U)
10205  #define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
10206  #define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk
10207  #define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
10208  #define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
10209  #define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
10210  #define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
10211  #define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
10212  #define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
10213  
10214  #define RCC_PLLCFGR_PLLN_Pos               (6U)
10215  #define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
10216  #define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk
10217  #define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
10218  #define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
10219  #define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
10220  #define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
10221  #define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
10222  #define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
10223  #define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
10224  #define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
10225  #define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
10226  
10227  #define RCC_PLLCFGR_PLLP_Pos               (16U)
10228  #define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
10229  #define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk
10230  #define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
10231  #define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
10232  
10233  #define RCC_PLLCFGR_PLLSRC_Pos             (22U)
10234  #define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
10235  #define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk
10236  #define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)
10237  #define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
10238  #define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk
10239  #define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U
10240  
10241  #define RCC_PLLCFGR_PLLQ_Pos               (24U)
10242  #define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
10243  #define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk
10244  #define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
10245  #define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
10246  #define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
10247  #define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
10248  
10249  
10250  /********************  Bit definition for RCC_CFGR register  ******************/
10251  /*!< SW configuration */
10252  #define RCC_CFGR_SW_Pos                    (0U)
10253  #define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
10254  #define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
10255  #define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
10256  #define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
10257  
10258  #define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
10259  #define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
10260  #define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
10261  
10262  /*!< SWS configuration */
10263  #define RCC_CFGR_SWS_Pos                   (2U)
10264  #define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
10265  #define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
10266  #define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
10267  #define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
10268  
10269  #define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
10270  #define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
10271  #define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
10272  
10273  /*!< HPRE configuration */
10274  #define RCC_CFGR_HPRE_Pos                  (4U)
10275  #define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
10276  #define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
10277  #define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
10278  #define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
10279  #define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
10280  #define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
10281  
10282  #define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
10283  #define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
10284  #define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
10285  #define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
10286  #define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
10287  #define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
10288  #define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
10289  #define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
10290  #define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
10291  
10292  /*!< PPRE1 configuration */
10293  #define RCC_CFGR_PPRE1_Pos                 (10U)
10294  #define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
10295  #define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
10296  #define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
10297  #define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
10298  #define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
10299  
10300  #define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
10301  #define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
10302  #define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
10303  #define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
10304  #define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
10305  
10306  /*!< PPRE2 configuration */
10307  #define RCC_CFGR_PPRE2_Pos                 (13U)
10308  #define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
10309  #define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
10310  #define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
10311  #define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
10312  #define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
10313  
10314  #define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
10315  #define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
10316  #define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
10317  #define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
10318  #define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
10319  
10320  /*!< RTCPRE configuration */
10321  #define RCC_CFGR_RTCPRE_Pos                (16U)
10322  #define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
10323  #define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk
10324  #define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
10325  #define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
10326  #define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
10327  #define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
10328  #define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
10329  
10330  /*!< MCO1 configuration */
10331  #define RCC_CFGR_MCO1_Pos                  (21U)
10332  #define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
10333  #define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk
10334  #define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
10335  #define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
10336  
10337  #define RCC_CFGR_I2SSRC_Pos                (23U)
10338  #define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
10339  #define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk
10340  
10341  #define RCC_CFGR_MCO1PRE_Pos               (24U)
10342  #define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
10343  #define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk
10344  #define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
10345  #define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
10346  #define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
10347  
10348  #define RCC_CFGR_MCO2PRE_Pos               (27U)
10349  #define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
10350  #define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk
10351  #define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
10352  #define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
10353  #define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
10354  
10355  #define RCC_CFGR_MCO2_Pos                  (30U)
10356  #define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
10357  #define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk
10358  #define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
10359  #define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
10360  
10361  /********************  Bit definition for RCC_CIR register  *******************/
10362  #define RCC_CIR_LSIRDYF_Pos                (0U)
10363  #define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
10364  #define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk
10365  #define RCC_CIR_LSERDYF_Pos                (1U)
10366  #define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
10367  #define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk
10368  #define RCC_CIR_HSIRDYF_Pos                (2U)
10369  #define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
10370  #define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk
10371  #define RCC_CIR_HSERDYF_Pos                (3U)
10372  #define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
10373  #define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk
10374  #define RCC_CIR_PLLRDYF_Pos                (4U)
10375  #define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
10376  #define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk
10377  #define RCC_CIR_PLLI2SRDYF_Pos             (5U)
10378  #define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
10379  #define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk
10380  
10381  #define RCC_CIR_PLLSAIRDYF_Pos             (6U)
10382  #define RCC_CIR_PLLSAIRDYF_Msk             (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */
10383  #define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk
10384  #define RCC_CIR_CSSF_Pos                   (7U)
10385  #define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
10386  #define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk
10387  #define RCC_CIR_LSIRDYIE_Pos               (8U)
10388  #define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
10389  #define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk
10390  #define RCC_CIR_LSERDYIE_Pos               (9U)
10391  #define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
10392  #define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk
10393  #define RCC_CIR_HSIRDYIE_Pos               (10U)
10394  #define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
10395  #define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk
10396  #define RCC_CIR_HSERDYIE_Pos               (11U)
10397  #define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
10398  #define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk
10399  #define RCC_CIR_PLLRDYIE_Pos               (12U)
10400  #define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
10401  #define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk
10402  #define RCC_CIR_PLLI2SRDYIE_Pos            (13U)
10403  #define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
10404  #define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk
10405  
10406  #define RCC_CIR_PLLSAIRDYIE_Pos            (14U)
10407  #define RCC_CIR_PLLSAIRDYIE_Msk            (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */
10408  #define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk
10409  #define RCC_CIR_LSIRDYC_Pos                (16U)
10410  #define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
10411  #define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk
10412  #define RCC_CIR_LSERDYC_Pos                (17U)
10413  #define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
10414  #define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk
10415  #define RCC_CIR_HSIRDYC_Pos                (18U)
10416  #define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
10417  #define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk
10418  #define RCC_CIR_HSERDYC_Pos                (19U)
10419  #define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
10420  #define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk
10421  #define RCC_CIR_PLLRDYC_Pos                (20U)
10422  #define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
10423  #define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk
10424  #define RCC_CIR_PLLI2SRDYC_Pos             (21U)
10425  #define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
10426  #define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk
10427  #define RCC_CIR_PLLSAIRDYC_Pos             (22U)
10428  #define RCC_CIR_PLLSAIRDYC_Msk             (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */
10429  #define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk
10430  
10431  #define RCC_CIR_CSSC_Pos                   (23U)
10432  #define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
10433  #define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk
10434  
10435  /********************  Bit definition for RCC_AHB1RSTR register  **************/
10436  #define RCC_AHB1RSTR_GPIOARST_Pos          (0U)
10437  #define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
10438  #define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk
10439  #define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)
10440  #define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
10441  #define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk
10442  #define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)
10443  #define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
10444  #define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk
10445  #define RCC_AHB1RSTR_GPIODRST_Pos          (3U)
10446  #define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
10447  #define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk
10448  #define RCC_AHB1RSTR_GPIOERST_Pos          (4U)
10449  #define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
10450  #define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk
10451  #define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)
10452  #define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
10453  #define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk
10454  #define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)
10455  #define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
10456  #define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk
10457  #define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)
10458  #define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
10459  #define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk
10460  #define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)
10461  #define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
10462  #define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk
10463  #define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)
10464  #define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
10465  #define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk
10466  #define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)
10467  #define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
10468  #define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk
10469  #define RCC_AHB1RSTR_CRCRST_Pos            (12U)
10470  #define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
10471  #define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk
10472  #define RCC_AHB1RSTR_DMA1RST_Pos           (21U)
10473  #define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
10474  #define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk
10475  #define RCC_AHB1RSTR_DMA2RST_Pos           (22U)
10476  #define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
10477  #define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk
10478  #define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)
10479  #define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
10480  #define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk
10481  #define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)
10482  #define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
10483  #define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk
10484  #define RCC_AHB1RSTR_OTGHRST_Pos           (29U)
10485  #define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
10486  #define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk
10487  
10488  /********************  Bit definition for RCC_AHB2RSTR register  **************/
10489  #define RCC_AHB2RSTR_DCMIRST_Pos           (0U)
10490  #define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
10491  #define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk
10492  #define RCC_AHB2RSTR_RNGRST_Pos            (6U)
10493  #define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
10494  #define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk
10495  #define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)
10496  #define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
10497  #define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk
10498  /********************  Bit definition for RCC_AHB3RSTR register  **************/
10499  #define RCC_AHB3RSTR_FMCRST_Pos            (0U)
10500  #define RCC_AHB3RSTR_FMCRST_Msk            (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */
10501  #define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk
10502  
10503  
10504  /********************  Bit definition for RCC_APB1RSTR register  **************/
10505  #define RCC_APB1RSTR_TIM2RST_Pos           (0U)
10506  #define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
10507  #define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk
10508  #define RCC_APB1RSTR_TIM3RST_Pos           (1U)
10509  #define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
10510  #define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk
10511  #define RCC_APB1RSTR_TIM4RST_Pos           (2U)
10512  #define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
10513  #define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk
10514  #define RCC_APB1RSTR_TIM5RST_Pos           (3U)
10515  #define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
10516  #define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk
10517  #define RCC_APB1RSTR_TIM6RST_Pos           (4U)
10518  #define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
10519  #define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk
10520  #define RCC_APB1RSTR_TIM7RST_Pos           (5U)
10521  #define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
10522  #define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk
10523  #define RCC_APB1RSTR_TIM12RST_Pos          (6U)
10524  #define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
10525  #define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk
10526  #define RCC_APB1RSTR_TIM13RST_Pos          (7U)
10527  #define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
10528  #define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk
10529  #define RCC_APB1RSTR_TIM14RST_Pos          (8U)
10530  #define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
10531  #define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk
10532  #define RCC_APB1RSTR_WWDGRST_Pos           (11U)
10533  #define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
10534  #define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk
10535  #define RCC_APB1RSTR_SPI2RST_Pos           (14U)
10536  #define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
10537  #define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk
10538  #define RCC_APB1RSTR_SPI3RST_Pos           (15U)
10539  #define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
10540  #define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk
10541  #define RCC_APB1RSTR_USART2RST_Pos         (17U)
10542  #define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
10543  #define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk
10544  #define RCC_APB1RSTR_USART3RST_Pos         (18U)
10545  #define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
10546  #define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk
10547  #define RCC_APB1RSTR_UART4RST_Pos          (19U)
10548  #define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
10549  #define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk
10550  #define RCC_APB1RSTR_UART5RST_Pos          (20U)
10551  #define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
10552  #define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk
10553  #define RCC_APB1RSTR_I2C1RST_Pos           (21U)
10554  #define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
10555  #define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk
10556  #define RCC_APB1RSTR_I2C2RST_Pos           (22U)
10557  #define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
10558  #define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk
10559  #define RCC_APB1RSTR_I2C3RST_Pos           (23U)
10560  #define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
10561  #define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk
10562  #define RCC_APB1RSTR_CAN1RST_Pos           (25U)
10563  #define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
10564  #define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk
10565  #define RCC_APB1RSTR_CAN2RST_Pos           (26U)
10566  #define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
10567  #define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk
10568  #define RCC_APB1RSTR_PWRRST_Pos            (28U)
10569  #define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
10570  #define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk
10571  #define RCC_APB1RSTR_DACRST_Pos            (29U)
10572  #define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
10573  #define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk
10574  #define RCC_APB1RSTR_UART7RST_Pos          (30U)
10575  #define RCC_APB1RSTR_UART7RST_Msk          (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
10576  #define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk
10577  #define RCC_APB1RSTR_UART8RST_Pos          (31U)
10578  #define RCC_APB1RSTR_UART8RST_Msk          (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
10579  #define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk
10580  
10581  /********************  Bit definition for RCC_APB2RSTR register  **************/
10582  #define RCC_APB2RSTR_TIM1RST_Pos           (0U)
10583  #define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
10584  #define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk
10585  #define RCC_APB2RSTR_TIM8RST_Pos           (1U)
10586  #define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
10587  #define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk
10588  #define RCC_APB2RSTR_USART1RST_Pos         (4U)
10589  #define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
10590  #define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk
10591  #define RCC_APB2RSTR_USART6RST_Pos         (5U)
10592  #define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
10593  #define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk
10594  #define RCC_APB2RSTR_ADCRST_Pos            (8U)
10595  #define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
10596  #define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk
10597  #define RCC_APB2RSTR_SDIORST_Pos           (11U)
10598  #define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
10599  #define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk
10600  #define RCC_APB2RSTR_SPI1RST_Pos           (12U)
10601  #define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
10602  #define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk
10603  #define RCC_APB2RSTR_SPI4RST_Pos           (13U)
10604  #define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */
10605  #define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk
10606  #define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)
10607  #define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
10608  #define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk
10609  #define RCC_APB2RSTR_TIM9RST_Pos           (16U)
10610  #define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
10611  #define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk
10612  #define RCC_APB2RSTR_TIM10RST_Pos          (17U)
10613  #define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
10614  #define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk
10615  #define RCC_APB2RSTR_TIM11RST_Pos          (18U)
10616  #define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
10617  #define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk
10618  #define RCC_APB2RSTR_SPI5RST_Pos           (20U)
10619  #define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */
10620  #define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk
10621  #define RCC_APB2RSTR_SPI6RST_Pos           (21U)
10622  #define RCC_APB2RSTR_SPI6RST_Msk           (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */
10623  #define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk
10624  #define RCC_APB2RSTR_SAI1RST_Pos           (22U)
10625  #define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */
10626  #define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk
10627  
10628  /* Old SPI1RST bit definition, maintained for legacy purpose */
10629  #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
10630  
10631  /********************  Bit definition for RCC_AHB1ENR register  ***************/
10632  #define RCC_AHB1ENR_GPIOAEN_Pos            (0U)
10633  #define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
10634  #define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk
10635  #define RCC_AHB1ENR_GPIOBEN_Pos            (1U)
10636  #define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
10637  #define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk
10638  #define RCC_AHB1ENR_GPIOCEN_Pos            (2U)
10639  #define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
10640  #define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk
10641  #define RCC_AHB1ENR_GPIODEN_Pos            (3U)
10642  #define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
10643  #define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk
10644  #define RCC_AHB1ENR_GPIOEEN_Pos            (4U)
10645  #define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
10646  #define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk
10647  #define RCC_AHB1ENR_GPIOFEN_Pos            (5U)
10648  #define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
10649  #define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk
10650  #define RCC_AHB1ENR_GPIOGEN_Pos            (6U)
10651  #define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
10652  #define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk
10653  #define RCC_AHB1ENR_GPIOHEN_Pos            (7U)
10654  #define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
10655  #define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk
10656  #define RCC_AHB1ENR_GPIOIEN_Pos            (8U)
10657  #define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
10658  #define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk
10659  #define RCC_AHB1ENR_GPIOJEN_Pos            (9U)
10660  #define RCC_AHB1ENR_GPIOJEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */
10661  #define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk
10662  #define RCC_AHB1ENR_GPIOKEN_Pos            (10U)
10663  #define RCC_AHB1ENR_GPIOKEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */
10664  #define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk
10665  #define RCC_AHB1ENR_CRCEN_Pos              (12U)
10666  #define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
10667  #define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk
10668  #define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)
10669  #define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
10670  #define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk
10671  #define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)
10672  #define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
10673  #define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk
10674  #define RCC_AHB1ENR_DMA1EN_Pos             (21U)
10675  #define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
10676  #define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk
10677  #define RCC_AHB1ENR_DMA2EN_Pos             (22U)
10678  #define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
10679  #define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk
10680  #define RCC_AHB1ENR_DMA2DEN_Pos            (23U)
10681  #define RCC_AHB1ENR_DMA2DEN_Msk            (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */
10682  #define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk
10683  #define RCC_AHB1ENR_ETHMACEN_Pos           (25U)
10684  #define RCC_AHB1ENR_ETHMACEN_Msk           (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
10685  #define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk
10686  #define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)
10687  #define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
10688  #define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk
10689  #define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)
10690  #define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
10691  #define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk
10692  #define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)
10693  #define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
10694  #define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk
10695  #define RCC_AHB1ENR_OTGHSEN_Pos            (29U)
10696  #define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
10697  #define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk
10698  #define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)
10699  #define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
10700  #define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk
10701  /********************  Bit definition for RCC_AHB2ENR register  ***************/
10702  /*
10703   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10704   */
10705  #define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */
10706  
10707  #define RCC_AHB2ENR_DCMIEN_Pos             (0U)
10708  #define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
10709  #define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk
10710  #define RCC_AHB2ENR_RNGEN_Pos              (6U)
10711  #define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
10712  #define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk
10713  #define RCC_AHB2ENR_OTGFSEN_Pos            (7U)
10714  #define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
10715  #define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk
10716  
10717  /********************  Bit definition for RCC_AHB3ENR register  ***************/
10718  /*
10719   * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10720   */
10721  #define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */
10722  
10723  #define RCC_AHB3ENR_FMCEN_Pos              (0U)
10724  #define RCC_AHB3ENR_FMCEN_Msk              (0x1UL << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */
10725  #define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk
10726  
10727  /********************  Bit definition for RCC_APB1ENR register  ***************/
10728  #define RCC_APB1ENR_TIM2EN_Pos             (0U)
10729  #define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
10730  #define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk
10731  #define RCC_APB1ENR_TIM3EN_Pos             (1U)
10732  #define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
10733  #define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk
10734  #define RCC_APB1ENR_TIM4EN_Pos             (2U)
10735  #define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
10736  #define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk
10737  #define RCC_APB1ENR_TIM5EN_Pos             (3U)
10738  #define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
10739  #define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk
10740  #define RCC_APB1ENR_TIM6EN_Pos             (4U)
10741  #define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
10742  #define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk
10743  #define RCC_APB1ENR_TIM7EN_Pos             (5U)
10744  #define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
10745  #define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk
10746  #define RCC_APB1ENR_TIM12EN_Pos            (6U)
10747  #define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
10748  #define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk
10749  #define RCC_APB1ENR_TIM13EN_Pos            (7U)
10750  #define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
10751  #define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk
10752  #define RCC_APB1ENR_TIM14EN_Pos            (8U)
10753  #define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
10754  #define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk
10755  #define RCC_APB1ENR_WWDGEN_Pos             (11U)
10756  #define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
10757  #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk
10758  #define RCC_APB1ENR_SPI2EN_Pos             (14U)
10759  #define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
10760  #define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk
10761  #define RCC_APB1ENR_SPI3EN_Pos             (15U)
10762  #define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
10763  #define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk
10764  #define RCC_APB1ENR_USART2EN_Pos           (17U)
10765  #define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
10766  #define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk
10767  #define RCC_APB1ENR_USART3EN_Pos           (18U)
10768  #define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
10769  #define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk
10770  #define RCC_APB1ENR_UART4EN_Pos            (19U)
10771  #define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
10772  #define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk
10773  #define RCC_APB1ENR_UART5EN_Pos            (20U)
10774  #define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
10775  #define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk
10776  #define RCC_APB1ENR_I2C1EN_Pos             (21U)
10777  #define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
10778  #define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk
10779  #define RCC_APB1ENR_I2C2EN_Pos             (22U)
10780  #define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
10781  #define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk
10782  #define RCC_APB1ENR_I2C3EN_Pos             (23U)
10783  #define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
10784  #define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk
10785  #define RCC_APB1ENR_CAN1EN_Pos             (25U)
10786  #define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
10787  #define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk
10788  #define RCC_APB1ENR_CAN2EN_Pos             (26U)
10789  #define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
10790  #define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk
10791  #define RCC_APB1ENR_PWREN_Pos              (28U)
10792  #define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
10793  #define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk
10794  #define RCC_APB1ENR_DACEN_Pos              (29U)
10795  #define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
10796  #define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk
10797  #define RCC_APB1ENR_UART7EN_Pos            (30U)
10798  #define RCC_APB1ENR_UART7EN_Msk            (0x1UL << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */
10799  #define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk
10800  #define RCC_APB1ENR_UART8EN_Pos            (31U)
10801  #define RCC_APB1ENR_UART8EN_Msk            (0x1UL << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */
10802  #define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk
10803  
10804  /********************  Bit definition for RCC_APB2ENR register  ***************/
10805  #define RCC_APB2ENR_TIM1EN_Pos             (0U)
10806  #define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
10807  #define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk
10808  #define RCC_APB2ENR_TIM8EN_Pos             (1U)
10809  #define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
10810  #define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk
10811  #define RCC_APB2ENR_USART1EN_Pos           (4U)
10812  #define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
10813  #define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk
10814  #define RCC_APB2ENR_USART6EN_Pos           (5U)
10815  #define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
10816  #define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk
10817  #define RCC_APB2ENR_ADC1EN_Pos             (8U)
10818  #define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
10819  #define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk
10820  #define RCC_APB2ENR_ADC2EN_Pos             (9U)
10821  #define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
10822  #define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk
10823  #define RCC_APB2ENR_ADC3EN_Pos             (10U)
10824  #define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
10825  #define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk
10826  #define RCC_APB2ENR_SDIOEN_Pos             (11U)
10827  #define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
10828  #define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk
10829  #define RCC_APB2ENR_SPI1EN_Pos             (12U)
10830  #define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
10831  #define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk
10832  #define RCC_APB2ENR_SPI4EN_Pos             (13U)
10833  #define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */
10834  #define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk
10835  #define RCC_APB2ENR_SYSCFGEN_Pos           (14U)
10836  #define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
10837  #define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk
10838  #define RCC_APB2ENR_TIM9EN_Pos             (16U)
10839  #define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
10840  #define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk
10841  #define RCC_APB2ENR_TIM10EN_Pos            (17U)
10842  #define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
10843  #define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk
10844  #define RCC_APB2ENR_TIM11EN_Pos            (18U)
10845  #define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
10846  #define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk
10847  #define RCC_APB2ENR_SPI5EN_Pos             (20U)
10848  #define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */
10849  #define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk
10850  #define RCC_APB2ENR_SPI6EN_Pos             (21U)
10851  #define RCC_APB2ENR_SPI6EN_Msk             (0x1UL << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */
10852  #define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk
10853  #define RCC_APB2ENR_SAI1EN_Pos             (22U)
10854  #define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */
10855  #define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk
10856  
10857  /********************  Bit definition for RCC_AHB1LPENR register  *************/
10858  #define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)
10859  #define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
10860  #define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk
10861  #define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)
10862  #define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
10863  #define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk
10864  #define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)
10865  #define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
10866  #define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk
10867  #define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)
10868  #define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
10869  #define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk
10870  #define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)
10871  #define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
10872  #define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk
10873  #define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)
10874  #define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
10875  #define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk
10876  #define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)
10877  #define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
10878  #define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk
10879  #define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)
10880  #define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
10881  #define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk
10882  #define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)
10883  #define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
10884  #define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk
10885  #define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)
10886  #define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
10887  #define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk
10888  #define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)
10889  #define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
10890  #define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk
10891  #define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)
10892  #define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
10893  #define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk
10894  #define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)
10895  #define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
10896  #define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk
10897  #define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)
10898  #define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
10899  #define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk
10900  #define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)
10901  #define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
10902  #define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk
10903  #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)
10904  #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
10905  #define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10906  #define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)
10907  #define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
10908  #define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk
10909  #define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)
10910  #define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
10911  #define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk
10912  #define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)
10913  #define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
10914  #define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk
10915  
10916  #define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)
10917  #define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
10918  #define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk
10919  #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)
10920  #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
10921  #define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk
10922  #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)
10923  #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
10924  #define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk
10925  #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)
10926  #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
10927  #define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
10928  #define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)
10929  #define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
10930  #define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk
10931  #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)
10932  #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
10933  #define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10934  
10935  /********************  Bit definition for RCC_AHB2LPENR register  *************/
10936  #define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)
10937  #define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
10938  #define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk
10939  #define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)
10940  #define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
10941  #define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk
10942  #define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)
10943  #define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
10944  #define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk
10945  
10946  /********************  Bit definition for RCC_AHB3LPENR register  *************/
10947  #define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)
10948  #define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
10949  #define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk
10950  
10951  /********************  Bit definition for RCC_APB1LPENR register  *************/
10952  #define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)
10953  #define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
10954  #define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk
10955  #define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)
10956  #define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
10957  #define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk
10958  #define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)
10959  #define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
10960  #define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk
10961  #define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)
10962  #define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
10963  #define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk
10964  #define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)
10965  #define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
10966  #define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk
10967  #define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)
10968  #define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
10969  #define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk
10970  #define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)
10971  #define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
10972  #define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk
10973  #define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)
10974  #define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
10975  #define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk
10976  #define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)
10977  #define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
10978  #define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk
10979  #define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)
10980  #define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
10981  #define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk
10982  #define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)
10983  #define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
10984  #define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk
10985  #define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)
10986  #define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
10987  #define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk
10988  #define RCC_APB1LPENR_USART2LPEN_Pos       (17U)
10989  #define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
10990  #define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk
10991  #define RCC_APB1LPENR_USART3LPEN_Pos       (18U)
10992  #define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
10993  #define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk
10994  #define RCC_APB1LPENR_UART4LPEN_Pos        (19U)
10995  #define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
10996  #define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk
10997  #define RCC_APB1LPENR_UART5LPEN_Pos        (20U)
10998  #define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
10999  #define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk
11000  #define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)
11001  #define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
11002  #define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk
11003  #define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)
11004  #define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
11005  #define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk
11006  #define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)
11007  #define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
11008  #define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk
11009  #define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)
11010  #define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
11011  #define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk
11012  #define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)
11013  #define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
11014  #define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk
11015  #define RCC_APB1LPENR_PWRLPEN_Pos          (28U)
11016  #define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
11017  #define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk
11018  #define RCC_APB1LPENR_DACLPEN_Pos          (29U)
11019  #define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
11020  #define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk
11021  #define RCC_APB1LPENR_UART7LPEN_Pos        (30U)
11022  #define RCC_APB1LPENR_UART7LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
11023  #define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk
11024  #define RCC_APB1LPENR_UART8LPEN_Pos        (31U)
11025  #define RCC_APB1LPENR_UART8LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
11026  #define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk
11027  
11028  /********************  Bit definition for RCC_APB2LPENR register  *************/
11029  #define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)
11030  #define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
11031  #define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk
11032  #define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)
11033  #define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
11034  #define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk
11035  #define RCC_APB2LPENR_USART1LPEN_Pos       (4U)
11036  #define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
11037  #define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk
11038  #define RCC_APB2LPENR_USART6LPEN_Pos       (5U)
11039  #define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
11040  #define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk
11041  #define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)
11042  #define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
11043  #define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk
11044  #define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)
11045  #define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
11046  #define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk
11047  #define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)
11048  #define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
11049  #define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk
11050  #define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)
11051  #define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
11052  #define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk
11053  #define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)
11054  #define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
11055  #define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk
11056  #define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)
11057  #define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
11058  #define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk
11059  #define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)
11060  #define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
11061  #define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk
11062  #define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)
11063  #define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
11064  #define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk
11065  #define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)
11066  #define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
11067  #define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk
11068  #define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)
11069  #define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
11070  #define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk
11071  #define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)
11072  #define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
11073  #define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk
11074  #define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)
11075  #define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
11076  #define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk
11077  #define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)
11078  #define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
11079  #define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk
11080  
11081  /********************  Bit definition for RCC_BDCR register  ******************/
11082  #define RCC_BDCR_LSEON_Pos                 (0U)
11083  #define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
11084  #define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk
11085  #define RCC_BDCR_LSERDY_Pos                (1U)
11086  #define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
11087  #define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk
11088  #define RCC_BDCR_LSEBYP_Pos                (2U)
11089  #define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
11090  #define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk
11091  
11092  #define RCC_BDCR_RTCSEL_Pos                (8U)
11093  #define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
11094  #define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk
11095  #define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
11096  #define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
11097  
11098  #define RCC_BDCR_RTCEN_Pos                 (15U)
11099  #define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
11100  #define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk
11101  #define RCC_BDCR_BDRST_Pos                 (16U)
11102  #define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
11103  #define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk
11104  
11105  /********************  Bit definition for RCC_CSR register  *******************/
11106  #define RCC_CSR_LSION_Pos                  (0U)
11107  #define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
11108  #define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
11109  #define RCC_CSR_LSIRDY_Pos                 (1U)
11110  #define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
11111  #define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
11112  #define RCC_CSR_RMVF_Pos                   (24U)
11113  #define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
11114  #define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk
11115  #define RCC_CSR_BORRSTF_Pos                (25U)
11116  #define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
11117  #define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk
11118  #define RCC_CSR_PINRSTF_Pos                (26U)
11119  #define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
11120  #define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
11121  #define RCC_CSR_PORRSTF_Pos                (27U)
11122  #define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
11123  #define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk
11124  #define RCC_CSR_SFTRSTF_Pos                (28U)
11125  #define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
11126  #define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk
11127  #define RCC_CSR_IWDGRSTF_Pos               (29U)
11128  #define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
11129  #define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
11130  #define RCC_CSR_WWDGRSTF_Pos               (30U)
11131  #define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
11132  #define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk
11133  #define RCC_CSR_LPWRRSTF_Pos               (31U)
11134  #define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
11135  #define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
11136  /* Legacy defines */
11137  #define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
11138  #define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
11139  
11140  /********************  Bit definition for RCC_SSCGR register  *****************/
11141  #define RCC_SSCGR_MODPER_Pos               (0U)
11142  #define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
11143  #define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk
11144  #define RCC_SSCGR_INCSTEP_Pos              (13U)
11145  #define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
11146  #define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk
11147  #define RCC_SSCGR_SPREADSEL_Pos            (30U)
11148  #define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
11149  #define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk
11150  #define RCC_SSCGR_SSCGEN_Pos               (31U)
11151  #define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
11152  #define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk
11153  
11154  /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
11155  #define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)
11156  #define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
11157  #define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk
11158  #define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
11159  #define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
11160  #define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
11161  #define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
11162  #define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
11163  #define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
11164  #define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
11165  #define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
11166  #define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
11167  
11168  #define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)
11169  #define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
11170  #define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk
11171  #define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
11172  #define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
11173  #define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
11174  #define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
11175  #define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)
11176  #define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
11177  #define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk
11178  #define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
11179  #define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
11180  #define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
11181  
11182  /********************  Bit definition for RCC_PLLSAICFGR register  ************/
11183  #define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)
11184  #define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
11185  #define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk
11186  #define RCC_PLLSAICFGR_PLLSAIN_0           (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
11187  #define RCC_PLLSAICFGR_PLLSAIN_1           (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
11188  #define RCC_PLLSAICFGR_PLLSAIN_2           (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
11189  #define RCC_PLLSAICFGR_PLLSAIN_3           (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
11190  #define RCC_PLLSAICFGR_PLLSAIN_4           (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
11191  #define RCC_PLLSAICFGR_PLLSAIN_5           (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
11192  #define RCC_PLLSAICFGR_PLLSAIN_6           (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
11193  #define RCC_PLLSAICFGR_PLLSAIN_7           (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
11194  #define RCC_PLLSAICFGR_PLLSAIN_8           (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
11195  
11196  
11197  #define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)
11198  #define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
11199  #define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk
11200  #define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
11201  #define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
11202  #define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
11203  #define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
11204  
11205  #define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)
11206  #define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
11207  #define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk
11208  #define RCC_PLLSAICFGR_PLLSAIR_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
11209  #define RCC_PLLSAICFGR_PLLSAIR_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
11210  #define RCC_PLLSAICFGR_PLLSAIR_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
11211  
11212  /********************  Bit definition for RCC_DCKCFGR register  ***************/
11213  #define RCC_DCKCFGR_PLLI2SDIVQ_Pos        (0U)
11214  #define RCC_DCKCFGR_PLLI2SDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
11215  #define RCC_DCKCFGR_PLLI2SDIVQ            RCC_DCKCFGR_PLLI2SDIVQ_Msk
11216  #define RCC_DCKCFGR_PLLI2SDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
11217  #define RCC_DCKCFGR_PLLI2SDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
11218  #define RCC_DCKCFGR_PLLI2SDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
11219  #define RCC_DCKCFGR_PLLI2SDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
11220  #define RCC_DCKCFGR_PLLI2SDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
11221  
11222  #define RCC_DCKCFGR_PLLSAIDIVQ_Pos        (8U)
11223  #define RCC_DCKCFGR_PLLSAIDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
11224  #define RCC_DCKCFGR_PLLSAIDIVQ            RCC_DCKCFGR_PLLSAIDIVQ_Msk
11225  #define RCC_DCKCFGR_PLLSAIDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
11226  #define RCC_DCKCFGR_PLLSAIDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
11227  #define RCC_DCKCFGR_PLLSAIDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
11228  #define RCC_DCKCFGR_PLLSAIDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
11229  #define RCC_DCKCFGR_PLLSAIDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
11230  #define RCC_DCKCFGR_PLLSAIDIVR_Pos        (16U)
11231  #define RCC_DCKCFGR_PLLSAIDIVR_Msk        (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11232  #define RCC_DCKCFGR_PLLSAIDIVR            RCC_DCKCFGR_PLLSAIDIVR_Msk
11233  #define RCC_DCKCFGR_PLLSAIDIVR_0          (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11234  #define RCC_DCKCFGR_PLLSAIDIVR_1          (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
11235  
11236  #define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)
11237  #define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */
11238  #define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk
11239  #define RCC_DCKCFGR_SAI1ASRC_0             (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */
11240  #define RCC_DCKCFGR_SAI1ASRC_1             (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */
11241  #define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)
11242  #define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */
11243  #define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk
11244  #define RCC_DCKCFGR_SAI1BSRC_0             (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */
11245  #define RCC_DCKCFGR_SAI1BSRC_1             (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */
11246  #define RCC_DCKCFGR_TIMPRE_Pos             (24U)
11247  #define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */
11248  #define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk
11249  
11250  
11251  /******************************************************************************/
11252  /*                                                                            */
11253  /*                                    RNG                                     */
11254  /*                                                                            */
11255  /******************************************************************************/
11256  /********************  Bits definition for RNG_CR register  *******************/
11257  #define RNG_CR_RNGEN_Pos    (2U)
11258  #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
11259  #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
11260  #define RNG_CR_IE_Pos       (3U)
11261  #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
11262  #define RNG_CR_IE           RNG_CR_IE_Msk
11263  
11264  /********************  Bits definition for RNG_SR register  *******************/
11265  #define RNG_SR_DRDY_Pos     (0U)
11266  #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
11267  #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
11268  #define RNG_SR_CECS_Pos     (1U)
11269  #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
11270  #define RNG_SR_CECS         RNG_SR_CECS_Msk
11271  #define RNG_SR_SECS_Pos     (2U)
11272  #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
11273  #define RNG_SR_SECS         RNG_SR_SECS_Msk
11274  #define RNG_SR_CEIS_Pos     (5U)
11275  #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
11276  #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
11277  #define RNG_SR_SEIS_Pos     (6U)
11278  #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
11279  #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
11280  
11281  /******************************************************************************/
11282  /*                                                                            */
11283  /*                           Real-Time Clock (RTC)                            */
11284  /*                                                                            */
11285  /******************************************************************************/
11286  /*
11287   * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)
11288   */
11289  #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
11290  #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
11291  /********************  Bits definition for RTC_TR register  *******************/
11292  #define RTC_TR_PM_Pos                 (22U)
11293  #define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
11294  #define RTC_TR_PM                     RTC_TR_PM_Msk
11295  #define RTC_TR_HT_Pos                 (20U)
11296  #define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
11297  #define RTC_TR_HT                     RTC_TR_HT_Msk
11298  #define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
11299  #define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
11300  #define RTC_TR_HU_Pos                 (16U)
11301  #define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
11302  #define RTC_TR_HU                     RTC_TR_HU_Msk
11303  #define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
11304  #define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
11305  #define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
11306  #define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
11307  #define RTC_TR_MNT_Pos                (12U)
11308  #define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
11309  #define RTC_TR_MNT                    RTC_TR_MNT_Msk
11310  #define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
11311  #define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
11312  #define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
11313  #define RTC_TR_MNU_Pos                (8U)
11314  #define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
11315  #define RTC_TR_MNU                    RTC_TR_MNU_Msk
11316  #define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
11317  #define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
11318  #define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
11319  #define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
11320  #define RTC_TR_ST_Pos                 (4U)
11321  #define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
11322  #define RTC_TR_ST                     RTC_TR_ST_Msk
11323  #define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
11324  #define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
11325  #define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
11326  #define RTC_TR_SU_Pos                 (0U)
11327  #define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
11328  #define RTC_TR_SU                     RTC_TR_SU_Msk
11329  #define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
11330  #define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
11331  #define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
11332  #define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
11333  
11334  /********************  Bits definition for RTC_DR register  *******************/
11335  #define RTC_DR_YT_Pos                 (20U)
11336  #define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
11337  #define RTC_DR_YT                     RTC_DR_YT_Msk
11338  #define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
11339  #define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
11340  #define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
11341  #define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
11342  #define RTC_DR_YU_Pos                 (16U)
11343  #define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
11344  #define RTC_DR_YU                     RTC_DR_YU_Msk
11345  #define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
11346  #define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
11347  #define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
11348  #define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
11349  #define RTC_DR_WDU_Pos                (13U)
11350  #define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
11351  #define RTC_DR_WDU                    RTC_DR_WDU_Msk
11352  #define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
11353  #define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
11354  #define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
11355  #define RTC_DR_MT_Pos                 (12U)
11356  #define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
11357  #define RTC_DR_MT                     RTC_DR_MT_Msk
11358  #define RTC_DR_MU_Pos                 (8U)
11359  #define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
11360  #define RTC_DR_MU                     RTC_DR_MU_Msk
11361  #define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
11362  #define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
11363  #define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
11364  #define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
11365  #define RTC_DR_DT_Pos                 (4U)
11366  #define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
11367  #define RTC_DR_DT                     RTC_DR_DT_Msk
11368  #define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
11369  #define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
11370  #define RTC_DR_DU_Pos                 (0U)
11371  #define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
11372  #define RTC_DR_DU                     RTC_DR_DU_Msk
11373  #define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
11374  #define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
11375  #define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
11376  #define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
11377  
11378  /********************  Bits definition for RTC_CR register  *******************/
11379  #define RTC_CR_COE_Pos                (23U)
11380  #define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
11381  #define RTC_CR_COE                    RTC_CR_COE_Msk
11382  #define RTC_CR_OSEL_Pos               (21U)
11383  #define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
11384  #define RTC_CR_OSEL                   RTC_CR_OSEL_Msk
11385  #define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
11386  #define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
11387  #define RTC_CR_POL_Pos                (20U)
11388  #define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
11389  #define RTC_CR_POL                    RTC_CR_POL_Msk
11390  #define RTC_CR_COSEL_Pos              (19U)
11391  #define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
11392  #define RTC_CR_COSEL                  RTC_CR_COSEL_Msk
11393  #define RTC_CR_BKP_Pos                 (18U)
11394  #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
11395  #define RTC_CR_BKP                     RTC_CR_BKP_Msk
11396  #define RTC_CR_SUB1H_Pos              (17U)
11397  #define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
11398  #define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk
11399  #define RTC_CR_ADD1H_Pos              (16U)
11400  #define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
11401  #define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk
11402  #define RTC_CR_TSIE_Pos               (15U)
11403  #define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
11404  #define RTC_CR_TSIE                   RTC_CR_TSIE_Msk
11405  #define RTC_CR_WUTIE_Pos              (14U)
11406  #define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
11407  #define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk
11408  #define RTC_CR_ALRBIE_Pos             (13U)
11409  #define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
11410  #define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk
11411  #define RTC_CR_ALRAIE_Pos             (12U)
11412  #define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
11413  #define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk
11414  #define RTC_CR_TSE_Pos                (11U)
11415  #define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
11416  #define RTC_CR_TSE                    RTC_CR_TSE_Msk
11417  #define RTC_CR_WUTE_Pos               (10U)
11418  #define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
11419  #define RTC_CR_WUTE                   RTC_CR_WUTE_Msk
11420  #define RTC_CR_ALRBE_Pos              (9U)
11421  #define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
11422  #define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk
11423  #define RTC_CR_ALRAE_Pos              (8U)
11424  #define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
11425  #define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk
11426  #define RTC_CR_DCE_Pos                (7U)
11427  #define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
11428  #define RTC_CR_DCE                    RTC_CR_DCE_Msk
11429  #define RTC_CR_FMT_Pos                (6U)
11430  #define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
11431  #define RTC_CR_FMT                    RTC_CR_FMT_Msk
11432  #define RTC_CR_BYPSHAD_Pos            (5U)
11433  #define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
11434  #define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk
11435  #define RTC_CR_REFCKON_Pos            (4U)
11436  #define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
11437  #define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk
11438  #define RTC_CR_TSEDGE_Pos             (3U)
11439  #define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
11440  #define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk
11441  #define RTC_CR_WUCKSEL_Pos            (0U)
11442  #define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
11443  #define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk
11444  #define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
11445  #define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
11446  #define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
11447  
11448  /* Legacy defines */
11449  #define RTC_CR_BCK                     RTC_CR_BKP
11450  
11451  /********************  Bits definition for RTC_ISR register  ******************/
11452  #define RTC_ISR_RECALPF_Pos           (16U)
11453  #define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
11454  #define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk
11455  #define RTC_ISR_TAMP1F_Pos            (13U)
11456  #define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
11457  #define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk
11458  #define RTC_ISR_TAMP2F_Pos            (14U)
11459  #define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
11460  #define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk
11461  #define RTC_ISR_TSOVF_Pos             (12U)
11462  #define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
11463  #define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk
11464  #define RTC_ISR_TSF_Pos               (11U)
11465  #define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
11466  #define RTC_ISR_TSF                   RTC_ISR_TSF_Msk
11467  #define RTC_ISR_WUTF_Pos              (10U)
11468  #define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
11469  #define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk
11470  #define RTC_ISR_ALRBF_Pos             (9U)
11471  #define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
11472  #define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk
11473  #define RTC_ISR_ALRAF_Pos             (8U)
11474  #define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
11475  #define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk
11476  #define RTC_ISR_INIT_Pos              (7U)
11477  #define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
11478  #define RTC_ISR_INIT                  RTC_ISR_INIT_Msk
11479  #define RTC_ISR_INITF_Pos             (6U)
11480  #define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
11481  #define RTC_ISR_INITF                 RTC_ISR_INITF_Msk
11482  #define RTC_ISR_RSF_Pos               (5U)
11483  #define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
11484  #define RTC_ISR_RSF                   RTC_ISR_RSF_Msk
11485  #define RTC_ISR_INITS_Pos             (4U)
11486  #define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
11487  #define RTC_ISR_INITS                 RTC_ISR_INITS_Msk
11488  #define RTC_ISR_SHPF_Pos              (3U)
11489  #define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
11490  #define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk
11491  #define RTC_ISR_WUTWF_Pos             (2U)
11492  #define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
11493  #define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk
11494  #define RTC_ISR_ALRBWF_Pos            (1U)
11495  #define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
11496  #define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk
11497  #define RTC_ISR_ALRAWF_Pos            (0U)
11498  #define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
11499  #define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk
11500  
11501  /********************  Bits definition for RTC_PRER register  *****************/
11502  #define RTC_PRER_PREDIV_A_Pos         (16U)
11503  #define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
11504  #define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk
11505  #define RTC_PRER_PREDIV_S_Pos         (0U)
11506  #define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
11507  #define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk
11508  
11509  /********************  Bits definition for RTC_WUTR register  *****************/
11510  #define RTC_WUTR_WUT_Pos              (0U)
11511  #define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
11512  #define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk
11513  
11514  /********************  Bits definition for RTC_CALIBR register  ***************/
11515  #define RTC_CALIBR_DCS_Pos            (7U)
11516  #define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
11517  #define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk
11518  #define RTC_CALIBR_DC_Pos             (0U)
11519  #define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
11520  #define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk
11521  
11522  /********************  Bits definition for RTC_ALRMAR register  ***************/
11523  #define RTC_ALRMAR_MSK4_Pos           (31U)
11524  #define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
11525  #define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk
11526  #define RTC_ALRMAR_WDSEL_Pos          (30U)
11527  #define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
11528  #define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk
11529  #define RTC_ALRMAR_DT_Pos             (28U)
11530  #define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
11531  #define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk
11532  #define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
11533  #define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
11534  #define RTC_ALRMAR_DU_Pos             (24U)
11535  #define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
11536  #define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk
11537  #define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
11538  #define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
11539  #define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
11540  #define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
11541  #define RTC_ALRMAR_MSK3_Pos           (23U)
11542  #define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
11543  #define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk
11544  #define RTC_ALRMAR_PM_Pos             (22U)
11545  #define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
11546  #define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk
11547  #define RTC_ALRMAR_HT_Pos             (20U)
11548  #define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
11549  #define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk
11550  #define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
11551  #define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
11552  #define RTC_ALRMAR_HU_Pos             (16U)
11553  #define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
11554  #define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk
11555  #define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
11556  #define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
11557  #define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
11558  #define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
11559  #define RTC_ALRMAR_MSK2_Pos           (15U)
11560  #define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
11561  #define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk
11562  #define RTC_ALRMAR_MNT_Pos            (12U)
11563  #define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
11564  #define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk
11565  #define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
11566  #define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
11567  #define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
11568  #define RTC_ALRMAR_MNU_Pos            (8U)
11569  #define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
11570  #define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk
11571  #define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
11572  #define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
11573  #define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
11574  #define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
11575  #define RTC_ALRMAR_MSK1_Pos           (7U)
11576  #define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
11577  #define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk
11578  #define RTC_ALRMAR_ST_Pos             (4U)
11579  #define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
11580  #define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk
11581  #define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
11582  #define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
11583  #define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
11584  #define RTC_ALRMAR_SU_Pos             (0U)
11585  #define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
11586  #define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk
11587  #define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
11588  #define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
11589  #define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
11590  #define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
11591  
11592  /********************  Bits definition for RTC_ALRMBR register  ***************/
11593  #define RTC_ALRMBR_MSK4_Pos           (31U)
11594  #define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
11595  #define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk
11596  #define RTC_ALRMBR_WDSEL_Pos          (30U)
11597  #define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
11598  #define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk
11599  #define RTC_ALRMBR_DT_Pos             (28U)
11600  #define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
11601  #define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk
11602  #define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
11603  #define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
11604  #define RTC_ALRMBR_DU_Pos             (24U)
11605  #define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
11606  #define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk
11607  #define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
11608  #define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
11609  #define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
11610  #define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
11611  #define RTC_ALRMBR_MSK3_Pos           (23U)
11612  #define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
11613  #define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk
11614  #define RTC_ALRMBR_PM_Pos             (22U)
11615  #define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
11616  #define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk
11617  #define RTC_ALRMBR_HT_Pos             (20U)
11618  #define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
11619  #define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk
11620  #define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
11621  #define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
11622  #define RTC_ALRMBR_HU_Pos             (16U)
11623  #define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
11624  #define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk
11625  #define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
11626  #define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
11627  #define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
11628  #define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
11629  #define RTC_ALRMBR_MSK2_Pos           (15U)
11630  #define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
11631  #define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk
11632  #define RTC_ALRMBR_MNT_Pos            (12U)
11633  #define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
11634  #define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk
11635  #define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
11636  #define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
11637  #define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
11638  #define RTC_ALRMBR_MNU_Pos            (8U)
11639  #define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
11640  #define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk
11641  #define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
11642  #define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
11643  #define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
11644  #define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
11645  #define RTC_ALRMBR_MSK1_Pos           (7U)
11646  #define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
11647  #define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk
11648  #define RTC_ALRMBR_ST_Pos             (4U)
11649  #define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
11650  #define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk
11651  #define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
11652  #define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
11653  #define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
11654  #define RTC_ALRMBR_SU_Pos             (0U)
11655  #define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
11656  #define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk
11657  #define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
11658  #define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
11659  #define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
11660  #define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
11661  
11662  /********************  Bits definition for RTC_WPR register  ******************/
11663  #define RTC_WPR_KEY_Pos               (0U)
11664  #define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
11665  #define RTC_WPR_KEY                   RTC_WPR_KEY_Msk
11666  
11667  /********************  Bits definition for RTC_SSR register  ******************/
11668  #define RTC_SSR_SS_Pos                (0U)
11669  #define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
11670  #define RTC_SSR_SS                    RTC_SSR_SS_Msk
11671  
11672  /********************  Bits definition for RTC_SHIFTR register  ***************/
11673  #define RTC_SHIFTR_SUBFS_Pos          (0U)
11674  #define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
11675  #define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk
11676  #define RTC_SHIFTR_ADD1S_Pos          (31U)
11677  #define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
11678  #define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk
11679  
11680  /********************  Bits definition for RTC_TSTR register  *****************/
11681  #define RTC_TSTR_PM_Pos               (22U)
11682  #define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
11683  #define RTC_TSTR_PM                   RTC_TSTR_PM_Msk
11684  #define RTC_TSTR_HT_Pos               (20U)
11685  #define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
11686  #define RTC_TSTR_HT                   RTC_TSTR_HT_Msk
11687  #define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
11688  #define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
11689  #define RTC_TSTR_HU_Pos               (16U)
11690  #define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
11691  #define RTC_TSTR_HU                   RTC_TSTR_HU_Msk
11692  #define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
11693  #define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
11694  #define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
11695  #define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
11696  #define RTC_TSTR_MNT_Pos              (12U)
11697  #define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
11698  #define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk
11699  #define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
11700  #define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
11701  #define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
11702  #define RTC_TSTR_MNU_Pos              (8U)
11703  #define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
11704  #define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk
11705  #define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
11706  #define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
11707  #define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
11708  #define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
11709  #define RTC_TSTR_ST_Pos               (4U)
11710  #define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
11711  #define RTC_TSTR_ST                   RTC_TSTR_ST_Msk
11712  #define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
11713  #define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
11714  #define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
11715  #define RTC_TSTR_SU_Pos               (0U)
11716  #define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
11717  #define RTC_TSTR_SU                   RTC_TSTR_SU_Msk
11718  #define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
11719  #define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
11720  #define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
11721  #define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
11722  
11723  /********************  Bits definition for RTC_TSDR register  *****************/
11724  #define RTC_TSDR_WDU_Pos              (13U)
11725  #define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
11726  #define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk
11727  #define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
11728  #define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
11729  #define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
11730  #define RTC_TSDR_MT_Pos               (12U)
11731  #define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
11732  #define RTC_TSDR_MT                   RTC_TSDR_MT_Msk
11733  #define RTC_TSDR_MU_Pos               (8U)
11734  #define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
11735  #define RTC_TSDR_MU                   RTC_TSDR_MU_Msk
11736  #define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
11737  #define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
11738  #define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
11739  #define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
11740  #define RTC_TSDR_DT_Pos               (4U)
11741  #define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
11742  #define RTC_TSDR_DT                   RTC_TSDR_DT_Msk
11743  #define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
11744  #define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
11745  #define RTC_TSDR_DU_Pos               (0U)
11746  #define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
11747  #define RTC_TSDR_DU                   RTC_TSDR_DU_Msk
11748  #define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
11749  #define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
11750  #define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
11751  #define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
11752  
11753  /********************  Bits definition for RTC_TSSSR register  ****************/
11754  #define RTC_TSSSR_SS_Pos              (0U)
11755  #define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
11756  #define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk
11757  
11758  /********************  Bits definition for RTC_CAL register  *****************/
11759  #define RTC_CALR_CALP_Pos             (15U)
11760  #define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
11761  #define RTC_CALR_CALP                 RTC_CALR_CALP_Msk
11762  #define RTC_CALR_CALW8_Pos            (14U)
11763  #define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
11764  #define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk
11765  #define RTC_CALR_CALW16_Pos           (13U)
11766  #define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
11767  #define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk
11768  #define RTC_CALR_CALM_Pos             (0U)
11769  #define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
11770  #define RTC_CALR_CALM                 RTC_CALR_CALM_Msk
11771  #define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
11772  #define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
11773  #define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
11774  #define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
11775  #define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
11776  #define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
11777  #define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
11778  #define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
11779  #define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
11780  
11781  /********************  Bits definition for RTC_TAFCR register  ****************/
11782  #define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)
11783  #define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
11784  #define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk
11785  #define RTC_TAFCR_TSINSEL_Pos         (17U)
11786  #define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
11787  #define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk
11788  #define RTC_TAFCR_TAMP1INSEL_Pos      (16U)
11789  #define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
11790  #define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk
11791  #define RTC_TAFCR_TAMPPUDIS_Pos       (15U)
11792  #define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
11793  #define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk
11794  #define RTC_TAFCR_TAMPPRCH_Pos        (13U)
11795  #define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
11796  #define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk
11797  #define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
11798  #define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
11799  #define RTC_TAFCR_TAMPFLT_Pos         (11U)
11800  #define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
11801  #define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk
11802  #define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
11803  #define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
11804  #define RTC_TAFCR_TAMPFREQ_Pos        (8U)
11805  #define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
11806  #define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk
11807  #define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
11808  #define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
11809  #define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
11810  #define RTC_TAFCR_TAMPTS_Pos          (7U)
11811  #define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
11812  #define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk
11813  #define RTC_TAFCR_TAMP2TRG_Pos        (4U)
11814  #define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
11815  #define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk
11816  #define RTC_TAFCR_TAMP2E_Pos          (3U)
11817  #define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
11818  #define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk
11819  #define RTC_TAFCR_TAMPIE_Pos          (2U)
11820  #define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
11821  #define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk
11822  #define RTC_TAFCR_TAMP1TRG_Pos        (1U)
11823  #define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
11824  #define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk
11825  #define RTC_TAFCR_TAMP1E_Pos          (0U)
11826  #define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
11827  #define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk
11828  
11829  /* Legacy defines */
11830  #define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
11831  
11832  /********************  Bits definition for RTC_ALRMASSR register  *************/
11833  #define RTC_ALRMASSR_MASKSS_Pos       (24U)
11834  #define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
11835  #define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk
11836  #define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
11837  #define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
11838  #define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
11839  #define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
11840  #define RTC_ALRMASSR_SS_Pos           (0U)
11841  #define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
11842  #define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk
11843  
11844  /********************  Bits definition for RTC_ALRMBSSR register  *************/
11845  #define RTC_ALRMBSSR_MASKSS_Pos       (24U)
11846  #define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
11847  #define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk
11848  #define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
11849  #define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
11850  #define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
11851  #define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
11852  #define RTC_ALRMBSSR_SS_Pos           (0U)
11853  #define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
11854  #define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk
11855  
11856  /********************  Bits definition for RTC_BKP0R register  ****************/
11857  #define RTC_BKP0R_Pos                 (0U)
11858  #define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
11859  #define RTC_BKP0R                     RTC_BKP0R_Msk
11860  
11861  /********************  Bits definition for RTC_BKP1R register  ****************/
11862  #define RTC_BKP1R_Pos                 (0U)
11863  #define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
11864  #define RTC_BKP1R                     RTC_BKP1R_Msk
11865  
11866  /********************  Bits definition for RTC_BKP2R register  ****************/
11867  #define RTC_BKP2R_Pos                 (0U)
11868  #define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
11869  #define RTC_BKP2R                     RTC_BKP2R_Msk
11870  
11871  /********************  Bits definition for RTC_BKP3R register  ****************/
11872  #define RTC_BKP3R_Pos                 (0U)
11873  #define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
11874  #define RTC_BKP3R                     RTC_BKP3R_Msk
11875  
11876  /********************  Bits definition for RTC_BKP4R register  ****************/
11877  #define RTC_BKP4R_Pos                 (0U)
11878  #define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
11879  #define RTC_BKP4R                     RTC_BKP4R_Msk
11880  
11881  /********************  Bits definition for RTC_BKP5R register  ****************/
11882  #define RTC_BKP5R_Pos                 (0U)
11883  #define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
11884  #define RTC_BKP5R                     RTC_BKP5R_Msk
11885  
11886  /********************  Bits definition for RTC_BKP6R register  ****************/
11887  #define RTC_BKP6R_Pos                 (0U)
11888  #define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
11889  #define RTC_BKP6R                     RTC_BKP6R_Msk
11890  
11891  /********************  Bits definition for RTC_BKP7R register  ****************/
11892  #define RTC_BKP7R_Pos                 (0U)
11893  #define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
11894  #define RTC_BKP7R                     RTC_BKP7R_Msk
11895  
11896  /********************  Bits definition for RTC_BKP8R register  ****************/
11897  #define RTC_BKP8R_Pos                 (0U)
11898  #define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
11899  #define RTC_BKP8R                     RTC_BKP8R_Msk
11900  
11901  /********************  Bits definition for RTC_BKP9R register  ****************/
11902  #define RTC_BKP9R_Pos                 (0U)
11903  #define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
11904  #define RTC_BKP9R                     RTC_BKP9R_Msk
11905  
11906  /********************  Bits definition for RTC_BKP10R register  ***************/
11907  #define RTC_BKP10R_Pos                (0U)
11908  #define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
11909  #define RTC_BKP10R                    RTC_BKP10R_Msk
11910  
11911  /********************  Bits definition for RTC_BKP11R register  ***************/
11912  #define RTC_BKP11R_Pos                (0U)
11913  #define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
11914  #define RTC_BKP11R                    RTC_BKP11R_Msk
11915  
11916  /********************  Bits definition for RTC_BKP12R register  ***************/
11917  #define RTC_BKP12R_Pos                (0U)
11918  #define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
11919  #define RTC_BKP12R                    RTC_BKP12R_Msk
11920  
11921  /********************  Bits definition for RTC_BKP13R register  ***************/
11922  #define RTC_BKP13R_Pos                (0U)
11923  #define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
11924  #define RTC_BKP13R                    RTC_BKP13R_Msk
11925  
11926  /********************  Bits definition for RTC_BKP14R register  ***************/
11927  #define RTC_BKP14R_Pos                (0U)
11928  #define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
11929  #define RTC_BKP14R                    RTC_BKP14R_Msk
11930  
11931  /********************  Bits definition for RTC_BKP15R register  ***************/
11932  #define RTC_BKP15R_Pos                (0U)
11933  #define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
11934  #define RTC_BKP15R                    RTC_BKP15R_Msk
11935  
11936  /********************  Bits definition for RTC_BKP16R register  ***************/
11937  #define RTC_BKP16R_Pos                (0U)
11938  #define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
11939  #define RTC_BKP16R                    RTC_BKP16R_Msk
11940  
11941  /********************  Bits definition for RTC_BKP17R register  ***************/
11942  #define RTC_BKP17R_Pos                (0U)
11943  #define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
11944  #define RTC_BKP17R                    RTC_BKP17R_Msk
11945  
11946  /********************  Bits definition for RTC_BKP18R register  ***************/
11947  #define RTC_BKP18R_Pos                (0U)
11948  #define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
11949  #define RTC_BKP18R                    RTC_BKP18R_Msk
11950  
11951  /********************  Bits definition for RTC_BKP19R register  ***************/
11952  #define RTC_BKP19R_Pos                (0U)
11953  #define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
11954  #define RTC_BKP19R                    RTC_BKP19R_Msk
11955  
11956  /******************** Number of backup registers ******************************/
11957  #define RTC_BKP_NUMBER                       0x000000014U
11958  
11959  /******************************************************************************/
11960  /*                                                                            */
11961  /*                          Serial Audio Interface                            */
11962  /*                                                                            */
11963  /******************************************************************************/
11964  /********************  Bit definition for SAI_GCR register  *******************/
11965  #define SAI_GCR_SYNCIN_Pos         (0U)
11966  #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
11967  #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
11968  #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
11969  #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
11970  
11971  #define SAI_GCR_SYNCOUT_Pos        (4U)
11972  #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
11973  #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
11974  #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
11975  #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
11976  
11977  /*******************  Bit definition for SAI_xCR1 register  *******************/
11978  #define SAI_xCR1_MODE_Pos          (0U)
11979  #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
11980  #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
11981  #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
11982  #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
11983  
11984  #define SAI_xCR1_PRTCFG_Pos        (2U)
11985  #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
11986  #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
11987  #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
11988  #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
11989  
11990  #define SAI_xCR1_DS_Pos            (5U)
11991  #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
11992  #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
11993  #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
11994  #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
11995  #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
11996  
11997  #define SAI_xCR1_LSBFIRST_Pos      (8U)
11998  #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
11999  #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
12000  #define SAI_xCR1_CKSTR_Pos         (9U)
12001  #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
12002  #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
12003  
12004  #define SAI_xCR1_SYNCEN_Pos        (10U)
12005  #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
12006  #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
12007  #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
12008  #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
12009  
12010  #define SAI_xCR1_MONO_Pos          (12U)
12011  #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
12012  #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
12013  #define SAI_xCR1_OUTDRIV_Pos       (13U)
12014  #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
12015  #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
12016  #define SAI_xCR1_SAIEN_Pos         (16U)
12017  #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
12018  #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
12019  #define SAI_xCR1_DMAEN_Pos         (17U)
12020  #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
12021  #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
12022  #define SAI_xCR1_NODIV_Pos         (19U)
12023  #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
12024  #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
12025  
12026  #define SAI_xCR1_MCKDIV_Pos        (20U)
12027  #define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
12028  #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
12029  #define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */
12030  #define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */
12031  #define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */
12032  #define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */
12033  
12034  /*******************  Bit definition for SAI_xCR2 register  *******************/
12035  #define SAI_xCR2_FTH_Pos           (0U)
12036  #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
12037  #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
12038  #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
12039  #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
12040  #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
12041  
12042  #define SAI_xCR2_FFLUSH_Pos        (3U)
12043  #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
12044  #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
12045  #define SAI_xCR2_TRIS_Pos          (4U)
12046  #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
12047  #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
12048  #define SAI_xCR2_MUTE_Pos          (5U)
12049  #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
12050  #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
12051  #define SAI_xCR2_MUTEVAL_Pos       (6U)
12052  #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
12053  #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
12054  
12055  #define SAI_xCR2_MUTECNT_Pos       (7U)
12056  #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
12057  #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
12058  #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
12059  #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
12060  #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
12061  #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
12062  #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
12063  #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
12064  
12065  #define SAI_xCR2_CPL_Pos           (13U)
12066  #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
12067  #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
12068  
12069  #define SAI_xCR2_COMP_Pos          (14U)
12070  #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
12071  #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
12072  #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
12073  #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
12074  
12075  /******************  Bit definition for SAI_xFRCR register  *******************/
12076  #define SAI_xFRCR_FRL_Pos          (0U)
12077  #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
12078  #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
12079  #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
12080  #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
12081  #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
12082  #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
12083  #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
12084  #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
12085  #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
12086  #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
12087  
12088  #define SAI_xFRCR_FSALL_Pos        (8U)
12089  #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
12090  #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
12091  #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
12092  #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
12093  #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
12094  #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
12095  #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
12096  #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
12097  #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
12098  
12099  #define SAI_xFRCR_FSDEF_Pos        (16U)
12100  #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
12101  #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
12102  #define SAI_xFRCR_FSPOL_Pos        (17U)
12103  #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
12104  #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
12105  #define SAI_xFRCR_FSOFF_Pos        (18U)
12106  #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
12107  #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
12108  /* Legacy defines */
12109  #define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
12110  
12111  /******************  Bit definition for SAI_xSLOTR register  *******************/
12112  #define SAI_xSLOTR_FBOFF_Pos       (0U)
12113  #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
12114  #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
12115  #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
12116  #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
12117  #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
12118  #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
12119  #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
12120  
12121  #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
12122  #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
12123  #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
12124  #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
12125  #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
12126  
12127  #define SAI_xSLOTR_NBSLOT_Pos      (8U)
12128  #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
12129  #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
12130  #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
12131  #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
12132  #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
12133  #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
12134  
12135  #define SAI_xSLOTR_SLOTEN_Pos      (16U)
12136  #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
12137  #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
12138  
12139  /*******************  Bit definition for SAI_xIMR register  *******************/
12140  #define SAI_xIMR_OVRUDRIE_Pos      (0U)
12141  #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
12142  #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
12143  #define SAI_xIMR_MUTEDETIE_Pos     (1U)
12144  #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
12145  #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
12146  #define SAI_xIMR_WCKCFGIE_Pos      (2U)
12147  #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
12148  #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
12149  #define SAI_xIMR_FREQIE_Pos        (3U)
12150  #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
12151  #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
12152  #define SAI_xIMR_CNRDYIE_Pos       (4U)
12153  #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
12154  #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
12155  #define SAI_xIMR_AFSDETIE_Pos      (5U)
12156  #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
12157  #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
12158  #define SAI_xIMR_LFSDETIE_Pos      (6U)
12159  #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
12160  #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
12161  
12162  /********************  Bit definition for SAI_xSR register  *******************/
12163  #define SAI_xSR_OVRUDR_Pos         (0U)
12164  #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
12165  #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
12166  #define SAI_xSR_MUTEDET_Pos        (1U)
12167  #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
12168  #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
12169  #define SAI_xSR_WCKCFG_Pos         (2U)
12170  #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
12171  #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
12172  #define SAI_xSR_FREQ_Pos           (3U)
12173  #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
12174  #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
12175  #define SAI_xSR_CNRDY_Pos          (4U)
12176  #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
12177  #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
12178  #define SAI_xSR_AFSDET_Pos         (5U)
12179  #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
12180  #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
12181  #define SAI_xSR_LFSDET_Pos         (6U)
12182  #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
12183  #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
12184  
12185  #define SAI_xSR_FLVL_Pos           (16U)
12186  #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
12187  #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
12188  #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
12189  #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
12190  #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
12191  
12192  /******************  Bit definition for SAI_xCLRFR register  ******************/
12193  #define SAI_xCLRFR_COVRUDR_Pos     (0U)
12194  #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
12195  #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
12196  #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
12197  #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
12198  #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
12199  #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
12200  #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
12201  #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
12202  #define SAI_xCLRFR_CFREQ_Pos       (3U)
12203  #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
12204  #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
12205  #define SAI_xCLRFR_CCNRDY_Pos      (4U)
12206  #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
12207  #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
12208  #define SAI_xCLRFR_CAFSDET_Pos     (5U)
12209  #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
12210  #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
12211  #define SAI_xCLRFR_CLFSDET_Pos     (6U)
12212  #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
12213  #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
12214  
12215  /******************  Bit definition for SAI_xDR register  ******************/
12216  #define SAI_xDR_DATA_Pos           (0U)
12217  #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
12218  #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
12219  
12220  
12221  /******************************************************************************/
12222  /*                                                                            */
12223  /*                          SD host Interface                                 */
12224  /*                                                                            */
12225  /******************************************************************************/
12226  /******************  Bit definition for SDIO_POWER register  ******************/
12227  #define SDIO_POWER_PWRCTRL_Pos         (0U)
12228  #define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
12229  #define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
12230  #define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
12231  #define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
12232  
12233  /******************  Bit definition for SDIO_CLKCR register  ******************/
12234  #define SDIO_CLKCR_CLKDIV_Pos          (0U)
12235  #define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
12236  #define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
12237  #define SDIO_CLKCR_CLKEN_Pos           (8U)
12238  #define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
12239  #define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
12240  #define SDIO_CLKCR_PWRSAV_Pos          (9U)
12241  #define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
12242  #define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
12243  #define SDIO_CLKCR_BYPASS_Pos          (10U)
12244  #define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
12245  #define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
12246  
12247  #define SDIO_CLKCR_WIDBUS_Pos          (11U)
12248  #define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
12249  #define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
12250  #define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
12251  #define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
12252  
12253  #define SDIO_CLKCR_NEGEDGE_Pos         (13U)
12254  #define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
12255  #define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
12256  #define SDIO_CLKCR_HWFC_EN_Pos         (14U)
12257  #define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
12258  #define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
12259  
12260  /*******************  Bit definition for SDIO_ARG register  *******************/
12261  #define SDIO_ARG_CMDARG_Pos            (0U)
12262  #define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
12263  #define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
12264  
12265  /*******************  Bit definition for SDIO_CMD register  *******************/
12266  #define SDIO_CMD_CMDINDEX_Pos          (0U)
12267  #define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
12268  #define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
12269  
12270  #define SDIO_CMD_WAITRESP_Pos          (6U)
12271  #define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
12272  #define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
12273  #define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
12274  #define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
12275  
12276  #define SDIO_CMD_WAITINT_Pos           (8U)
12277  #define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
12278  #define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
12279  #define SDIO_CMD_WAITPEND_Pos          (9U)
12280  #define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
12281  #define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
12282  #define SDIO_CMD_CPSMEN_Pos            (10U)
12283  #define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
12284  #define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
12285  #define SDIO_CMD_SDIOSUSPEND_Pos       (11U)
12286  #define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
12287  #define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
12288  #define SDIO_CMD_ENCMDCOMPL_Pos        (12U)
12289  #define SDIO_CMD_ENCMDCOMPL_Msk        (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */
12290  #define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */
12291  #define SDIO_CMD_NIEN_Pos              (13U)
12292  #define SDIO_CMD_NIEN_Msk              (0x1UL << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */
12293  #define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */
12294  #define SDIO_CMD_CEATACMD_Pos          (14U)
12295  #define SDIO_CMD_CEATACMD_Msk          (0x1UL << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */
12296  #define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */
12297  
12298  /*****************  Bit definition for SDIO_RESPCMD register  *****************/
12299  #define SDIO_RESPCMD_RESPCMD_Pos       (0U)
12300  #define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
12301  #define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
12302  
12303  /******************  Bit definition for SDIO_RESP0 register  ******************/
12304  #define SDIO_RESP0_CARDSTATUS0_Pos     (0U)
12305  #define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
12306  #define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
12307  
12308  /******************  Bit definition for SDIO_RESP1 register  ******************/
12309  #define SDIO_RESP1_CARDSTATUS1_Pos     (0U)
12310  #define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
12311  #define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
12312  
12313  /******************  Bit definition for SDIO_RESP2 register  ******************/
12314  #define SDIO_RESP2_CARDSTATUS2_Pos     (0U)
12315  #define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
12316  #define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
12317  
12318  /******************  Bit definition for SDIO_RESP3 register  ******************/
12319  #define SDIO_RESP3_CARDSTATUS3_Pos     (0U)
12320  #define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
12321  #define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
12322  
12323  /******************  Bit definition for SDIO_RESP4 register  ******************/
12324  #define SDIO_RESP4_CARDSTATUS4_Pos     (0U)
12325  #define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
12326  #define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
12327  
12328  /******************  Bit definition for SDIO_DTIMER register  *****************/
12329  #define SDIO_DTIMER_DATATIME_Pos       (0U)
12330  #define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
12331  #define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
12332  
12333  /******************  Bit definition for SDIO_DLEN register  *******************/
12334  #define SDIO_DLEN_DATALENGTH_Pos       (0U)
12335  #define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
12336  #define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
12337  
12338  /******************  Bit definition for SDIO_DCTRL register  ******************/
12339  #define SDIO_DCTRL_DTEN_Pos            (0U)
12340  #define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
12341  #define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
12342  #define SDIO_DCTRL_DTDIR_Pos           (1U)
12343  #define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
12344  #define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
12345  #define SDIO_DCTRL_DTMODE_Pos          (2U)
12346  #define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
12347  #define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
12348  #define SDIO_DCTRL_DMAEN_Pos           (3U)
12349  #define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
12350  #define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
12351  
12352  #define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)
12353  #define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
12354  #define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
12355  #define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
12356  #define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
12357  #define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
12358  #define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
12359  
12360  #define SDIO_DCTRL_RWSTART_Pos         (8U)
12361  #define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
12362  #define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
12363  #define SDIO_DCTRL_RWSTOP_Pos          (9U)
12364  #define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
12365  #define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
12366  #define SDIO_DCTRL_RWMOD_Pos           (10U)
12367  #define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
12368  #define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
12369  #define SDIO_DCTRL_SDIOEN_Pos          (11U)
12370  #define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
12371  #define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
12372  
12373  /******************  Bit definition for SDIO_DCOUNT register  *****************/
12374  #define SDIO_DCOUNT_DATACOUNT_Pos      (0U)
12375  #define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
12376  #define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
12377  
12378  /******************  Bit definition for SDIO_STA register  ********************/
12379  #define SDIO_STA_CCRCFAIL_Pos          (0U)
12380  #define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
12381  #define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
12382  #define SDIO_STA_DCRCFAIL_Pos          (1U)
12383  #define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
12384  #define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
12385  #define SDIO_STA_CTIMEOUT_Pos          (2U)
12386  #define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
12387  #define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
12388  #define SDIO_STA_DTIMEOUT_Pos          (3U)
12389  #define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
12390  #define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
12391  #define SDIO_STA_TXUNDERR_Pos          (4U)
12392  #define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
12393  #define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
12394  #define SDIO_STA_RXOVERR_Pos           (5U)
12395  #define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
12396  #define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
12397  #define SDIO_STA_CMDREND_Pos           (6U)
12398  #define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
12399  #define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
12400  #define SDIO_STA_CMDSENT_Pos           (7U)
12401  #define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
12402  #define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
12403  #define SDIO_STA_DATAEND_Pos           (8U)
12404  #define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
12405  #define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
12406  #define SDIO_STA_STBITERR_Pos          (9U)
12407  #define SDIO_STA_STBITERR_Msk          (0x1UL << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */
12408  #define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */
12409  #define SDIO_STA_DBCKEND_Pos           (10U)
12410  #define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
12411  #define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
12412  #define SDIO_STA_CMDACT_Pos            (11U)
12413  #define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
12414  #define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
12415  #define SDIO_STA_TXACT_Pos             (12U)
12416  #define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
12417  #define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
12418  #define SDIO_STA_RXACT_Pos             (13U)
12419  #define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
12420  #define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
12421  #define SDIO_STA_TXFIFOHE_Pos          (14U)
12422  #define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
12423  #define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
12424  #define SDIO_STA_RXFIFOHF_Pos          (15U)
12425  #define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
12426  #define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
12427  #define SDIO_STA_TXFIFOF_Pos           (16U)
12428  #define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
12429  #define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
12430  #define SDIO_STA_RXFIFOF_Pos           (17U)
12431  #define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
12432  #define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
12433  #define SDIO_STA_TXFIFOE_Pos           (18U)
12434  #define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
12435  #define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
12436  #define SDIO_STA_RXFIFOE_Pos           (19U)
12437  #define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
12438  #define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
12439  #define SDIO_STA_TXDAVL_Pos            (20U)
12440  #define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
12441  #define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
12442  #define SDIO_STA_RXDAVL_Pos            (21U)
12443  #define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
12444  #define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
12445  #define SDIO_STA_SDIOIT_Pos            (22U)
12446  #define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
12447  #define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
12448  #define SDIO_STA_CEATAEND_Pos          (23U)
12449  #define SDIO_STA_CEATAEND_Msk          (0x1UL << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */
12450  #define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */
12451  
12452  /*******************  Bit definition for SDIO_ICR register  *******************/
12453  #define SDIO_ICR_CCRCFAILC_Pos         (0U)
12454  #define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
12455  #define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
12456  #define SDIO_ICR_DCRCFAILC_Pos         (1U)
12457  #define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
12458  #define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
12459  #define SDIO_ICR_CTIMEOUTC_Pos         (2U)
12460  #define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
12461  #define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
12462  #define SDIO_ICR_DTIMEOUTC_Pos         (3U)
12463  #define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
12464  #define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
12465  #define SDIO_ICR_TXUNDERRC_Pos         (4U)
12466  #define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
12467  #define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
12468  #define SDIO_ICR_RXOVERRC_Pos          (5U)
12469  #define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
12470  #define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
12471  #define SDIO_ICR_CMDRENDC_Pos          (6U)
12472  #define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
12473  #define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
12474  #define SDIO_ICR_CMDSENTC_Pos          (7U)
12475  #define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
12476  #define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
12477  #define SDIO_ICR_DATAENDC_Pos          (8U)
12478  #define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
12479  #define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
12480  #define SDIO_ICR_STBITERRC_Pos         (9U)
12481  #define SDIO_ICR_STBITERRC_Msk         (0x1UL << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */
12482  #define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */
12483  #define SDIO_ICR_DBCKENDC_Pos          (10U)
12484  #define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
12485  #define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
12486  #define SDIO_ICR_SDIOITC_Pos           (22U)
12487  #define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
12488  #define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
12489  #define SDIO_ICR_CEATAENDC_Pos         (23U)
12490  #define SDIO_ICR_CEATAENDC_Msk         (0x1UL << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */
12491  #define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */
12492  
12493  /******************  Bit definition for SDIO_MASK register  *******************/
12494  #define SDIO_MASK_CCRCFAILIE_Pos       (0U)
12495  #define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
12496  #define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
12497  #define SDIO_MASK_DCRCFAILIE_Pos       (1U)
12498  #define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
12499  #define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
12500  #define SDIO_MASK_CTIMEOUTIE_Pos       (2U)
12501  #define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
12502  #define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
12503  #define SDIO_MASK_DTIMEOUTIE_Pos       (3U)
12504  #define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
12505  #define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
12506  #define SDIO_MASK_TXUNDERRIE_Pos       (4U)
12507  #define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
12508  #define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
12509  #define SDIO_MASK_RXOVERRIE_Pos        (5U)
12510  #define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
12511  #define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
12512  #define SDIO_MASK_CMDRENDIE_Pos        (6U)
12513  #define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
12514  #define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
12515  #define SDIO_MASK_CMDSENTIE_Pos        (7U)
12516  #define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
12517  #define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
12518  #define SDIO_MASK_DATAENDIE_Pos        (8U)
12519  #define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
12520  #define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
12521  #define SDIO_MASK_STBITERRIE_Pos       (9U)
12522  #define SDIO_MASK_STBITERRIE_Msk       (0x1UL << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */
12523  #define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */
12524  #define SDIO_MASK_DBCKENDIE_Pos        (10U)
12525  #define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
12526  #define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
12527  #define SDIO_MASK_CMDACTIE_Pos         (11U)
12528  #define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
12529  #define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
12530  #define SDIO_MASK_TXACTIE_Pos          (12U)
12531  #define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
12532  #define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
12533  #define SDIO_MASK_RXACTIE_Pos          (13U)
12534  #define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
12535  #define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
12536  #define SDIO_MASK_TXFIFOHEIE_Pos       (14U)
12537  #define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
12538  #define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
12539  #define SDIO_MASK_RXFIFOHFIE_Pos       (15U)
12540  #define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
12541  #define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
12542  #define SDIO_MASK_TXFIFOFIE_Pos        (16U)
12543  #define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
12544  #define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
12545  #define SDIO_MASK_RXFIFOFIE_Pos        (17U)
12546  #define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
12547  #define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
12548  #define SDIO_MASK_TXFIFOEIE_Pos        (18U)
12549  #define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
12550  #define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
12551  #define SDIO_MASK_RXFIFOEIE_Pos        (19U)
12552  #define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
12553  #define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
12554  #define SDIO_MASK_TXDAVLIE_Pos         (20U)
12555  #define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
12556  #define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
12557  #define SDIO_MASK_RXDAVLIE_Pos         (21U)
12558  #define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
12559  #define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
12560  #define SDIO_MASK_SDIOITIE_Pos         (22U)
12561  #define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
12562  #define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
12563  #define SDIO_MASK_CEATAENDIE_Pos       (23U)
12564  #define SDIO_MASK_CEATAENDIE_Msk       (0x1UL << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */
12565  #define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */
12566  
12567  /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
12568  #define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)
12569  #define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
12570  #define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
12571  
12572  /******************  Bit definition for SDIO_FIFO register  *******************/
12573  #define SDIO_FIFO_FIFODATA_Pos         (0U)
12574  #define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
12575  #define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
12576  
12577  /******************************************************************************/
12578  /*                                                                            */
12579  /*                        Serial Peripheral Interface                         */
12580  /*                                                                            */
12581  /******************************************************************************/
12582  #define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */
12583  
12584  /*******************  Bit definition for SPI_CR1 register  ********************/
12585  #define SPI_CR1_CPHA_Pos            (0U)
12586  #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
12587  #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
12588  #define SPI_CR1_CPOL_Pos            (1U)
12589  #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
12590  #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
12591  #define SPI_CR1_MSTR_Pos            (2U)
12592  #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
12593  #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
12594  
12595  #define SPI_CR1_BR_Pos              (3U)
12596  #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
12597  #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
12598  #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
12599  #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
12600  #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
12601  
12602  #define SPI_CR1_SPE_Pos             (6U)
12603  #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
12604  #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
12605  #define SPI_CR1_LSBFIRST_Pos        (7U)
12606  #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
12607  #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
12608  #define SPI_CR1_SSI_Pos             (8U)
12609  #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
12610  #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
12611  #define SPI_CR1_SSM_Pos             (9U)
12612  #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
12613  #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
12614  #define SPI_CR1_RXONLY_Pos          (10U)
12615  #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
12616  #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
12617  #define SPI_CR1_DFF_Pos             (11U)
12618  #define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
12619  #define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
12620  #define SPI_CR1_CRCNEXT_Pos         (12U)
12621  #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
12622  #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
12623  #define SPI_CR1_CRCEN_Pos           (13U)
12624  #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
12625  #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
12626  #define SPI_CR1_BIDIOE_Pos          (14U)
12627  #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
12628  #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
12629  #define SPI_CR1_BIDIMODE_Pos        (15U)
12630  #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
12631  #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
12632  
12633  /*******************  Bit definition for SPI_CR2 register  ********************/
12634  #define SPI_CR2_RXDMAEN_Pos         (0U)
12635  #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
12636  #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
12637  #define SPI_CR2_TXDMAEN_Pos         (1U)
12638  #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
12639  #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
12640  #define SPI_CR2_SSOE_Pos            (2U)
12641  #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
12642  #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
12643  #define SPI_CR2_FRF_Pos             (4U)
12644  #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
12645  #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
12646  #define SPI_CR2_ERRIE_Pos           (5U)
12647  #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
12648  #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
12649  #define SPI_CR2_RXNEIE_Pos          (6U)
12650  #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
12651  #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
12652  #define SPI_CR2_TXEIE_Pos           (7U)
12653  #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
12654  #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
12655  
12656  /********************  Bit definition for SPI_SR register  ********************/
12657  #define SPI_SR_RXNE_Pos             (0U)
12658  #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
12659  #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
12660  #define SPI_SR_TXE_Pos              (1U)
12661  #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
12662  #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
12663  #define SPI_SR_CHSIDE_Pos           (2U)
12664  #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
12665  #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
12666  #define SPI_SR_UDR_Pos              (3U)
12667  #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
12668  #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
12669  #define SPI_SR_CRCERR_Pos           (4U)
12670  #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
12671  #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
12672  #define SPI_SR_MODF_Pos             (5U)
12673  #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
12674  #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
12675  #define SPI_SR_OVR_Pos              (6U)
12676  #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
12677  #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
12678  #define SPI_SR_BSY_Pos              (7U)
12679  #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
12680  #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
12681  #define SPI_SR_FRE_Pos              (8U)
12682  #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
12683  #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
12684  
12685  /********************  Bit definition for SPI_DR register  ********************/
12686  #define SPI_DR_DR_Pos               (0U)
12687  #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
12688  #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
12689  
12690  /*******************  Bit definition for SPI_CRCPR register  ******************/
12691  #define SPI_CRCPR_CRCPOLY_Pos       (0U)
12692  #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
12693  #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
12694  
12695  /******************  Bit definition for SPI_RXCRCR register  ******************/
12696  #define SPI_RXCRCR_RXCRC_Pos        (0U)
12697  #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
12698  #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
12699  
12700  /******************  Bit definition for SPI_TXCRCR register  ******************/
12701  #define SPI_TXCRCR_TXCRC_Pos        (0U)
12702  #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
12703  #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
12704  
12705  /******************  Bit definition for SPI_I2SCFGR register  *****************/
12706  #define SPI_I2SCFGR_CHLEN_Pos       (0U)
12707  #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
12708  #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
12709  
12710  #define SPI_I2SCFGR_DATLEN_Pos      (1U)
12711  #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
12712  #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
12713  #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
12714  #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
12715  
12716  #define SPI_I2SCFGR_CKPOL_Pos       (3U)
12717  #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
12718  #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
12719  
12720  #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
12721  #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
12722  #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
12723  #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
12724  #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
12725  
12726  #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
12727  #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
12728  #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
12729  
12730  #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
12731  #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
12732  #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
12733  #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
12734  #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
12735  
12736  #define SPI_I2SCFGR_I2SE_Pos        (10U)
12737  #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
12738  #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
12739  #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
12740  #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
12741  #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
12742  
12743  /******************  Bit definition for SPI_I2SPR register  *******************/
12744  #define SPI_I2SPR_I2SDIV_Pos        (0U)
12745  #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
12746  #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
12747  #define SPI_I2SPR_ODD_Pos           (8U)
12748  #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
12749  #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
12750  #define SPI_I2SPR_MCKOE_Pos         (9U)
12751  #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
12752  #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
12753  
12754  /******************************************************************************/
12755  /*                                                                            */
12756  /*                                 SYSCFG                                     */
12757  /*                                                                            */
12758  /******************************************************************************/
12759  /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
12760  #define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)
12761  #define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
12762  #define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
12763  #define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
12764  #define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
12765  #define SYSCFG_MEMRMP_MEM_MODE_2             (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
12766  #define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)
12767  #define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
12768  #define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */
12769  #define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)
12770  #define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
12771  #define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */
12772  #define SYSCFG_MEMRMP_SWP_FMC_0              (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
12773  /* Legacy Defines */
12774  #define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC
12775  /******************  Bit definition for SYSCFG_PMC register  ******************/
12776  #define SYSCFG_PMC_ADCxDC2_Pos               (16U)
12777  #define SYSCFG_PMC_ADCxDC2_Msk               (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */
12778  #define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12779  #define SYSCFG_PMC_ADC1DC2_Pos               (16U)
12780  #define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */
12781  #define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12782  #define SYSCFG_PMC_ADC2DC2_Pos               (17U)
12783  #define SYSCFG_PMC_ADC2DC2_Msk               (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */
12784  #define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12785  #define SYSCFG_PMC_ADC3DC2_Pos               (18U)
12786  #define SYSCFG_PMC_ADC3DC2_Msk               (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */
12787  #define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
12788  #define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)
12789  #define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
12790  #define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */
12791  /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
12792  #define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
12793  
12794  /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
12795  #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)
12796  #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
12797  #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
12798  #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)
12799  #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
12800  #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
12801  #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)
12802  #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
12803  #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
12804  #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)
12805  #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
12806  #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
12807  /**
12808    * @brief   EXTI0 configuration
12809    */
12810  #define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
12811  #define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
12812  #define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
12813  #define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
12814  #define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
12815  #define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
12816  #define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
12817  #define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
12818  #define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */
12819  #define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */
12820  #define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */
12821  
12822  /**
12823    * @brief   EXTI1 configuration
12824    */
12825  #define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
12826  #define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
12827  #define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
12828  #define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
12829  #define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
12830  #define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
12831  #define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
12832  #define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
12833  #define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */
12834  #define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */
12835  #define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */
12836  
12837  /**
12838    * @brief   EXTI2 configuration
12839    */
12840  #define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
12841  #define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
12842  #define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
12843  #define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
12844  #define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
12845  #define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
12846  #define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
12847  #define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
12848  #define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */
12849  #define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */
12850  #define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */
12851  
12852  /**
12853    * @brief   EXTI3 configuration
12854    */
12855  #define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
12856  #define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
12857  #define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
12858  #define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
12859  #define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
12860  #define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
12861  #define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
12862  #define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
12863  #define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */
12864  #define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */
12865  #define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */
12866  
12867  /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
12868  #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)
12869  #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
12870  #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
12871  #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)
12872  #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
12873  #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
12874  #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)
12875  #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
12876  #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
12877  #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)
12878  #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
12879  #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
12880  
12881  /**
12882    * @brief   EXTI4 configuration
12883    */
12884  #define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
12885  #define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
12886  #define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
12887  #define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
12888  #define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
12889  #define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
12890  #define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
12891  #define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
12892  #define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */
12893  #define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */
12894  #define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */
12895  
12896  /**
12897    * @brief   EXTI5 configuration
12898    */
12899  #define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
12900  #define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
12901  #define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
12902  #define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
12903  #define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
12904  #define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
12905  #define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
12906  #define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
12907  #define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */
12908  #define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */
12909  #define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */
12910  
12911  /**
12912    * @brief   EXTI6 configuration
12913    */
12914  #define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
12915  #define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
12916  #define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
12917  #define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
12918  #define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
12919  #define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
12920  #define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
12921  #define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
12922  #define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */
12923  #define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */
12924  #define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */
12925  
12926  /**
12927    * @brief   EXTI7 configuration
12928    */
12929  #define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
12930  #define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
12931  #define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
12932  #define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
12933  #define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
12934  #define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
12935  #define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
12936  #define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
12937  #define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */
12938  #define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */
12939  #define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */
12940  
12941  /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
12942  #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)
12943  #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
12944  #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
12945  #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)
12946  #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
12947  #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
12948  #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)
12949  #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
12950  #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
12951  #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)
12952  #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
12953  #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
12954  
12955  /**
12956    * @brief   EXTI8 configuration
12957    */
12958  #define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
12959  #define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
12960  #define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
12961  #define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
12962  #define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
12963  #define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
12964  #define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
12965  #define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
12966  #define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */
12967  #define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */
12968  
12969  /**
12970    * @brief   EXTI9 configuration
12971    */
12972  #define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
12973  #define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
12974  #define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
12975  #define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
12976  #define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
12977  #define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
12978  #define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
12979  #define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
12980  #define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */
12981  #define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */
12982  
12983  /**
12984    * @brief   EXTI10 configuration
12985    */
12986  #define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
12987  #define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
12988  #define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
12989  #define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
12990  #define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
12991  #define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
12992  #define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
12993  #define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
12994  #define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */
12995  #define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */
12996  
12997  /**
12998    * @brief   EXTI11 configuration
12999    */
13000  #define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
13001  #define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
13002  #define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
13003  #define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
13004  #define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
13005  #define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
13006  #define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
13007  #define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
13008  #define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */
13009  #define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */
13010  
13011  
13012  /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
13013  #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)
13014  #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
13015  #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
13016  #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)
13017  #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
13018  #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
13019  #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)
13020  #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
13021  #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
13022  #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)
13023  #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
13024  #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
13025  
13026  /**
13027    * @brief   EXTI12 configuration
13028    */
13029  #define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
13030  #define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
13031  #define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
13032  #define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
13033  #define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
13034  #define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
13035  #define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
13036  #define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
13037  #define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */
13038  #define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */
13039  
13040  /**
13041    * @brief   EXTI13 configuration
13042    */
13043  #define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
13044  #define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
13045  #define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
13046  #define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
13047  #define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
13048  #define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
13049  #define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
13050  #define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
13051  #define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */
13052  #define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */
13053  
13054  /**
13055    * @brief   EXTI14 configuration
13056    */
13057  #define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
13058  #define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
13059  #define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
13060  #define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
13061  #define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
13062  #define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
13063  #define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
13064  #define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
13065  #define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */
13066  #define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */
13067  
13068  /**
13069    * @brief   EXTI15 configuration
13070    */
13071  #define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
13072  #define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
13073  #define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
13074  #define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
13075  #define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
13076  #define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
13077  #define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
13078  #define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
13079  #define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */
13080  #define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */
13081  
13082  /******************  Bit definition for SYSCFG_CMPCR register  ****************/
13083  #define SYSCFG_CMPCR_CMP_PD_Pos              (0U)
13084  #define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
13085  #define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
13086  #define SYSCFG_CMPCR_READY_Pos               (8U)
13087  #define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
13088  #define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
13089  
13090  /******************************************************************************/
13091  /*                                                                            */
13092  /*                                    TIM                                     */
13093  /*                                                                            */
13094  /******************************************************************************/
13095  /*******************  Bit definition for TIM_CR1 register  ********************/
13096  #define TIM_CR1_CEN_Pos           (0U)
13097  #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
13098  #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
13099  #define TIM_CR1_UDIS_Pos          (1U)
13100  #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
13101  #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
13102  #define TIM_CR1_URS_Pos           (2U)
13103  #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
13104  #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
13105  #define TIM_CR1_OPM_Pos           (3U)
13106  #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
13107  #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
13108  #define TIM_CR1_DIR_Pos           (4U)
13109  #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
13110  #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
13111  
13112  #define TIM_CR1_CMS_Pos           (5U)
13113  #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
13114  #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
13115  #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
13116  #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
13117  
13118  #define TIM_CR1_ARPE_Pos          (7U)
13119  #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
13120  #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
13121  
13122  #define TIM_CR1_CKD_Pos           (8U)
13123  #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
13124  #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
13125  #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
13126  #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
13127  
13128  /*******************  Bit definition for TIM_CR2 register  ********************/
13129  #define TIM_CR2_CCPC_Pos          (0U)
13130  #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
13131  #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
13132  #define TIM_CR2_CCUS_Pos          (2U)
13133  #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
13134  #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
13135  #define TIM_CR2_CCDS_Pos          (3U)
13136  #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
13137  #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
13138  
13139  #define TIM_CR2_MMS_Pos           (4U)
13140  #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
13141  #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
13142  #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
13143  #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
13144  #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
13145  
13146  #define TIM_CR2_TI1S_Pos          (7U)
13147  #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
13148  #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
13149  #define TIM_CR2_OIS1_Pos          (8U)
13150  #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
13151  #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
13152  #define TIM_CR2_OIS1N_Pos         (9U)
13153  #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
13154  #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
13155  #define TIM_CR2_OIS2_Pos          (10U)
13156  #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
13157  #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
13158  #define TIM_CR2_OIS2N_Pos         (11U)
13159  #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
13160  #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
13161  #define TIM_CR2_OIS3_Pos          (12U)
13162  #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
13163  #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
13164  #define TIM_CR2_OIS3N_Pos         (13U)
13165  #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
13166  #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
13167  #define TIM_CR2_OIS4_Pos          (14U)
13168  #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
13169  #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
13170  
13171  /*******************  Bit definition for TIM_SMCR register  *******************/
13172  #define TIM_SMCR_SMS_Pos          (0U)
13173  #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
13174  #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
13175  #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
13176  #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
13177  #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
13178  
13179  #define TIM_SMCR_TS_Pos           (4U)
13180  #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
13181  #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
13182  #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
13183  #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
13184  #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
13185  
13186  #define TIM_SMCR_MSM_Pos          (7U)
13187  #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
13188  #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
13189  
13190  #define TIM_SMCR_ETF_Pos          (8U)
13191  #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
13192  #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
13193  #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
13194  #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
13195  #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
13196  #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
13197  
13198  #define TIM_SMCR_ETPS_Pos         (12U)
13199  #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
13200  #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
13201  #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
13202  #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
13203  
13204  #define TIM_SMCR_ECE_Pos          (14U)
13205  #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
13206  #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
13207  #define TIM_SMCR_ETP_Pos          (15U)
13208  #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
13209  #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
13210  
13211  /*******************  Bit definition for TIM_DIER register  *******************/
13212  #define TIM_DIER_UIE_Pos          (0U)
13213  #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
13214  #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
13215  #define TIM_DIER_CC1IE_Pos        (1U)
13216  #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
13217  #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
13218  #define TIM_DIER_CC2IE_Pos        (2U)
13219  #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
13220  #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
13221  #define TIM_DIER_CC3IE_Pos        (3U)
13222  #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
13223  #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
13224  #define TIM_DIER_CC4IE_Pos        (4U)
13225  #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
13226  #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
13227  #define TIM_DIER_COMIE_Pos        (5U)
13228  #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
13229  #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
13230  #define TIM_DIER_TIE_Pos          (6U)
13231  #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
13232  #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
13233  #define TIM_DIER_BIE_Pos          (7U)
13234  #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
13235  #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
13236  #define TIM_DIER_UDE_Pos          (8U)
13237  #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
13238  #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
13239  #define TIM_DIER_CC1DE_Pos        (9U)
13240  #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
13241  #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
13242  #define TIM_DIER_CC2DE_Pos        (10U)
13243  #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
13244  #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
13245  #define TIM_DIER_CC3DE_Pos        (11U)
13246  #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
13247  #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
13248  #define TIM_DIER_CC4DE_Pos        (12U)
13249  #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
13250  #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
13251  #define TIM_DIER_COMDE_Pos        (13U)
13252  #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
13253  #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
13254  #define TIM_DIER_TDE_Pos          (14U)
13255  #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
13256  #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
13257  
13258  /********************  Bit definition for TIM_SR register  ********************/
13259  #define TIM_SR_UIF_Pos            (0U)
13260  #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
13261  #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
13262  #define TIM_SR_CC1IF_Pos          (1U)
13263  #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
13264  #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
13265  #define TIM_SR_CC2IF_Pos          (2U)
13266  #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
13267  #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
13268  #define TIM_SR_CC3IF_Pos          (3U)
13269  #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
13270  #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
13271  #define TIM_SR_CC4IF_Pos          (4U)
13272  #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
13273  #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
13274  #define TIM_SR_COMIF_Pos          (5U)
13275  #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
13276  #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
13277  #define TIM_SR_TIF_Pos            (6U)
13278  #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
13279  #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
13280  #define TIM_SR_BIF_Pos            (7U)
13281  #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
13282  #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
13283  #define TIM_SR_CC1OF_Pos          (9U)
13284  #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
13285  #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
13286  #define TIM_SR_CC2OF_Pos          (10U)
13287  #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
13288  #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
13289  #define TIM_SR_CC3OF_Pos          (11U)
13290  #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
13291  #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
13292  #define TIM_SR_CC4OF_Pos          (12U)
13293  #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
13294  #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
13295  
13296  /*******************  Bit definition for TIM_EGR register  ********************/
13297  #define TIM_EGR_UG_Pos            (0U)
13298  #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
13299  #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
13300  #define TIM_EGR_CC1G_Pos          (1U)
13301  #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
13302  #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
13303  #define TIM_EGR_CC2G_Pos          (2U)
13304  #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
13305  #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
13306  #define TIM_EGR_CC3G_Pos          (3U)
13307  #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
13308  #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
13309  #define TIM_EGR_CC4G_Pos          (4U)
13310  #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
13311  #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
13312  #define TIM_EGR_COMG_Pos          (5U)
13313  #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
13314  #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
13315  #define TIM_EGR_TG_Pos            (6U)
13316  #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
13317  #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
13318  #define TIM_EGR_BG_Pos            (7U)
13319  #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
13320  #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
13321  
13322  /******************  Bit definition for TIM_CCMR1 register  *******************/
13323  #define TIM_CCMR1_CC1S_Pos        (0U)
13324  #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
13325  #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13326  #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
13327  #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
13328  
13329  #define TIM_CCMR1_OC1FE_Pos       (2U)
13330  #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
13331  #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
13332  #define TIM_CCMR1_OC1PE_Pos       (3U)
13333  #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
13334  #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
13335  
13336  #define TIM_CCMR1_OC1M_Pos        (4U)
13337  #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
13338  #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
13339  #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
13340  #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
13341  #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
13342  
13343  #define TIM_CCMR1_OC1CE_Pos       (7U)
13344  #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
13345  #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
13346  
13347  #define TIM_CCMR1_CC2S_Pos        (8U)
13348  #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
13349  #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13350  #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
13351  #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
13352  
13353  #define TIM_CCMR1_OC2FE_Pos       (10U)
13354  #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
13355  #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
13356  #define TIM_CCMR1_OC2PE_Pos       (11U)
13357  #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
13358  #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
13359  
13360  #define TIM_CCMR1_OC2M_Pos        (12U)
13361  #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
13362  #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
13363  #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
13364  #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
13365  #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
13366  
13367  #define TIM_CCMR1_OC2CE_Pos       (15U)
13368  #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
13369  #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
13370  
13371  /*----------------------------------------------------------------------------*/
13372  
13373  #define TIM_CCMR1_IC1PSC_Pos      (2U)
13374  #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
13375  #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
13376  #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
13377  #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
13378  
13379  #define TIM_CCMR1_IC1F_Pos        (4U)
13380  #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
13381  #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
13382  #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
13383  #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
13384  #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
13385  #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
13386  
13387  #define TIM_CCMR1_IC2PSC_Pos      (10U)
13388  #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
13389  #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
13390  #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
13391  #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
13392  
13393  #define TIM_CCMR1_IC2F_Pos        (12U)
13394  #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
13395  #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
13396  #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
13397  #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
13398  #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
13399  #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
13400  
13401  /******************  Bit definition for TIM_CCMR2 register  *******************/
13402  #define TIM_CCMR2_CC3S_Pos        (0U)
13403  #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
13404  #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
13405  #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
13406  #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
13407  
13408  #define TIM_CCMR2_OC3FE_Pos       (2U)
13409  #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
13410  #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
13411  #define TIM_CCMR2_OC3PE_Pos       (3U)
13412  #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
13413  #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
13414  
13415  #define TIM_CCMR2_OC3M_Pos        (4U)
13416  #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
13417  #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
13418  #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
13419  #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
13420  #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
13421  
13422  #define TIM_CCMR2_OC3CE_Pos       (7U)
13423  #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
13424  #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
13425  
13426  #define TIM_CCMR2_CC4S_Pos        (8U)
13427  #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
13428  #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
13429  #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
13430  #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
13431  
13432  #define TIM_CCMR2_OC4FE_Pos       (10U)
13433  #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
13434  #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
13435  #define TIM_CCMR2_OC4PE_Pos       (11U)
13436  #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
13437  #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
13438  
13439  #define TIM_CCMR2_OC4M_Pos        (12U)
13440  #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
13441  #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
13442  #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
13443  #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
13444  #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
13445  
13446  #define TIM_CCMR2_OC4CE_Pos       (15U)
13447  #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
13448  #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
13449  
13450  /*----------------------------------------------------------------------------*/
13451  
13452  #define TIM_CCMR2_IC3PSC_Pos      (2U)
13453  #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
13454  #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
13455  #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
13456  #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
13457  
13458  #define TIM_CCMR2_IC3F_Pos        (4U)
13459  #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
13460  #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
13461  #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
13462  #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
13463  #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
13464  #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
13465  
13466  #define TIM_CCMR2_IC4PSC_Pos      (10U)
13467  #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
13468  #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
13469  #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
13470  #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
13471  
13472  #define TIM_CCMR2_IC4F_Pos        (12U)
13473  #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
13474  #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
13475  #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
13476  #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
13477  #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
13478  #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
13479  
13480  /*******************  Bit definition for TIM_CCER register  *******************/
13481  #define TIM_CCER_CC1E_Pos         (0U)
13482  #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
13483  #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
13484  #define TIM_CCER_CC1P_Pos         (1U)
13485  #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
13486  #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
13487  #define TIM_CCER_CC1NE_Pos        (2U)
13488  #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
13489  #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
13490  #define TIM_CCER_CC1NP_Pos        (3U)
13491  #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
13492  #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
13493  #define TIM_CCER_CC2E_Pos         (4U)
13494  #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
13495  #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
13496  #define TIM_CCER_CC2P_Pos         (5U)
13497  #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
13498  #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
13499  #define TIM_CCER_CC2NE_Pos        (6U)
13500  #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
13501  #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
13502  #define TIM_CCER_CC2NP_Pos        (7U)
13503  #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
13504  #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
13505  #define TIM_CCER_CC3E_Pos         (8U)
13506  #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
13507  #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
13508  #define TIM_CCER_CC3P_Pos         (9U)
13509  #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
13510  #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
13511  #define TIM_CCER_CC3NE_Pos        (10U)
13512  #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
13513  #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
13514  #define TIM_CCER_CC3NP_Pos        (11U)
13515  #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
13516  #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
13517  #define TIM_CCER_CC4E_Pos         (12U)
13518  #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
13519  #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
13520  #define TIM_CCER_CC4P_Pos         (13U)
13521  #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
13522  #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
13523  #define TIM_CCER_CC4NP_Pos        (15U)
13524  #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
13525  #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
13526  
13527  /*******************  Bit definition for TIM_CNT register  ********************/
13528  #define TIM_CNT_CNT_Pos           (0U)
13529  #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
13530  #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
13531  
13532  /*******************  Bit definition for TIM_PSC register  ********************/
13533  #define TIM_PSC_PSC_Pos           (0U)
13534  #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
13535  #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
13536  
13537  /*******************  Bit definition for TIM_ARR register  ********************/
13538  #define TIM_ARR_ARR_Pos           (0U)
13539  #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
13540  #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
13541  
13542  /*******************  Bit definition for TIM_RCR register  ********************/
13543  #define TIM_RCR_REP_Pos           (0U)
13544  #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
13545  #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
13546  
13547  /*******************  Bit definition for TIM_CCR1 register  *******************/
13548  #define TIM_CCR1_CCR1_Pos         (0U)
13549  #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
13550  #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
13551  
13552  /*******************  Bit definition for TIM_CCR2 register  *******************/
13553  #define TIM_CCR2_CCR2_Pos         (0U)
13554  #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
13555  #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
13556  
13557  /*******************  Bit definition for TIM_CCR3 register  *******************/
13558  #define TIM_CCR3_CCR3_Pos         (0U)
13559  #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
13560  #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
13561  
13562  /*******************  Bit definition for TIM_CCR4 register  *******************/
13563  #define TIM_CCR4_CCR4_Pos         (0U)
13564  #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
13565  #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
13566  
13567  /*******************  Bit definition for TIM_BDTR register  *******************/
13568  #define TIM_BDTR_DTG_Pos          (0U)
13569  #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
13570  #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
13571  #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
13572  #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
13573  #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
13574  #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
13575  #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
13576  #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
13577  #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
13578  #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
13579  
13580  #define TIM_BDTR_LOCK_Pos         (8U)
13581  #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
13582  #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
13583  #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
13584  #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
13585  
13586  #define TIM_BDTR_OSSI_Pos         (10U)
13587  #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
13588  #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
13589  #define TIM_BDTR_OSSR_Pos         (11U)
13590  #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
13591  #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
13592  #define TIM_BDTR_BKE_Pos          (12U)
13593  #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
13594  #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
13595  #define TIM_BDTR_BKP_Pos          (13U)
13596  #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
13597  #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
13598  #define TIM_BDTR_AOE_Pos          (14U)
13599  #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
13600  #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
13601  #define TIM_BDTR_MOE_Pos          (15U)
13602  #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
13603  #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
13604  
13605  /*******************  Bit definition for TIM_DCR register  ********************/
13606  #define TIM_DCR_DBA_Pos           (0U)
13607  #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
13608  #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
13609  #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
13610  #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
13611  #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
13612  #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
13613  #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
13614  
13615  #define TIM_DCR_DBL_Pos           (8U)
13616  #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
13617  #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
13618  #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
13619  #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
13620  #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
13621  #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
13622  #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
13623  
13624  /*******************  Bit definition for TIM_DMAR register  *******************/
13625  #define TIM_DMAR_DMAB_Pos         (0U)
13626  #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
13627  #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
13628  
13629  /*******************  Bit definition for TIM_OR register  *********************/
13630  #define TIM_OR_TI1_RMP_Pos        (0U)
13631  #define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
13632  #define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
13633  #define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
13634  #define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
13635  
13636  #define TIM_OR_TI4_RMP_Pos        (6U)
13637  #define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
13638  #define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
13639  #define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
13640  #define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
13641  #define TIM_OR_ITR1_RMP_Pos       (10U)
13642  #define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
13643  #define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
13644  #define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
13645  #define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
13646  
13647  
13648  /******************************************************************************/
13649  /*                                                                            */
13650  /*         Universal Synchronous Asynchronous Receiver Transmitter            */
13651  /*                                                                            */
13652  /******************************************************************************/
13653  /*******************  Bit definition for USART_SR register  *******************/
13654  #define USART_SR_PE_Pos               (0U)
13655  #define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
13656  #define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
13657  #define USART_SR_FE_Pos               (1U)
13658  #define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
13659  #define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
13660  #define USART_SR_NE_Pos               (2U)
13661  #define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
13662  #define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
13663  #define USART_SR_ORE_Pos              (3U)
13664  #define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
13665  #define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
13666  #define USART_SR_IDLE_Pos             (4U)
13667  #define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
13668  #define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
13669  #define USART_SR_RXNE_Pos             (5U)
13670  #define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
13671  #define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
13672  #define USART_SR_TC_Pos               (6U)
13673  #define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
13674  #define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
13675  #define USART_SR_TXE_Pos              (7U)
13676  #define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
13677  #define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
13678  #define USART_SR_LBD_Pos              (8U)
13679  #define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
13680  #define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
13681  #define USART_SR_CTS_Pos              (9U)
13682  #define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
13683  #define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
13684  
13685  /*******************  Bit definition for USART_DR register  *******************/
13686  #define USART_DR_DR_Pos               (0U)
13687  #define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
13688  #define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
13689  
13690  /******************  Bit definition for USART_BRR register  *******************/
13691  #define USART_BRR_DIV_Fraction_Pos    (0U)
13692  #define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
13693  #define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
13694  #define USART_BRR_DIV_Mantissa_Pos    (4U)
13695  #define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
13696  #define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
13697  
13698  /******************  Bit definition for USART_CR1 register  *******************/
13699  #define USART_CR1_SBK_Pos             (0U)
13700  #define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
13701  #define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
13702  #define USART_CR1_RWU_Pos             (1U)
13703  #define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
13704  #define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
13705  #define USART_CR1_RE_Pos              (2U)
13706  #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
13707  #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
13708  #define USART_CR1_TE_Pos              (3U)
13709  #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
13710  #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
13711  #define USART_CR1_IDLEIE_Pos          (4U)
13712  #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
13713  #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
13714  #define USART_CR1_RXNEIE_Pos          (5U)
13715  #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
13716  #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
13717  #define USART_CR1_TCIE_Pos            (6U)
13718  #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
13719  #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
13720  #define USART_CR1_TXEIE_Pos           (7U)
13721  #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
13722  #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
13723  #define USART_CR1_PEIE_Pos            (8U)
13724  #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
13725  #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
13726  #define USART_CR1_PS_Pos              (9U)
13727  #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
13728  #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
13729  #define USART_CR1_PCE_Pos             (10U)
13730  #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
13731  #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
13732  #define USART_CR1_WAKE_Pos            (11U)
13733  #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
13734  #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
13735  #define USART_CR1_M_Pos               (12U)
13736  #define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
13737  #define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
13738  #define USART_CR1_UE_Pos              (13U)
13739  #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
13740  #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
13741  #define USART_CR1_OVER8_Pos           (15U)
13742  #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
13743  #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
13744  
13745  /******************  Bit definition for USART_CR2 register  *******************/
13746  #define USART_CR2_ADD_Pos             (0U)
13747  #define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
13748  #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
13749  #define USART_CR2_LBDL_Pos            (5U)
13750  #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
13751  #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
13752  #define USART_CR2_LBDIE_Pos           (6U)
13753  #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
13754  #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
13755  #define USART_CR2_LBCL_Pos            (8U)
13756  #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
13757  #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
13758  #define USART_CR2_CPHA_Pos            (9U)
13759  #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
13760  #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
13761  #define USART_CR2_CPOL_Pos            (10U)
13762  #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
13763  #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
13764  #define USART_CR2_CLKEN_Pos           (11U)
13765  #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
13766  #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
13767  
13768  #define USART_CR2_STOP_Pos            (12U)
13769  #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
13770  #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
13771  #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
13772  #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
13773  
13774  #define USART_CR2_LINEN_Pos           (14U)
13775  #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
13776  #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
13777  
13778  /******************  Bit definition for USART_CR3 register  *******************/
13779  #define USART_CR3_EIE_Pos             (0U)
13780  #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
13781  #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
13782  #define USART_CR3_IREN_Pos            (1U)
13783  #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
13784  #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
13785  #define USART_CR3_IRLP_Pos            (2U)
13786  #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
13787  #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
13788  #define USART_CR3_HDSEL_Pos           (3U)
13789  #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
13790  #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
13791  #define USART_CR3_NACK_Pos            (4U)
13792  #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
13793  #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
13794  #define USART_CR3_SCEN_Pos            (5U)
13795  #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
13796  #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
13797  #define USART_CR3_DMAR_Pos            (6U)
13798  #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
13799  #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
13800  #define USART_CR3_DMAT_Pos            (7U)
13801  #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
13802  #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
13803  #define USART_CR3_RTSE_Pos            (8U)
13804  #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
13805  #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
13806  #define USART_CR3_CTSE_Pos            (9U)
13807  #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
13808  #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
13809  #define USART_CR3_CTSIE_Pos           (10U)
13810  #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
13811  #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
13812  #define USART_CR3_ONEBIT_Pos          (11U)
13813  #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
13814  #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
13815  
13816  /******************  Bit definition for USART_GTPR register  ******************/
13817  #define USART_GTPR_PSC_Pos            (0U)
13818  #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
13819  #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
13820  #define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
13821  #define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
13822  #define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
13823  #define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
13824  #define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
13825  #define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
13826  #define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
13827  #define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
13828  
13829  #define USART_GTPR_GT_Pos             (8U)
13830  #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
13831  #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
13832  
13833  /******************************************************************************/
13834  /*                                                                            */
13835  /*                            Window WATCHDOG                                 */
13836  /*                                                                            */
13837  /******************************************************************************/
13838  /*******************  Bit definition for WWDG_CR register  ********************/
13839  #define WWDG_CR_T_Pos           (0U)
13840  #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
13841  #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
13842  #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
13843  #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
13844  #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
13845  #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
13846  #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
13847  #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
13848  #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
13849  /* Legacy defines */
13850  #define  WWDG_CR_T0                          WWDG_CR_T_0
13851  #define  WWDG_CR_T1                          WWDG_CR_T_1
13852  #define  WWDG_CR_T2                          WWDG_CR_T_2
13853  #define  WWDG_CR_T3                          WWDG_CR_T_3
13854  #define  WWDG_CR_T4                          WWDG_CR_T_4
13855  #define  WWDG_CR_T5                          WWDG_CR_T_5
13856  #define  WWDG_CR_T6                          WWDG_CR_T_6
13857  
13858  #define WWDG_CR_WDGA_Pos        (7U)
13859  #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
13860  #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
13861  
13862  /*******************  Bit definition for WWDG_CFR register  *******************/
13863  #define WWDG_CFR_W_Pos          (0U)
13864  #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
13865  #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
13866  #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
13867  #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
13868  #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
13869  #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
13870  #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
13871  #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
13872  #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
13873  /* Legacy defines */
13874  #define  WWDG_CFR_W0                         WWDG_CFR_W_0
13875  #define  WWDG_CFR_W1                         WWDG_CFR_W_1
13876  #define  WWDG_CFR_W2                         WWDG_CFR_W_2
13877  #define  WWDG_CFR_W3                         WWDG_CFR_W_3
13878  #define  WWDG_CFR_W4                         WWDG_CFR_W_4
13879  #define  WWDG_CFR_W5                         WWDG_CFR_W_5
13880  #define  WWDG_CFR_W6                         WWDG_CFR_W_6
13881  
13882  #define WWDG_CFR_WDGTB_Pos      (7U)
13883  #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
13884  #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
13885  #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
13886  #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
13887  /* Legacy defines */
13888  #define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
13889  #define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
13890  
13891  #define WWDG_CFR_EWI_Pos        (9U)
13892  #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
13893  #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
13894  
13895  /*******************  Bit definition for WWDG_SR register  ********************/
13896  #define WWDG_SR_EWIF_Pos        (0U)
13897  #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
13898  #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
13899  
13900  
13901  /******************************************************************************/
13902  /*                                                                            */
13903  /*                                DBG                                         */
13904  /*                                                                            */
13905  /******************************************************************************/
13906  /********************  Bit definition for DBGMCU_IDCODE register  *************/
13907  #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
13908  #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
13909  #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
13910  #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
13911  #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
13912  #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
13913  
13914  /********************  Bit definition for DBGMCU_CR register  *****************/
13915  #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
13916  #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
13917  #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
13918  #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
13919  #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
13920  #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
13921  #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
13922  #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
13923  #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
13924  #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
13925  #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
13926  #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
13927  
13928  #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
13929  #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
13930  #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
13931  #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
13932  #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
13933  
13934  /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
13935  #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
13936  #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
13937  #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13938  #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
13939  #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
13940  #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13941  #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)
13942  #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
13943  #define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13944  #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)
13945  #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
13946  #define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13947  #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
13948  #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
13949  #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13950  #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
13951  #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
13952  #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
13953  #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)
13954  #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
13955  #define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
13956  #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)
13957  #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
13958  #define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
13959  #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
13960  #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
13961  #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
13962  #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
13963  #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
13964  #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
13965  #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
13966  #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
13967  #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
13968  #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
13969  #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
13970  #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
13971  #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
13972  #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
13973  #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
13974  #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
13975  #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
13976  #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
13977  #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)
13978  #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
13979  #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
13980  #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)
13981  #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
13982  #define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
13983  #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)
13984  #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
13985  #define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
13986  /* Old IWDGSTOP bit definition, maintained for legacy purpose */
13987  #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
13988  
13989  /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
13990  #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
13991  #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
13992  #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
13993  #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)
13994  #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
13995  #define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
13996  #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)
13997  #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
13998  #define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
13999  #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)
14000  #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
14001  #define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14002  #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)
14003  #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
14004  #define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14005  
14006  /******************************************************************************/
14007  /*                                                                            */
14008  /*                Ethernet MAC Registers bits definitions                     */
14009  /*                                                                            */
14010  /******************************************************************************/
14011  /* Bit definition for Ethernet MAC Control Register register */
14012  #define ETH_MACCR_WD_Pos                              (23U)
14013  #define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
14014  #define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
14015  #define ETH_MACCR_JD_Pos                              (22U)
14016  #define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
14017  #define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
14018  #define ETH_MACCR_IFG_Pos                             (17U)
14019  #define ETH_MACCR_IFG_Msk                             (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
14020  #define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
14021  #define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
14022  #define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
14023  #define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
14024  #define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
14025  #define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
14026  #define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
14027  #define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
14028  #define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
14029  #define ETH_MACCR_CSD_Pos                             (16U)
14030  #define ETH_MACCR_CSD_Msk                             (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
14031  #define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
14032  #define ETH_MACCR_FES_Pos                             (14U)
14033  #define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
14034  #define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
14035  #define ETH_MACCR_ROD_Pos                             (13U)
14036  #define ETH_MACCR_ROD_Msk                             (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
14037  #define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
14038  #define ETH_MACCR_LM_Pos                              (12U)
14039  #define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
14040  #define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
14041  #define ETH_MACCR_DM_Pos                              (11U)
14042  #define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
14043  #define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
14044  #define ETH_MACCR_IPCO_Pos                            (10U)
14045  #define ETH_MACCR_IPCO_Msk                            (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
14046  #define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
14047  #define ETH_MACCR_RD_Pos                              (9U)
14048  #define ETH_MACCR_RD_Msk                              (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
14049  #define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
14050  #define ETH_MACCR_APCS_Pos                            (7U)
14051  #define ETH_MACCR_APCS_Msk                            (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
14052  #define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
14053  #define ETH_MACCR_BL_Pos                              (5U)
14054  #define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
14055  #define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
14056                                                         a transmission attempt during retries after a collision: 0 =< r <2^k */
14057  #define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
14058  #define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
14059  #define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
14060  #define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */
14061  #define ETH_MACCR_DC_Pos                              (4U)
14062  #define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
14063  #define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
14064  #define ETH_MACCR_TE_Pos                              (3U)
14065  #define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
14066  #define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
14067  #define ETH_MACCR_RE_Pos                              (2U)
14068  #define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
14069  #define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
14070  
14071  /* Bit definition for Ethernet MAC Frame Filter Register */
14072  #define ETH_MACFFR_RA_Pos                             (31U)
14073  #define ETH_MACFFR_RA_Msk                             (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
14074  #define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
14075  #define ETH_MACFFR_HPF_Pos                            (10U)
14076  #define ETH_MACFFR_HPF_Msk                            (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
14077  #define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
14078  #define ETH_MACFFR_SAF_Pos                            (9U)
14079  #define ETH_MACFFR_SAF_Msk                            (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
14080  #define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
14081  #define ETH_MACFFR_SAIF_Pos                           (8U)
14082  #define ETH_MACFFR_SAIF_Msk                           (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
14083  #define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */
14084  #define ETH_MACFFR_PCF_Pos                            (6U)
14085  #define ETH_MACFFR_PCF_Msk                            (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
14086  #define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
14087  #define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)
14088  #define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
14089  #define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
14090  #define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)
14091  #define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
14092  #define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
14093  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)
14094  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
14095  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
14096  #define ETH_MACFFR_BFD_Pos                            (5U)
14097  #define ETH_MACFFR_BFD_Msk                            (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
14098  #define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */
14099  #define ETH_MACFFR_PAM_Pos                            (4U)
14100  #define ETH_MACFFR_PAM_Msk                            (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
14101  #define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
14102  #define ETH_MACFFR_DAIF_Pos                           (3U)
14103  #define ETH_MACFFR_DAIF_Msk                           (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
14104  #define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
14105  #define ETH_MACFFR_HM_Pos                             (2U)
14106  #define ETH_MACFFR_HM_Msk                             (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
14107  #define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */
14108  #define ETH_MACFFR_HU_Pos                             (1U)
14109  #define ETH_MACFFR_HU_Msk                             (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
14110  #define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
14111  #define ETH_MACFFR_PM_Pos                             (0U)
14112  #define ETH_MACFFR_PM_Msk                             (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
14113  #define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
14114  
14115  /* Bit definition for Ethernet MAC Hash Table High Register */
14116  #define ETH_MACHTHR_HTH_Pos                           (0U)
14117  #define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
14118  #define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
14119  
14120  /* Bit definition for Ethernet MAC Hash Table Low Register */
14121  #define ETH_MACHTLR_HTL_Pos                           (0U)
14122  #define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
14123  #define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
14124  
14125  /* Bit definition for Ethernet MAC MII Address Register */
14126  #define ETH_MACMIIAR_PA_Pos                           (11U)
14127  #define ETH_MACMIIAR_PA_Msk                           (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
14128  #define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
14129  #define ETH_MACMIIAR_MR_Pos                           (6U)
14130  #define ETH_MACMIIAR_MR_Msk                           (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
14131  #define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
14132  #define ETH_MACMIIAR_CR_Pos                           (2U)
14133  #define ETH_MACMIIAR_CR_Msk                           (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
14134  #define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
14135  #define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */
14136  #define ETH_MACMIIAR_CR_Div62_Pos                     (2U)
14137  #define ETH_MACMIIAR_CR_Div62_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
14138  #define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */
14139  #define ETH_MACMIIAR_CR_Div16_Pos                     (3U)
14140  #define ETH_MACMIIAR_CR_Div16_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
14141  #define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */
14142  #define ETH_MACMIIAR_CR_Div26_Pos                     (2U)
14143  #define ETH_MACMIIAR_CR_Div26_Msk                     (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
14144  #define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */
14145  #define ETH_MACMIIAR_CR_Div102_Pos                    (4U)
14146  #define ETH_MACMIIAR_CR_Div102_Msk                    (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
14147  #define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
14148  #define ETH_MACMIIAR_MW_Pos                           (1U)
14149  #define ETH_MACMIIAR_MW_Msk                           (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
14150  #define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
14151  #define ETH_MACMIIAR_MB_Pos                           (0U)
14152  #define ETH_MACMIIAR_MB_Msk                           (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
14153  #define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */
14154  
14155  /* Bit definition for Ethernet MAC MII Data Register */
14156  #define ETH_MACMIIDR_MD_Pos                           (0U)
14157  #define ETH_MACMIIDR_MD_Msk                           (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
14158  #define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
14159  
14160  /* Bit definition for Ethernet MAC Flow Control Register */
14161  #define ETH_MACFCR_PT_Pos                             (16U)
14162  #define ETH_MACFCR_PT_Msk                             (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
14163  #define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
14164  #define ETH_MACFCR_ZQPD_Pos                           (7U)
14165  #define ETH_MACFCR_ZQPD_Msk                           (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
14166  #define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
14167  #define ETH_MACFCR_PLT_Pos                            (4U)
14168  #define ETH_MACFCR_PLT_Msk                            (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
14169  #define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
14170  #define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */
14171  #define ETH_MACFCR_PLT_Minus28_Pos                    (4U)
14172  #define ETH_MACFCR_PLT_Minus28_Msk                    (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
14173  #define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */
14174  #define ETH_MACFCR_PLT_Minus144_Pos                   (5U)
14175  #define ETH_MACFCR_PLT_Minus144_Msk                   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
14176  #define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
14177  #define ETH_MACFCR_PLT_Minus256_Pos                   (4U)
14178  #define ETH_MACFCR_PLT_Minus256_Msk                   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
14179  #define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
14180  #define ETH_MACFCR_UPFD_Pos                           (3U)
14181  #define ETH_MACFCR_UPFD_Msk                           (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
14182  #define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
14183  #define ETH_MACFCR_RFCE_Pos                           (2U)
14184  #define ETH_MACFCR_RFCE_Msk                           (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
14185  #define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
14186  #define ETH_MACFCR_TFCE_Pos                           (1U)
14187  #define ETH_MACFCR_TFCE_Msk                           (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
14188  #define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
14189  #define ETH_MACFCR_FCBBPA_Pos                         (0U)
14190  #define ETH_MACFCR_FCBBPA_Msk                         (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
14191  #define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
14192  
14193  /* Bit definition for Ethernet MAC VLAN Tag Register */
14194  #define ETH_MACVLANTR_VLANTC_Pos                      (16U)
14195  #define ETH_MACVLANTR_VLANTC_Msk                      (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
14196  #define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
14197  #define ETH_MACVLANTR_VLANTI_Pos                      (0U)
14198  #define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
14199  #define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
14200  
14201  /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
14202  #define ETH_MACRWUFFR_D_Pos                           (0U)
14203  #define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
14204  #define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
14205  /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
14206     Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
14207  /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
14208     Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
14209     Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
14210     Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
14211     Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
14212                                RSVD - Filter1 Command - RSVD - Filter0 Command
14213     Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
14214     Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
14215     Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
14216  
14217  /* Bit definition for Ethernet MAC PMT Control and Status Register */
14218  #define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)
14219  #define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
14220  #define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
14221  #define ETH_MACPMTCSR_GU_Pos                          (9U)
14222  #define ETH_MACPMTCSR_GU_Msk                          (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
14223  #define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */
14224  #define ETH_MACPMTCSR_WFR_Pos                         (6U)
14225  #define ETH_MACPMTCSR_WFR_Msk                         (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
14226  #define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */
14227  #define ETH_MACPMTCSR_MPR_Pos                         (5U)
14228  #define ETH_MACPMTCSR_MPR_Msk                         (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
14229  #define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */
14230  #define ETH_MACPMTCSR_WFE_Pos                         (2U)
14231  #define ETH_MACPMTCSR_WFE_Msk                         (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
14232  #define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */
14233  #define ETH_MACPMTCSR_MPE_Pos                         (1U)
14234  #define ETH_MACPMTCSR_MPE_Msk                         (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
14235  #define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */
14236  #define ETH_MACPMTCSR_PD_Pos                          (0U)
14237  #define ETH_MACPMTCSR_PD_Msk                          (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
14238  #define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */
14239  
14240  /* Bit definition for Ethernet MAC debug Register */
14241  #define ETH_MACDBGR_TFF_Pos                           (25U)
14242  #define ETH_MACDBGR_TFF_Msk                           (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
14243  #define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
14244  #define ETH_MACDBGR_TFNE_Pos                          (24U)
14245  #define ETH_MACDBGR_TFNE_Msk                          (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
14246  #define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
14247  #define ETH_MACDBGR_TFWA_Pos                          (22U)
14248  #define ETH_MACDBGR_TFWA_Msk                          (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
14249  #define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */
14250  #define ETH_MACDBGR_TFRS_Pos                          (20U)
14251  #define ETH_MACDBGR_TFRS_Msk                          (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
14252  #define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
14253  #define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)
14254  #define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
14255  #define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
14256  #define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)
14257  #define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
14258  #define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
14259  #define ETH_MACDBGR_TFRS_READ_Pos                     (20U)
14260  #define ETH_MACDBGR_TFRS_READ_Msk                     (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
14261  #define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
14262  #define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
14263  #define ETH_MACDBGR_MTP_Pos                           (19U)
14264  #define ETH_MACDBGR_MTP_Msk                           (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
14265  #define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
14266  #define ETH_MACDBGR_MTFCS_Pos                         (17U)
14267  #define ETH_MACDBGR_MTFCS_Msk                         (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
14268  #define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
14269  #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)
14270  #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
14271  #define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
14272  #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)
14273  #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
14274  #define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
14275  #define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)
14276  #define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
14277  #define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
14278  #define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
14279  #define ETH_MACDBGR_MMTEA_Pos                         (16U)
14280  #define ETH_MACDBGR_MMTEA_Msk                         (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
14281  #define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
14282  #define ETH_MACDBGR_RFFL_Pos                          (8U)
14283  #define ETH_MACDBGR_RFFL_Msk                          (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
14284  #define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
14285  #define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)
14286  #define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
14287  #define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
14288  #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)
14289  #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
14290  #define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
14291  #define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)
14292  #define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
14293  #define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
14294  #define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
14295  #define ETH_MACDBGR_RFRCS_Pos                         (5U)
14296  #define ETH_MACDBGR_RFRCS_Msk                         (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
14297  #define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
14298  #define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)
14299  #define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
14300  #define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
14301  #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)
14302  #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
14303  #define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
14304  #define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)
14305  #define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
14306  #define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
14307  #define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
14308  #define ETH_MACDBGR_RFWRA_Pos                         (4U)
14309  #define ETH_MACDBGR_RFWRA_Msk                         (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
14310  #define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
14311  #define ETH_MACDBGR_MSFRWCS_Pos                       (1U)
14312  #define ETH_MACDBGR_MSFRWCS_Msk                       (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
14313  #define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
14314  #define ETH_MACDBGR_MSFRWCS_1                         (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
14315  #define ETH_MACDBGR_MSFRWCS_0                         (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
14316  #define ETH_MACDBGR_MMRPEA_Pos                        (0U)
14317  #define ETH_MACDBGR_MMRPEA_Msk                        (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
14318  #define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
14319  
14320  /* Bit definition for Ethernet MAC Status Register */
14321  #define ETH_MACSR_TSTS_Pos                            (9U)
14322  #define ETH_MACSR_TSTS_Msk                            (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
14323  #define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
14324  #define ETH_MACSR_MMCTS_Pos                           (6U)
14325  #define ETH_MACSR_MMCTS_Msk                           (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
14326  #define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */
14327  #define ETH_MACSR_MMMCRS_Pos                          (5U)
14328  #define ETH_MACSR_MMMCRS_Msk                          (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
14329  #define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */
14330  #define ETH_MACSR_MMCS_Pos                            (4U)
14331  #define ETH_MACSR_MMCS_Msk                            (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
14332  #define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */
14333  #define ETH_MACSR_PMTS_Pos                            (3U)
14334  #define ETH_MACSR_PMTS_Msk                            (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
14335  #define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */
14336  
14337  /* Bit definition for Ethernet MAC Interrupt Mask Register */
14338  #define ETH_MACIMR_TSTIM_Pos                          (9U)
14339  #define ETH_MACIMR_TSTIM_Msk                          (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
14340  #define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
14341  #define ETH_MACIMR_PMTIM_Pos                          (3U)
14342  #define ETH_MACIMR_PMTIM_Msk                          (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
14343  #define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */
14344  
14345  /* Bit definition for Ethernet MAC Address0 High Register */
14346  #define ETH_MACA0HR_MACA0H_Pos                        (0U)
14347  #define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
14348  #define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
14349  
14350  /* Bit definition for Ethernet MAC Address0 Low Register */
14351  #define ETH_MACA0LR_MACA0L_Pos                        (0U)
14352  #define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
14353  #define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
14354  
14355  /* Bit definition for Ethernet MAC Address1 High Register */
14356  #define ETH_MACA1HR_AE_Pos                            (31U)
14357  #define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
14358  #define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
14359  #define ETH_MACA1HR_SA_Pos                            (30U)
14360  #define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
14361  #define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
14362  #define ETH_MACA1HR_MBC_Pos                           (24U)
14363  #define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
14364  #define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
14365  #define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
14366  #define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
14367  #define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
14368  #define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
14369  #define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
14370  #define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */
14371  #define ETH_MACA1HR_MACA1H_Pos                        (0U)
14372  #define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
14373  #define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
14374  
14375  /* Bit definition for Ethernet MAC Address1 Low Register */
14376  #define ETH_MACA1LR_MACA1L_Pos                        (0U)
14377  #define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
14378  #define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
14379  
14380  /* Bit definition for Ethernet MAC Address2 High Register */
14381  #define ETH_MACA2HR_AE_Pos                            (31U)
14382  #define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
14383  #define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
14384  #define ETH_MACA2HR_SA_Pos                            (30U)
14385  #define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
14386  #define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
14387  #define ETH_MACA2HR_MBC_Pos                           (24U)
14388  #define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
14389  #define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
14390  #define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
14391  #define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
14392  #define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
14393  #define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
14394  #define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
14395  #define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
14396  #define ETH_MACA2HR_MACA2H_Pos                        (0U)
14397  #define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
14398  #define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
14399  
14400  /* Bit definition for Ethernet MAC Address2 Low Register */
14401  #define ETH_MACA2LR_MACA2L_Pos                        (0U)
14402  #define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
14403  #define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
14404  
14405  /* Bit definition for Ethernet MAC Address3 High Register */
14406  #define ETH_MACA3HR_AE_Pos                            (31U)
14407  #define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
14408  #define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
14409  #define ETH_MACA3HR_SA_Pos                            (30U)
14410  #define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
14411  #define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
14412  #define ETH_MACA3HR_MBC_Pos                           (24U)
14413  #define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
14414  #define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
14415  #define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
14416  #define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
14417  #define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
14418  #define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
14419  #define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
14420  #define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
14421  #define ETH_MACA3HR_MACA3H_Pos                        (0U)
14422  #define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
14423  #define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
14424  
14425  /* Bit definition for Ethernet MAC Address3 Low Register */
14426  #define ETH_MACA3LR_MACA3L_Pos                        (0U)
14427  #define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
14428  #define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
14429  
14430  /******************************************************************************/
14431  /*                Ethernet MMC Registers bits definition                      */
14432  /******************************************************************************/
14433  
14434  /* Bit definition for Ethernet MMC Contol Register */
14435  #define ETH_MMCCR_MCFHP_Pos                           (5U)
14436  #define ETH_MMCCR_MCFHP_Msk                           (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
14437  #define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
14438  #define ETH_MMCCR_MCP_Pos                             (4U)
14439  #define ETH_MMCCR_MCP_Msk                             (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
14440  #define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */
14441  #define ETH_MMCCR_MCF_Pos                             (3U)
14442  #define ETH_MMCCR_MCF_Msk                             (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
14443  #define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */
14444  #define ETH_MMCCR_ROR_Pos                             (2U)
14445  #define ETH_MMCCR_ROR_Msk                             (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
14446  #define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */
14447  #define ETH_MMCCR_CSR_Pos                             (1U)
14448  #define ETH_MMCCR_CSR_Msk                             (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
14449  #define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */
14450  #define ETH_MMCCR_CR_Pos                              (0U)
14451  #define ETH_MMCCR_CR_Msk                              (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
14452  #define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */
14453  
14454  /* Bit definition for Ethernet MMC Receive Interrupt Register */
14455  #define ETH_MMCRIR_RGUFS_Pos                          (17U)
14456  #define ETH_MMCRIR_RGUFS_Msk                          (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
14457  #define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
14458  #define ETH_MMCRIR_RFAES_Pos                          (6U)
14459  #define ETH_MMCRIR_RFAES_Msk                          (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
14460  #define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
14461  #define ETH_MMCRIR_RFCES_Pos                          (5U)
14462  #define ETH_MMCRIR_RFCES_Msk                          (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
14463  #define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
14464  
14465  /* Bit definition for Ethernet MMC Transmit Interrupt Register */
14466  #define ETH_MMCTIR_TGFS_Pos                           (21U)
14467  #define ETH_MMCTIR_TGFS_Msk                           (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
14468  #define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
14469  #define ETH_MMCTIR_TGFMSCS_Pos                        (15U)
14470  #define ETH_MMCTIR_TGFMSCS_Msk                        (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
14471  #define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
14472  #define ETH_MMCTIR_TGFSCS_Pos                         (14U)
14473  #define ETH_MMCTIR_TGFSCS_Msk                         (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
14474  #define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
14475  
14476  /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
14477  #define ETH_MMCRIMR_RGUFM_Pos                         (17U)
14478  #define ETH_MMCRIMR_RGUFM_Msk                         (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
14479  #define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
14480  #define ETH_MMCRIMR_RFAEM_Pos                         (6U)
14481  #define ETH_MMCRIMR_RFAEM_Msk                         (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
14482  #define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
14483  #define ETH_MMCRIMR_RFCEM_Pos                         (5U)
14484  #define ETH_MMCRIMR_RFCEM_Msk                         (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
14485  #define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
14486  
14487  /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
14488  #define ETH_MMCTIMR_TGFM_Pos                          (21U)
14489  #define ETH_MMCTIMR_TGFM_Msk                          (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
14490  #define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
14491  #define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)
14492  #define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
14493  #define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
14494  #define ETH_MMCTIMR_TGFSCM_Pos                        (14U)
14495  #define ETH_MMCTIMR_TGFSCM_Msk                        (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
14496  #define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
14497  
14498  /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
14499  #define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)
14500  #define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
14501  #define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
14502  
14503  /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
14504  #define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)
14505  #define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
14506  #define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
14507  
14508  /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
14509  #define ETH_MMCTGFCR_TGFC_Pos                         (0U)
14510  #define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
14511  #define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
14512  
14513  /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
14514  #define ETH_MMCRFCECR_RFCEC_Pos                       (0U)
14515  #define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
14516  #define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
14517  
14518  /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
14519  #define ETH_MMCRFAECR_RFAEC_Pos                       (0U)
14520  #define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
14521  #define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
14522  
14523  /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
14524  #define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)
14525  #define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
14526  #define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
14527  
14528  /******************************************************************************/
14529  /*               Ethernet PTP Registers bits definition                       */
14530  /******************************************************************************/
14531  
14532  /* Bit definition for Ethernet PTP Time Stamp Contol Register */
14533  #define ETH_PTPTSCR_TSCNT_Pos                         (16U)
14534  #define ETH_PTPTSCR_TSCNT_Msk                         (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
14535  #define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
14536  #define ETH_PTPTSSR_TSSMRME_Pos                       (15U)
14537  #define ETH_PTPTSSR_TSSMRME_Msk                       (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
14538  #define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
14539  #define ETH_PTPTSSR_TSSEME_Pos                        (14U)
14540  #define ETH_PTPTSSR_TSSEME_Msk                        (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
14541  #define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
14542  #define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)
14543  #define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
14544  #define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
14545  #define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)
14546  #define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
14547  #define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
14548  #define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)
14549  #define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
14550  #define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
14551  #define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)
14552  #define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
14553  #define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
14554  #define ETH_PTPTSSR_TSSSR_Pos                         (9U)
14555  #define ETH_PTPTSSR_TSSSR_Msk                         (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
14556  #define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
14557  #define ETH_PTPTSSR_TSSARFE_Pos                       (8U)
14558  #define ETH_PTPTSSR_TSSARFE_Msk                       (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
14559  #define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
14560  
14561  #define ETH_PTPTSCR_TSARU_Pos                         (5U)
14562  #define ETH_PTPTSCR_TSARU_Msk                         (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
14563  #define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
14564  #define ETH_PTPTSCR_TSITE_Pos                         (4U)
14565  #define ETH_PTPTSCR_TSITE_Msk                         (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
14566  #define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
14567  #define ETH_PTPTSCR_TSSTU_Pos                         (3U)
14568  #define ETH_PTPTSCR_TSSTU_Msk                         (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
14569  #define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
14570  #define ETH_PTPTSCR_TSSTI_Pos                         (2U)
14571  #define ETH_PTPTSCR_TSSTI_Msk                         (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
14572  #define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
14573  #define ETH_PTPTSCR_TSFCU_Pos                         (1U)
14574  #define ETH_PTPTSCR_TSFCU_Msk                         (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
14575  #define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
14576  #define ETH_PTPTSCR_TSE_Pos                           (0U)
14577  #define ETH_PTPTSCR_TSE_Msk                           (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
14578  #define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
14579  
14580  /* Bit definition for Ethernet PTP Sub-Second Increment Register */
14581  #define ETH_PTPSSIR_STSSI_Pos                         (0U)
14582  #define ETH_PTPSSIR_STSSI_Msk                         (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
14583  #define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
14584  
14585  /* Bit definition for Ethernet PTP Time Stamp High Register */
14586  #define ETH_PTPTSHR_STS_Pos                           (0U)
14587  #define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
14588  #define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
14589  
14590  /* Bit definition for Ethernet PTP Time Stamp Low Register */
14591  #define ETH_PTPTSLR_STPNS_Pos                         (31U)
14592  #define ETH_PTPTSLR_STPNS_Msk                         (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
14593  #define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
14594  #define ETH_PTPTSLR_STSS_Pos                          (0U)
14595  #define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
14596  #define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
14597  
14598  /* Bit definition for Ethernet PTP Time Stamp High Update Register */
14599  #define ETH_PTPTSHUR_TSUS_Pos                         (0U)
14600  #define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
14601  #define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
14602  
14603  /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
14604  #define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)
14605  #define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
14606  #define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
14607  #define ETH_PTPTSLUR_TSUSS_Pos                        (0U)
14608  #define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
14609  #define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
14610  
14611  /* Bit definition for Ethernet PTP Time Stamp Addend Register */
14612  #define ETH_PTPTSAR_TSA_Pos                           (0U)
14613  #define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
14614  #define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
14615  
14616  /* Bit definition for Ethernet PTP Target Time High Register */
14617  #define ETH_PTPTTHR_TTSH_Pos                          (0U)
14618  #define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
14619  #define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
14620  
14621  /* Bit definition for Ethernet PTP Target Time Low Register */
14622  #define ETH_PTPTTLR_TTSL_Pos                          (0U)
14623  #define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
14624  #define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
14625  
14626  /* Bit definition for Ethernet PTP Time Stamp Status Register */
14627  #define ETH_PTPTSSR_TSTTR_Pos                         (5U)
14628  #define ETH_PTPTSSR_TSTTR_Msk                         (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
14629  #define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
14630  #define ETH_PTPTSSR_TSSO_Pos                          (4U)
14631  #define ETH_PTPTSSR_TSSO_Msk                          (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
14632  #define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
14633  
14634  /******************************************************************************/
14635  /*                 Ethernet DMA Registers bits definition                     */
14636  /******************************************************************************/
14637  
14638  /* Bit definition for Ethernet DMA Bus Mode Register */
14639  #define ETH_DMABMR_AAB_Pos                            (25U)
14640  #define ETH_DMABMR_AAB_Msk                            (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
14641  #define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
14642  #define ETH_DMABMR_FPM_Pos                            (24U)
14643  #define ETH_DMABMR_FPM_Msk                            (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
14644  #define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
14645  #define ETH_DMABMR_USP_Pos                            (23U)
14646  #define ETH_DMABMR_USP_Msk                            (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
14647  #define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
14648  #define ETH_DMABMR_RDP_Pos                            (17U)
14649  #define ETH_DMABMR_RDP_Msk                            (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
14650  #define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
14651  #define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
14652  #define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
14653  #define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
14654  #define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
14655  #define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
14656  #define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
14657  #define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
14658  #define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
14659  #define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
14660  #define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
14661  #define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
14662  #define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
14663  #define ETH_DMABMR_FB_Pos                             (16U)
14664  #define ETH_DMABMR_FB_Msk                             (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
14665  #define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
14666  #define ETH_DMABMR_RTPR_Pos                           (14U)
14667  #define ETH_DMABMR_RTPR_Msk                           (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
14668  #define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
14669  #define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
14670  #define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
14671  #define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
14672  #define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */
14673  #define ETH_DMABMR_PBL_Pos                            (8U)
14674  #define ETH_DMABMR_PBL_Msk                            (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
14675  #define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
14676  #define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
14677  #define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
14678  #define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
14679  #define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
14680  #define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
14681  #define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
14682  #define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
14683  #define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
14684  #define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
14685  #define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
14686  #define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
14687  #define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
14688  #define ETH_DMABMR_EDE_Pos                            (7U)
14689  #define ETH_DMABMR_EDE_Msk                            (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
14690  #define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
14691  #define ETH_DMABMR_DSL_Pos                            (2U)
14692  #define ETH_DMABMR_DSL_Msk                            (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
14693  #define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
14694  #define ETH_DMABMR_DA_Pos                             (1U)
14695  #define ETH_DMABMR_DA_Msk                             (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
14696  #define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
14697  #define ETH_DMABMR_SR_Pos                             (0U)
14698  #define ETH_DMABMR_SR_Msk                             (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
14699  #define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
14700  
14701  /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
14702  #define ETH_DMATPDR_TPD_Pos                           (0U)
14703  #define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
14704  #define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
14705  
14706  /* Bit definition for Ethernet DMA Receive Poll Demand Register */
14707  #define ETH_DMARPDR_RPD_Pos                           (0U)
14708  #define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
14709  #define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
14710  
14711  /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
14712  #define ETH_DMARDLAR_SRL_Pos                          (0U)
14713  #define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
14714  #define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
14715  
14716  /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
14717  #define ETH_DMATDLAR_STL_Pos                          (0U)
14718  #define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
14719  #define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
14720  
14721  /* Bit definition for Ethernet DMA Status Register */
14722  #define ETH_DMASR_TSTS_Pos                            (29U)
14723  #define ETH_DMASR_TSTS_Msk                            (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
14724  #define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
14725  #define ETH_DMASR_PMTS_Pos                            (28U)
14726  #define ETH_DMASR_PMTS_Msk                            (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
14727  #define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
14728  #define ETH_DMASR_MMCS_Pos                            (27U)
14729  #define ETH_DMASR_MMCS_Msk                            (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
14730  #define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
14731  #define ETH_DMASR_EBS_Pos                             (23U)
14732  #define ETH_DMASR_EBS_Msk                             (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
14733  #define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
14734    /* combination with EBS[2:0] for GetFlagStatus function */
14735  #define ETH_DMASR_EBS_DescAccess_Pos                  (25U)
14736  #define ETH_DMASR_EBS_DescAccess_Msk                  (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
14737  #define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
14738  #define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)
14739  #define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
14740  #define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
14741  #define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)
14742  #define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
14743  #define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
14744  #define ETH_DMASR_TPS_Pos                             (20U)
14745  #define ETH_DMASR_TPS_Msk                             (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
14746  #define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
14747  #define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
14748  #define ETH_DMASR_TPS_Fetching_Pos                    (20U)
14749  #define ETH_DMASR_TPS_Fetching_Msk                    (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
14750  #define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
14751  #define ETH_DMASR_TPS_Waiting_Pos                     (21U)
14752  #define ETH_DMASR_TPS_Waiting_Msk                     (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
14753  #define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
14754  #define ETH_DMASR_TPS_Reading_Pos                     (20U)
14755  #define ETH_DMASR_TPS_Reading_Msk                     (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
14756  #define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
14757  #define ETH_DMASR_TPS_Suspended_Pos                   (21U)
14758  #define ETH_DMASR_TPS_Suspended_Msk                   (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
14759  #define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
14760  #define ETH_DMASR_TPS_Closing_Pos                     (20U)
14761  #define ETH_DMASR_TPS_Closing_Msk                     (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
14762  #define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
14763  #define ETH_DMASR_RPS_Pos                             (17U)
14764  #define ETH_DMASR_RPS_Msk                             (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
14765  #define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
14766  #define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
14767  #define ETH_DMASR_RPS_Fetching_Pos                    (17U)
14768  #define ETH_DMASR_RPS_Fetching_Msk                    (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
14769  #define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
14770  #define ETH_DMASR_RPS_Waiting_Pos                     (17U)
14771  #define ETH_DMASR_RPS_Waiting_Msk                     (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
14772  #define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
14773  #define ETH_DMASR_RPS_Suspended_Pos                   (19U)
14774  #define ETH_DMASR_RPS_Suspended_Msk                   (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
14775  #define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
14776  #define ETH_DMASR_RPS_Closing_Pos                     (17U)
14777  #define ETH_DMASR_RPS_Closing_Msk                     (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
14778  #define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
14779  #define ETH_DMASR_RPS_Queuing_Pos                     (17U)
14780  #define ETH_DMASR_RPS_Queuing_Msk                     (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
14781  #define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
14782  #define ETH_DMASR_NIS_Pos                             (16U)
14783  #define ETH_DMASR_NIS_Msk                             (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
14784  #define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
14785  #define ETH_DMASR_AIS_Pos                             (15U)
14786  #define ETH_DMASR_AIS_Msk                             (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
14787  #define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
14788  #define ETH_DMASR_ERS_Pos                             (14U)
14789  #define ETH_DMASR_ERS_Msk                             (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
14790  #define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
14791  #define ETH_DMASR_FBES_Pos                            (13U)
14792  #define ETH_DMASR_FBES_Msk                            (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
14793  #define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
14794  #define ETH_DMASR_ETS_Pos                             (10U)
14795  #define ETH_DMASR_ETS_Msk                             (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
14796  #define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
14797  #define ETH_DMASR_RWTS_Pos                            (9U)
14798  #define ETH_DMASR_RWTS_Msk                            (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
14799  #define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
14800  #define ETH_DMASR_RPSS_Pos                            (8U)
14801  #define ETH_DMASR_RPSS_Msk                            (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
14802  #define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
14803  #define ETH_DMASR_RBUS_Pos                            (7U)
14804  #define ETH_DMASR_RBUS_Msk                            (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
14805  #define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
14806  #define ETH_DMASR_RS_Pos                              (6U)
14807  #define ETH_DMASR_RS_Msk                              (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
14808  #define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
14809  #define ETH_DMASR_TUS_Pos                             (5U)
14810  #define ETH_DMASR_TUS_Msk                             (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
14811  #define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
14812  #define ETH_DMASR_ROS_Pos                             (4U)
14813  #define ETH_DMASR_ROS_Msk                             (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
14814  #define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
14815  #define ETH_DMASR_TJTS_Pos                            (3U)
14816  #define ETH_DMASR_TJTS_Msk                            (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
14817  #define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
14818  #define ETH_DMASR_TBUS_Pos                            (2U)
14819  #define ETH_DMASR_TBUS_Msk                            (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
14820  #define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
14821  #define ETH_DMASR_TPSS_Pos                            (1U)
14822  #define ETH_DMASR_TPSS_Msk                            (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
14823  #define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
14824  #define ETH_DMASR_TS_Pos                              (0U)
14825  #define ETH_DMASR_TS_Msk                              (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
14826  #define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
14827  
14828  /* Bit definition for Ethernet DMA Operation Mode Register */
14829  #define ETH_DMAOMR_DTCEFD_Pos                         (26U)
14830  #define ETH_DMAOMR_DTCEFD_Msk                         (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
14831  #define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
14832  #define ETH_DMAOMR_RSF_Pos                            (25U)
14833  #define ETH_DMAOMR_RSF_Msk                            (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
14834  #define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
14835  #define ETH_DMAOMR_DFRF_Pos                           (24U)
14836  #define ETH_DMAOMR_DFRF_Msk                           (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
14837  #define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
14838  #define ETH_DMAOMR_TSF_Pos                            (21U)
14839  #define ETH_DMAOMR_TSF_Msk                            (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
14840  #define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
14841  #define ETH_DMAOMR_FTF_Pos                            (20U)
14842  #define ETH_DMAOMR_FTF_Msk                            (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
14843  #define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
14844  #define ETH_DMAOMR_TTC_Pos                            (14U)
14845  #define ETH_DMAOMR_TTC_Msk                            (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
14846  #define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
14847  #define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
14848  #define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
14849  #define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
14850  #define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
14851  #define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
14852  #define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
14853  #define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
14854  #define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
14855  #define ETH_DMAOMR_ST_Pos                             (13U)
14856  #define ETH_DMAOMR_ST_Msk                             (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
14857  #define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
14858  #define ETH_DMAOMR_FEF_Pos                            (7U)
14859  #define ETH_DMAOMR_FEF_Msk                            (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
14860  #define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
14861  #define ETH_DMAOMR_FUGF_Pos                           (6U)
14862  #define ETH_DMAOMR_FUGF_Msk                           (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
14863  #define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
14864  #define ETH_DMAOMR_RTC_Pos                            (3U)
14865  #define ETH_DMAOMR_RTC_Msk                            (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
14866  #define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
14867  #define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
14868  #define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
14869  #define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
14870  #define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
14871  #define ETH_DMAOMR_OSF_Pos                            (2U)
14872  #define ETH_DMAOMR_OSF_Msk                            (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
14873  #define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
14874  #define ETH_DMAOMR_SR_Pos                             (1U)
14875  #define ETH_DMAOMR_SR_Msk                             (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
14876  #define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
14877  
14878  /* Bit definition for Ethernet DMA Interrupt Enable Register */
14879  #define ETH_DMAIER_NISE_Pos                           (16U)
14880  #define ETH_DMAIER_NISE_Msk                           (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
14881  #define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
14882  #define ETH_DMAIER_AISE_Pos                           (15U)
14883  #define ETH_DMAIER_AISE_Msk                           (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
14884  #define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
14885  #define ETH_DMAIER_ERIE_Pos                           (14U)
14886  #define ETH_DMAIER_ERIE_Msk                           (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
14887  #define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
14888  #define ETH_DMAIER_FBEIE_Pos                          (13U)
14889  #define ETH_DMAIER_FBEIE_Msk                          (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
14890  #define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
14891  #define ETH_DMAIER_ETIE_Pos                           (10U)
14892  #define ETH_DMAIER_ETIE_Msk                           (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
14893  #define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
14894  #define ETH_DMAIER_RWTIE_Pos                          (9U)
14895  #define ETH_DMAIER_RWTIE_Msk                          (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
14896  #define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
14897  #define ETH_DMAIER_RPSIE_Pos                          (8U)
14898  #define ETH_DMAIER_RPSIE_Msk                          (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
14899  #define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
14900  #define ETH_DMAIER_RBUIE_Pos                          (7U)
14901  #define ETH_DMAIER_RBUIE_Msk                          (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
14902  #define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
14903  #define ETH_DMAIER_RIE_Pos                            (6U)
14904  #define ETH_DMAIER_RIE_Msk                            (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
14905  #define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
14906  #define ETH_DMAIER_TUIE_Pos                           (5U)
14907  #define ETH_DMAIER_TUIE_Msk                           (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
14908  #define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
14909  #define ETH_DMAIER_ROIE_Pos                           (4U)
14910  #define ETH_DMAIER_ROIE_Msk                           (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
14911  #define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
14912  #define ETH_DMAIER_TJTIE_Pos                          (3U)
14913  #define ETH_DMAIER_TJTIE_Msk                          (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
14914  #define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
14915  #define ETH_DMAIER_TBUIE_Pos                          (2U)
14916  #define ETH_DMAIER_TBUIE_Msk                          (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
14917  #define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
14918  #define ETH_DMAIER_TPSIE_Pos                          (1U)
14919  #define ETH_DMAIER_TPSIE_Msk                          (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
14920  #define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
14921  #define ETH_DMAIER_TIE_Pos                            (0U)
14922  #define ETH_DMAIER_TIE_Msk                            (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
14923  #define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
14924  
14925  /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
14926  #define ETH_DMAMFBOCR_OFOC_Pos                        (28U)
14927  #define ETH_DMAMFBOCR_OFOC_Msk                        (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
14928  #define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
14929  #define ETH_DMAMFBOCR_MFA_Pos                         (17U)
14930  #define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
14931  #define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
14932  #define ETH_DMAMFBOCR_OMFC_Pos                        (16U)
14933  #define ETH_DMAMFBOCR_OMFC_Msk                        (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
14934  #define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
14935  #define ETH_DMAMFBOCR_MFC_Pos                         (0U)
14936  #define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
14937  #define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
14938  
14939  /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
14940  #define ETH_DMACHTDR_HTDAP_Pos                        (0U)
14941  #define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
14942  #define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
14943  
14944  /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
14945  #define ETH_DMACHRDR_HRDAP_Pos                        (0U)
14946  #define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
14947  #define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
14948  
14949  /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
14950  #define ETH_DMACHTBAR_HTBAP_Pos                       (0U)
14951  #define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
14952  #define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
14953  
14954  /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
14955  #define ETH_DMACHRBAR_HRBAP_Pos                       (0U)
14956  #define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
14957  #define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
14958  
14959  /******************************************************************************/
14960  /*                                                                            */
14961  /*                                       USB_OTG                              */
14962  /*                                                                            */
14963  /******************************************************************************/
14964  /********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
14965  #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
14966  #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
14967  #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
14968  #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
14969  #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
14970  #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
14971  #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
14972  #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
14973  #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
14974  #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
14975  #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
14976  #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
14977  #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
14978  #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
14979  #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
14980  #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
14981  #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
14982  #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
14983  #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
14984  #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
14985  #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
14986  #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
14987  #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
14988  #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
14989  #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
14990  #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
14991  #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
14992  #define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)
14993  #define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
14994  #define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */
14995  
14996  /********************  Bit definition forUSB_OTG_HCFG register  ********************/
14997  
14998  #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
14999  #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
15000  #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
15001  #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
15002  #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
15003  #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
15004  #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
15005  #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
15006  
15007  /********************  Bit definition for USB_OTG_DCFG register  ********************/
15008  
15009  #define USB_OTG_DCFG_DSPD_Pos                    (0U)
15010  #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
15011  #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
15012  #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
15013  #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
15014  #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
15015  #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
15016  #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
15017  
15018  #define USB_OTG_DCFG_DAD_Pos                     (4U)
15019  #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
15020  #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
15021  #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
15022  #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
15023  #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
15024  #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
15025  #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
15026  #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
15027  #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
15028  
15029  #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
15030  #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
15031  #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
15032  #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
15033  #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
15034  
15035  #define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
15036  #define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
15037  #define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
15038  
15039  #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
15040  #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
15041  #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
15042  
15043  #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
15044  #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
15045  #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
15046  #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
15047  #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
15048  
15049  /********************  Bit definition for USB_OTG_PCGCR register  ********************/
15050  #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
15051  #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
15052  #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
15053  #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
15054  #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
15055  #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
15056  #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
15057  #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
15058  #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
15059  
15060  /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
15061  #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
15062  #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
15063  #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
15064  #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
15065  #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
15066  #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
15067  #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
15068  #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
15069  #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
15070  #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
15071  #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
15072  #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
15073  #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
15074  #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
15075  #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
15076  #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
15077  #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
15078  #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
15079  
15080  /********************  Bit definition for USB_OTG_DCTL register  ********************/
15081  #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
15082  #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
15083  #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
15084  #define USB_OTG_DCTL_SDIS_Pos                    (1U)
15085  #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
15086  #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
15087  #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
15088  #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
15089  #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
15090  #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
15091  #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
15092  #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
15093  
15094  #define USB_OTG_DCTL_TCTL_Pos                    (4U)
15095  #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
15096  #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
15097  #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
15098  #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
15099  #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
15100  #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
15101  #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
15102  #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
15103  #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
15104  #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
15105  #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
15106  #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
15107  #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
15108  #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
15109  #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
15110  #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
15111  #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
15112  #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
15113  #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
15114  #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
15115  
15116  /********************  Bit definition for USB_OTG_HFIR register  ********************/
15117  #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
15118  #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
15119  #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
15120  
15121  /********************  Bit definition for USB_OTG_HFNUM register  ********************/
15122  #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
15123  #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
15124  #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
15125  #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
15126  #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
15127  #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
15128  
15129  /********************  Bit definition for USB_OTG_DSTS register  ********************/
15130  #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
15131  #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
15132  #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
15133  
15134  #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
15135  #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
15136  #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
15137  #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
15138  #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
15139  #define USB_OTG_DSTS_EERR_Pos                    (3U)
15140  #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
15141  #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
15142  #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
15143  #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
15144  #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
15145  
15146  /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
15147  #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
15148  #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
15149  #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
15150  #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
15151  #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
15152  #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
15153  #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
15154  #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
15155  #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
15156  #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
15157  #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
15158  #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
15159  #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
15160  #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
15161  #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
15162  #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
15163  #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
15164  #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
15165  #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
15166  #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
15167  
15168  /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
15169  
15170  #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
15171  #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
15172  #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
15173  #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
15174  #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
15175  #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
15176  #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
15177  #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
15178  #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
15179  #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
15180  #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
15181  #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
15182  #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
15183  #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
15184  #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
15185  #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
15186  #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
15187  #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
15188  #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
15189  #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
15190  #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
15191  #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
15192  #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
15193  #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
15194  #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
15195  #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
15196  #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
15197  #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
15198  #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
15199  #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
15200  #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
15201  #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
15202  #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
15203  #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
15204  #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
15205  #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
15206  #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
15207  #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
15208  #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
15209  #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
15210  #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
15211  #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
15212  #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
15213  #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
15214  #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
15215  #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
15216  #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
15217  #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
15218  #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
15219  #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
15220  #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
15221  #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
15222  #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
15223  #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
15224  #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
15225  #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
15226  #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
15227  #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
15228  #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
15229  #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
15230  #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
15231  
15232  /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
15233  #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
15234  #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
15235  #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
15236  #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
15237  #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
15238  #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
15239  #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
15240  #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
15241  #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
15242  #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
15243  #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
15244  #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
15245  #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
15246  #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
15247  #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
15248  
15249  
15250  #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
15251  #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
15252  #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
15253  #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
15254  #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
15255  #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
15256  #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
15257  #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
15258  #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
15259  #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
15260  #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
15261  #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
15262  #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
15263  #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
15264  
15265  /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
15266  #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
15267  #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
15268  #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
15269  #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
15270  #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
15271  #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
15272  #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
15273  #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
15274  #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
15275  #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
15276  #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
15277  #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
15278  #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
15279  #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
15280  #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
15281  #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
15282  #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
15283  #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
15284  #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
15285  #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
15286  #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
15287  #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
15288  #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
15289  #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
15290  
15291  /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
15292  #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
15293  #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
15294  #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
15295  #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
15296  #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
15297  #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
15298  #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
15299  #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
15300  #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
15301  #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
15302  #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
15303  #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
15304  #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
15305  #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
15306  
15307  #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
15308  #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
15309  #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
15310  #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
15311  #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
15312  #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
15313  #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
15314  #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
15315  #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
15316  #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
15317  #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
15318  
15319  /********************  Bit definition for USB_OTG_HAINT register  ********************/
15320  #define USB_OTG_HAINT_HAINT_Pos                  (0U)
15321  #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
15322  #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
15323  
15324  /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
15325  #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
15326  #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
15327  #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */
15328  #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
15329  #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
15330  #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
15331  #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
15332  #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
15333  #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
15334  #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
15335  #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
15336  #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
15337  #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
15338  #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
15339  #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
15340  #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
15341  #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
15342  #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
15343  #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
15344  #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
15345  #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
15346  #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
15347  #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
15348  #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
15349  #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
15350  #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
15351  #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
15352  #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
15353  #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
15354  #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
15355  #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
15356  #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
15357  #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
15358  #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
15359  #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
15360  #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
15361  /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
15362  #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
15363  #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
15364  #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
15365  #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
15366  #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
15367  #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
15368  #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
15369  #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
15370  #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
15371  #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
15372  #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
15373  #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
15374  #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
15375  #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
15376  #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
15377  #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
15378  #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
15379  #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
15380  #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
15381  #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
15382  #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
15383  #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
15384  #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
15385  #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
15386  #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
15387  #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
15388  #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
15389  #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
15390  #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
15391  #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
15392  #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
15393  #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
15394  #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
15395  #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
15396  #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
15397  #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
15398  #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
15399  #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
15400  #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
15401  #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
15402  #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
15403  #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
15404  #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
15405  #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
15406  #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
15407  #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
15408  #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
15409  #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
15410  #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
15411  #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
15412  #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
15413  #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
15414  #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
15415  #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
15416  #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
15417  #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
15418  #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
15419  #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
15420  #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
15421  #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
15422  #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
15423  #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
15424  #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
15425  #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
15426  #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
15427  #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
15428  #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
15429  #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
15430  #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
15431  #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
15432  #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
15433  #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
15434  #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
15435  #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
15436  #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
15437  #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
15438  #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
15439  #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
15440  
15441  /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
15442  #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
15443  #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
15444  #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
15445  #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
15446  #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
15447  #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
15448  #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
15449  #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
15450  #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
15451  #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
15452  #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
15453  #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
15454  #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
15455  #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
15456  #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
15457  #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
15458  #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
15459  #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
15460  #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
15461  #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
15462  #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
15463  #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
15464  #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
15465  #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
15466  #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
15467  #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
15468  #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
15469  #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
15470  #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
15471  #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
15472  #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
15473  #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
15474  #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
15475  #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
15476  #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
15477  #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
15478  #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
15479  #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
15480  #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
15481  #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
15482  #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
15483  #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
15484  #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
15485  #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
15486  #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
15487  #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
15488  #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
15489  #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
15490  #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
15491  #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
15492  #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
15493  #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
15494  #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
15495  #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
15496  #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
15497  #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
15498  #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
15499  #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
15500  #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
15501  #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
15502  #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
15503  #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
15504  #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
15505  #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
15506  #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
15507  #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
15508  #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
15509  #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
15510  #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
15511  #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
15512  #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
15513  #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
15514  #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
15515  #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
15516  #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
15517  #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
15518  #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
15519  #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
15520  
15521  /********************  Bit definition for USB_OTG_DAINT register  ********************/
15522  #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
15523  #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
15524  #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
15525  #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
15526  #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
15527  #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
15528  
15529  /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
15530  #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
15531  #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
15532  #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
15533  
15534  /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
15535  #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
15536  #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
15537  #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
15538  #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
15539  #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
15540  #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
15541  #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
15542  #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
15543  #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
15544  #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
15545  #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
15546  #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
15547  
15548  /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
15549  #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
15550  #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
15551  #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
15552  #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
15553  #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
15554  #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
15555  
15556  /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
15557  #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
15558  #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
15559  #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
15560  
15561  /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
15562  #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
15563  #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
15564  #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
15565  
15566  /********************  Bit definition for OTG register  ********************/
15567  #define USB_OTG_NPTXFSA_Pos                      (0U)
15568  #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
15569  #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
15570  #define USB_OTG_NPTXFD_Pos                       (16U)
15571  #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
15572  #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
15573  #define USB_OTG_TX0FSA_Pos                       (0U)
15574  #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
15575  #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
15576  #define USB_OTG_TX0FD_Pos                        (16U)
15577  #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
15578  #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
15579  
15580  /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
15581  #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
15582  #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
15583  #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
15584  
15585  /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
15586  #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
15587  #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
15588  #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
15589  
15590  #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
15591  #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
15592  #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
15593  #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
15594  #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
15595  #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
15596  #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
15597  #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
15598  #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
15599  #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
15600  #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
15601  
15602  #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
15603  #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
15604  #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
15605  #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
15606  #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
15607  #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
15608  #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
15609  #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
15610  #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
15611  #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
15612  
15613  /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
15614  #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
15615  #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
15616  #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
15617  #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
15618  #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
15619  #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
15620  
15621  #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
15622  #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
15623  #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
15624  #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
15625  #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
15626  #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
15627  #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
15628  #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
15629  #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
15630  #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
15631  #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
15632  #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
15633  #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
15634  #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
15635  #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
15636  
15637  #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
15638  #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
15639  #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
15640  #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
15641  #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
15642  #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
15643  #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
15644  #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
15645  #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
15646  #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
15647  #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
15648  #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
15649  #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
15650  #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
15651  #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
15652  
15653  /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
15654  #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
15655  #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
15656  #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
15657  
15658  /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
15659  #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
15660  #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
15661  #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
15662  #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
15663  #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
15664  #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
15665  
15666  /********************  Bit definition for USB_OTG_GCCFG register  ********************/
15667  #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
15668  #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
15669  #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
15670  #define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)
15671  #define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
15672  #define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/
15673  #define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)
15674  #define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
15675  #define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */
15676  #define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)
15677  #define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
15678  #define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */
15679  #define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)
15680  #define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
15681  #define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */
15682  #define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)
15683  #define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
15684  #define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/
15685  
15686  /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
15687  #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
15688  #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
15689  #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
15690  #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
15691  #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
15692  #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
15693  
15694  /********************  Bit definition for USB_OTG_CID register  ********************/
15695  #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
15696  #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
15697  #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
15698  
15699  /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
15700  #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
15701  #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
15702  #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
15703  #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
15704  #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
15705  #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
15706  #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
15707  #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
15708  #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
15709  #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
15710  #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
15711  #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
15712  #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
15713  #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
15714  #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
15715  #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
15716  #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
15717  #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
15718  #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
15719  #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
15720  #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
15721  #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
15722  #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
15723  #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
15724  #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
15725  #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
15726  #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
15727  
15728  /********************  Bit definition for USB_OTG_HPRT register  ********************/
15729  #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
15730  #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
15731  #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
15732  #define USB_OTG_HPRT_PCDET_Pos                   (1U)
15733  #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
15734  #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
15735  #define USB_OTG_HPRT_PENA_Pos                    (2U)
15736  #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
15737  #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
15738  #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
15739  #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
15740  #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
15741  #define USB_OTG_HPRT_POCA_Pos                    (4U)
15742  #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
15743  #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
15744  #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
15745  #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
15746  #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
15747  #define USB_OTG_HPRT_PRES_Pos                    (6U)
15748  #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
15749  #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
15750  #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
15751  #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
15752  #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
15753  #define USB_OTG_HPRT_PRST_Pos                    (8U)
15754  #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
15755  #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
15756  
15757  #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
15758  #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
15759  #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
15760  #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
15761  #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
15762  #define USB_OTG_HPRT_PPWR_Pos                    (12U)
15763  #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
15764  #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
15765  
15766  #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
15767  #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
15768  #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
15769  #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
15770  #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
15771  #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
15772  #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
15773  
15774  #define USB_OTG_HPRT_PSPD_Pos                    (17U)
15775  #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
15776  #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
15777  #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
15778  #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
15779  
15780  /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
15781  #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
15782  #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
15783  #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
15784  #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
15785  #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
15786  #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
15787  #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
15788  #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
15789  #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
15790  #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
15791  #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
15792  #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
15793  #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
15794  #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
15795  #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
15796  #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
15797  #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
15798  #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
15799  #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
15800  #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
15801  #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
15802  #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
15803  #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
15804  #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
15805  #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
15806  #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
15807  #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
15808  #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
15809  #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
15810  #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
15811  #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
15812  #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
15813  #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
15814  
15815  /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
15816  #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
15817  #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
15818  #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
15819  #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
15820  #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
15821  #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
15822  
15823  /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
15824  #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
15825  #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
15826  #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
15827  #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
15828  #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
15829  #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
15830  #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
15831  #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
15832  #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
15833  #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
15834  #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
15835  #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
15836  
15837  #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
15838  #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
15839  #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
15840  #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
15841  #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
15842  #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
15843  #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
15844  #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
15845  
15846  #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
15847  #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
15848  #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
15849  #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
15850  #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
15851  #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
15852  #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
15853  #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
15854  #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
15855  #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
15856  #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
15857  #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
15858  #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
15859  #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
15860  #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
15861  #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
15862  #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
15863  #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
15864  #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
15865  #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
15866  #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
15867  #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
15868  #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
15869  #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
15870  #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
15871  
15872  /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
15873  #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
15874  #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
15875  #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
15876  
15877  #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
15878  #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
15879  #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
15880  #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
15881  #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
15882  #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
15883  #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
15884  #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
15885  #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
15886  #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
15887  #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
15888  #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
15889  #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
15890  
15891  #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
15892  #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
15893  #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
15894  #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
15895  #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
15896  
15897  #define USB_OTG_HCCHAR_MC_Pos                    (20U)
15898  #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
15899  #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
15900  #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
15901  #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
15902  
15903  #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
15904  #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
15905  #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
15906  #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
15907  #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
15908  #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
15909  #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
15910  #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
15911  #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
15912  #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
15913  #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
15914  #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
15915  #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
15916  #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
15917  #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
15918  #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
15919  #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
15920  #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
15921  #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
15922  
15923  /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
15924  
15925  #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
15926  #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
15927  #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
15928  #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
15929  #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
15930  #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
15931  #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
15932  #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
15933  #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
15934  #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
15935  
15936  #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
15937  #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
15938  #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
15939  #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
15940  #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
15941  #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
15942  #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
15943  #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
15944  #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
15945  #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
15946  
15947  #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
15948  #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
15949  #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
15950  #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
15951  #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
15952  #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
15953  #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
15954  #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
15955  #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
15956  #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
15957  #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
15958  
15959  /********************  Bit definition for USB_OTG_HCINT register  ********************/
15960  #define USB_OTG_HCINT_XFRC_Pos                   (0U)
15961  #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
15962  #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
15963  #define USB_OTG_HCINT_CHH_Pos                    (1U)
15964  #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
15965  #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
15966  #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
15967  #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
15968  #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
15969  #define USB_OTG_HCINT_STALL_Pos                  (3U)
15970  #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
15971  #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
15972  #define USB_OTG_HCINT_NAK_Pos                    (4U)
15973  #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
15974  #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
15975  #define USB_OTG_HCINT_ACK_Pos                    (5U)
15976  #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
15977  #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
15978  #define USB_OTG_HCINT_NYET_Pos                   (6U)
15979  #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
15980  #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
15981  #define USB_OTG_HCINT_TXERR_Pos                  (7U)
15982  #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
15983  #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
15984  #define USB_OTG_HCINT_BBERR_Pos                  (8U)
15985  #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
15986  #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
15987  #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
15988  #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
15989  #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
15990  #define USB_OTG_HCINT_DTERR_Pos                  (10U)
15991  #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
15992  #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
15993  
15994  /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
15995  #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
15996  #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
15997  #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
15998  #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
15999  #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
16000  #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
16001  #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
16002  #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
16003  #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
16004  #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
16005  #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
16006  #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
16007  #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
16008  #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
16009  #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
16010  #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
16011  #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
16012  #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
16013  #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
16014  #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
16015  #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
16016  #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
16017  #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
16018  #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
16019  #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
16020  #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
16021  #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
16022  #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
16023  #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
16024  #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
16025  #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
16026  #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
16027  #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
16028  #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
16029  #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
16030  #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
16031  #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
16032  #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
16033  #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
16034  
16035  /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
16036  #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
16037  #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
16038  #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
16039  #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
16040  #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
16041  #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
16042  #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
16043  #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
16044  #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
16045  #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
16046  #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
16047  #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
16048  #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
16049  #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
16050  #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
16051  #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
16052  #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
16053  #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
16054  #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
16055  #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
16056  #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
16057  #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
16058  #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
16059  #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
16060  #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
16061  #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
16062  #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
16063  #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
16064  #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
16065  #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
16066  #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
16067  #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
16068  #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
16069  
16070  /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
16071  
16072  #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
16073  #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16074  #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
16075  #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
16076  #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16077  #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
16078  #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
16079  #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
16080  #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
16081  /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
16082  #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
16083  #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16084  #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
16085  #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
16086  #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16087  #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
16088  #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
16089  #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
16090  #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
16091  #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
16092  #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
16093  #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
16094  #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
16095  #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
16096  
16097  /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
16098  #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
16099  #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
16100  #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
16101  
16102  /********************  Bit definition for USB_OTG_HCDMA register  ********************/
16103  #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
16104  #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
16105  #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
16106  
16107  /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
16108  #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
16109  #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
16110  #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
16111  
16112  /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
16113  #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
16114  #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
16115  #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
16116  #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
16117  #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
16118  #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
16119  
16120  /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
16121  
16122  #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
16123  #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
16124  #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
16125  #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
16126  #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
16127  #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
16128  #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
16129  #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
16130  #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
16131  #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
16132  #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
16133  #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
16134  #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
16135  #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
16136  #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
16137  #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
16138  #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
16139  #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
16140  #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
16141  #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
16142  #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
16143  #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
16144  #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
16145  #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
16146  #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
16147  #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
16148  #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
16149  #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
16150  #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
16151  #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
16152  #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
16153  #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
16154  #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
16155  #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
16156  #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
16157  #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
16158  #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
16159  #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
16160  
16161  /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
16162  #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
16163  #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
16164  #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
16165  #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
16166  #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
16167  #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
16168  #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
16169  #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
16170  #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
16171  #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
16172  #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
16173  #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
16174  #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
16175  #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
16176  #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
16177  #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
16178  #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
16179  #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
16180  #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
16181  #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
16182  #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
16183  #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
16184  #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
16185  #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
16186  #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
16187  #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
16188  #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
16189  #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
16190  #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
16191  #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
16192  #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
16193  #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
16194  #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
16195  /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
16196  
16197  #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
16198  #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16199  #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
16200  #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
16201  #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16202  #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
16203  
16204  #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
16205  #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
16206  #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
16207  #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
16208  #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
16209  
16210  /********************  Bit definition for PCGCCTL register  ********************/
16211  #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
16212  #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
16213  #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
16214  #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
16215  #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
16216  #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
16217  #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
16218  #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
16219  #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
16220  
16221  /* Legacy define */
16222  /********************  Bit definition for OTG register  ********************/
16223  #define USB_OTG_CHNUM_Pos                        (0U)
16224  #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
16225  #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
16226  #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
16227  #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
16228  #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
16229  #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
16230  #define USB_OTG_BCNT_Pos                         (4U)
16231  #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
16232  #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
16233  
16234  #define USB_OTG_DPID_Pos                         (15U)
16235  #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
16236  #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
16237  #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
16238  #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
16239  
16240  #define USB_OTG_PKTSTS_Pos                       (17U)
16241  #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
16242  #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
16243  #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
16244  #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
16245  #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
16246  #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
16247  
16248  #define USB_OTG_EPNUM_Pos                        (0U)
16249  #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
16250  #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
16251  #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
16252  #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
16253  #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
16254  #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
16255  
16256  #define USB_OTG_FRMNUM_Pos                       (21U)
16257  #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
16258  #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
16259  #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
16260  #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
16261  #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
16262  #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
16263  /**
16264    * @}
16265    */
16266  
16267  /**
16268    * @}
16269    */
16270  
16271  /** @addtogroup Exported_macros
16272    * @{
16273    */
16274  
16275  /******************************* ADC Instances ********************************/
16276  #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
16277                                         ((INSTANCE) == ADC2) || \
16278                                         ((INSTANCE) == ADC3))
16279  
16280  #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
16281  
16282  #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
16283  
16284  /******************************* CAN Instances ********************************/
16285  #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
16286                                         ((INSTANCE) == CAN2))
16287  /******************************* CRC Instances ********************************/
16288  #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
16289  
16290  /******************************* DAC Instances ********************************/
16291  #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
16292  
16293  /******************************* DCMI Instances *******************************/
16294  #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
16295  
16296  /******************************* DMA2D Instances *******************************/
16297  #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
16298  
16299  /******************************** DMA Instances *******************************/
16300  #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
16301                                                ((INSTANCE) == DMA1_Stream1) || \
16302                                                ((INSTANCE) == DMA1_Stream2) || \
16303                                                ((INSTANCE) == DMA1_Stream3) || \
16304                                                ((INSTANCE) == DMA1_Stream4) || \
16305                                                ((INSTANCE) == DMA1_Stream5) || \
16306                                                ((INSTANCE) == DMA1_Stream6) || \
16307                                                ((INSTANCE) == DMA1_Stream7) || \
16308                                                ((INSTANCE) == DMA2_Stream0) || \
16309                                                ((INSTANCE) == DMA2_Stream1) || \
16310                                                ((INSTANCE) == DMA2_Stream2) || \
16311                                                ((INSTANCE) == DMA2_Stream3) || \
16312                                                ((INSTANCE) == DMA2_Stream4) || \
16313                                                ((INSTANCE) == DMA2_Stream5) || \
16314                                                ((INSTANCE) == DMA2_Stream6) || \
16315                                                ((INSTANCE) == DMA2_Stream7))
16316  
16317  /******************************* GPIO Instances *******************************/
16318  #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
16319                                          ((INSTANCE) == GPIOB) || \
16320                                          ((INSTANCE) == GPIOC) || \
16321                                          ((INSTANCE) == GPIOD) || \
16322                                          ((INSTANCE) == GPIOE) || \
16323                                          ((INSTANCE) == GPIOF) || \
16324                                          ((INSTANCE) == GPIOG) || \
16325                                          ((INSTANCE) == GPIOH) || \
16326                                          ((INSTANCE) == GPIOI) || \
16327                                          ((INSTANCE) == GPIOJ) || \
16328                                          ((INSTANCE) == GPIOK))
16329  
16330  /******************************** I2C Instances *******************************/
16331  #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
16332                                         ((INSTANCE) == I2C2) || \
16333                                         ((INSTANCE) == I2C3))
16334  
16335  /******************************* SMBUS Instances ******************************/
16336  #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
16337  
16338  /******************************** I2S Instances *******************************/
16339  
16340  #define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
16341                                         ((INSTANCE) == SPI3))
16342  
16343  /*************************** I2S Extended Instances ***************************/
16344  #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
16345                                             ((INSTANCE) == I2S3ext))
16346  /* Legacy Defines */
16347  #define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE
16348  
16349  /******************************* RNG Instances ********************************/
16350  #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
16351  
16352  /****************************** RTC Instances *********************************/
16353  #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
16354  
16355  /******************************* SAI Instances ********************************/
16356  #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
16357                                       ((PERIPH) == SAI1_Block_B))
16358  /* Legacy define */
16359  
16360  #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
16361  
16362  /******************************** SPI Instances *******************************/
16363  #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)  || \
16364                                         ((INSTANCE) == SPI2)  || \
16365                                         ((INSTANCE) == SPI3)  || \
16366                                         ((INSTANCE) == SPI4)  || \
16367                                         ((INSTANCE) == SPI5)  || \
16368                                         ((INSTANCE) == SPI6))
16369  
16370  
16371  /****************** TIM Instances : All supported instances *******************/
16372  #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
16373                                      ((INSTANCE) == TIM2) || \
16374                                      ((INSTANCE) == TIM3) || \
16375                                      ((INSTANCE) == TIM4) || \
16376                                      ((INSTANCE) == TIM5) || \
16377                                      ((INSTANCE) == TIM6) || \
16378                                      ((INSTANCE) == TIM7) || \
16379                                      ((INSTANCE) == TIM8) || \
16380                                      ((INSTANCE) == TIM9) || \
16381                                      ((INSTANCE) == TIM10)|| \
16382                                      ((INSTANCE) == TIM11)|| \
16383                                      ((INSTANCE) == TIM12)|| \
16384                                      ((INSTANCE) == TIM13)|| \
16385                                      ((INSTANCE) == TIM14))
16386  
16387  /************* TIM Instances : at least 1 capture/compare channel *************/
16388  #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
16389                                           ((INSTANCE) == TIM2)  || \
16390                                           ((INSTANCE) == TIM3)  || \
16391                                           ((INSTANCE) == TIM4)  || \
16392                                           ((INSTANCE) == TIM5)  || \
16393                                           ((INSTANCE) == TIM8)  || \
16394                                           ((INSTANCE) == TIM9)  || \
16395                                           ((INSTANCE) == TIM10) || \
16396                                           ((INSTANCE) == TIM11) || \
16397                                           ((INSTANCE) == TIM12) || \
16398                                           ((INSTANCE) == TIM13) || \
16399                                           ((INSTANCE) == TIM14))
16400  
16401  /************ TIM Instances : at least 2 capture/compare channels *************/
16402  #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16403                                         ((INSTANCE) == TIM2) || \
16404                                         ((INSTANCE) == TIM3) || \
16405                                         ((INSTANCE) == TIM4) || \
16406                                         ((INSTANCE) == TIM5) || \
16407                                         ((INSTANCE) == TIM8) || \
16408                                         ((INSTANCE) == TIM9) || \
16409                                         ((INSTANCE) == TIM12))
16410  
16411  /************ TIM Instances : at least 3 capture/compare channels *************/
16412  #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
16413                                           ((INSTANCE) == TIM2) || \
16414                                           ((INSTANCE) == TIM3) || \
16415                                           ((INSTANCE) == TIM4) || \
16416                                           ((INSTANCE) == TIM5) || \
16417                                           ((INSTANCE) == TIM8))
16418  
16419  /************ TIM Instances : at least 4 capture/compare channels *************/
16420  #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16421                                         ((INSTANCE) == TIM2) || \
16422                                         ((INSTANCE) == TIM3) || \
16423                                         ((INSTANCE) == TIM4) || \
16424                                         ((INSTANCE) == TIM5) || \
16425                                         ((INSTANCE) == TIM8))
16426  
16427  /******************** TIM Instances : Advanced-control timers *****************/
16428  #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16429                                             ((INSTANCE) == TIM8))
16430  
16431  /******************* TIM Instances : Timer input XOR function *****************/
16432  #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
16433                                           ((INSTANCE) == TIM2) || \
16434                                           ((INSTANCE) == TIM3) || \
16435                                           ((INSTANCE) == TIM4) || \
16436                                           ((INSTANCE) == TIM5) || \
16437                                           ((INSTANCE) == TIM8))
16438  
16439  /****************** TIM Instances : DMA requests generation (UDE) *************/
16440  #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16441                                         ((INSTANCE) == TIM2) || \
16442                                         ((INSTANCE) == TIM3) || \
16443                                         ((INSTANCE) == TIM4) || \
16444                                         ((INSTANCE) == TIM5) || \
16445                                         ((INSTANCE) == TIM6) || \
16446                                         ((INSTANCE) == TIM7) || \
16447                                         ((INSTANCE) == TIM8))
16448  
16449  /************ TIM Instances : DMA requests generation (CCxDE) *****************/
16450  #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16451                                            ((INSTANCE) == TIM2) || \
16452                                            ((INSTANCE) == TIM3) || \
16453                                            ((INSTANCE) == TIM4) || \
16454                                            ((INSTANCE) == TIM5) || \
16455                                            ((INSTANCE) == TIM8))
16456  
16457  /************ TIM Instances : DMA requests generation (COMDE) *****************/
16458  #define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
16459                                            ((INSTANCE) == TIM2) || \
16460                                            ((INSTANCE) == TIM3) || \
16461                                            ((INSTANCE) == TIM4) || \
16462                                            ((INSTANCE) == TIM5) || \
16463                                            ((INSTANCE) == TIM8))
16464  
16465  /******************** TIM Instances : DMA burst feature ***********************/
16466  #define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
16467                                               ((INSTANCE) == TIM2) || \
16468                                               ((INSTANCE) == TIM3) || \
16469                                               ((INSTANCE) == TIM4) || \
16470                                               ((INSTANCE) == TIM5) || \
16471                                               ((INSTANCE) == TIM8))
16472  
16473  /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
16474  #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
16475                                            ((INSTANCE) == TIM2)  || \
16476                                            ((INSTANCE) == TIM3)  || \
16477                                            ((INSTANCE) == TIM4)  || \
16478                                            ((INSTANCE) == TIM5)  || \
16479                                            ((INSTANCE) == TIM6)  || \
16480                                            ((INSTANCE) == TIM7)  || \
16481                                            ((INSTANCE) == TIM8))
16482  
16483  /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
16484  #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16485                                           ((INSTANCE) == TIM2) || \
16486                                           ((INSTANCE) == TIM3) || \
16487                                           ((INSTANCE) == TIM4) || \
16488                                           ((INSTANCE) == TIM5) || \
16489                                           ((INSTANCE) == TIM8) || \
16490                                           ((INSTANCE) == TIM9) || \
16491                                           ((INSTANCE) == TIM12))
16492  /********************** TIM Instances : 32 bit Counter ************************/
16493  #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
16494                                                ((INSTANCE) == TIM5))
16495  
16496  /***************** TIM Instances : external trigger input availabe ************/
16497  #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
16498                                          ((INSTANCE) == TIM2) || \
16499                                          ((INSTANCE) == TIM3) || \
16500                                          ((INSTANCE) == TIM4) || \
16501                                          ((INSTANCE) == TIM5) || \
16502                                          ((INSTANCE) == TIM8))
16503  
16504  /****************** TIM Instances : remapping capability **********************/
16505  #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
16506                                           ((INSTANCE) == TIM5)  || \
16507                                           ((INSTANCE) == TIM11))
16508  
16509  /******************* TIM Instances : output(s) available **********************/
16510  #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
16511      ((((INSTANCE) == TIM1) &&                  \
16512       (((CHANNEL) == TIM_CHANNEL_1) ||          \
16513        ((CHANNEL) == TIM_CHANNEL_2) ||          \
16514        ((CHANNEL) == TIM_CHANNEL_3) ||          \
16515        ((CHANNEL) == TIM_CHANNEL_4)))           \
16516      ||                                         \
16517      (((INSTANCE) == TIM2) &&                   \
16518       (((CHANNEL) == TIM_CHANNEL_1) ||          \
16519        ((CHANNEL) == TIM_CHANNEL_2) ||          \
16520        ((CHANNEL) == TIM_CHANNEL_3) ||          \
16521        ((CHANNEL) == TIM_CHANNEL_4)))           \
16522      ||                                         \
16523      (((INSTANCE) == TIM3) &&                   \
16524       (((CHANNEL) == TIM_CHANNEL_1) ||          \
16525        ((CHANNEL) == TIM_CHANNEL_2) ||          \
16526        ((CHANNEL) == TIM_CHANNEL_3) ||          \
16527        ((CHANNEL) == TIM_CHANNEL_4)))           \
16528      ||                                         \
16529      (((INSTANCE) == TIM4) &&                   \
16530       (((CHANNEL) == TIM_CHANNEL_1) ||          \
16531        ((CHANNEL) == TIM_CHANNEL_2) ||          \
16532        ((CHANNEL) == TIM_CHANNEL_3) ||          \
16533        ((CHANNEL) == TIM_CHANNEL_4)))           \
16534      ||                                         \
16535      (((INSTANCE) == TIM5) &&                   \
16536       (((CHANNEL) == TIM_CHANNEL_1) ||          \
16537        ((CHANNEL) == TIM_CHANNEL_2) ||          \
16538        ((CHANNEL) == TIM_CHANNEL_3) ||          \
16539        ((CHANNEL) == TIM_CHANNEL_4)))           \
16540      ||                                         \
16541      (((INSTANCE) == TIM8) &&                   \
16542       (((CHANNEL) == TIM_CHANNEL_1) ||          \
16543        ((CHANNEL) == TIM_CHANNEL_2) ||          \
16544        ((CHANNEL) == TIM_CHANNEL_3) ||          \
16545        ((CHANNEL) == TIM_CHANNEL_4)))           \
16546      ||                                         \
16547      (((INSTANCE) == TIM9) &&                   \
16548       (((CHANNEL) == TIM_CHANNEL_1) ||          \
16549        ((CHANNEL) == TIM_CHANNEL_2)))           \
16550      ||                                         \
16551      (((INSTANCE) == TIM10) &&                  \
16552       (((CHANNEL) == TIM_CHANNEL_1)))           \
16553      ||                                         \
16554      (((INSTANCE) == TIM11) &&                  \
16555       (((CHANNEL) == TIM_CHANNEL_1)))           \
16556      ||                                         \
16557      (((INSTANCE) == TIM12) &&                  \
16558       (((CHANNEL) == TIM_CHANNEL_1) ||          \
16559        ((CHANNEL) == TIM_CHANNEL_2)))           \
16560      ||                                         \
16561      (((INSTANCE) == TIM13) &&                  \
16562       (((CHANNEL) == TIM_CHANNEL_1)))           \
16563      ||                                         \
16564      (((INSTANCE) == TIM14) &&                  \
16565       (((CHANNEL) == TIM_CHANNEL_1))))
16566  
16567  /************ TIM Instances : complementary output(s) available ***************/
16568  #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
16569     ((((INSTANCE) == TIM1) &&                    \
16570       (((CHANNEL) == TIM_CHANNEL_1) ||           \
16571        ((CHANNEL) == TIM_CHANNEL_2) ||           \
16572        ((CHANNEL) == TIM_CHANNEL_3)))            \
16573      ||                                          \
16574      (((INSTANCE) == TIM8) &&                    \
16575       (((CHANNEL) == TIM_CHANNEL_1) ||           \
16576        ((CHANNEL) == TIM_CHANNEL_2) ||           \
16577        ((CHANNEL) == TIM_CHANNEL_3))))
16578  
16579  /****************** TIM Instances : supporting counting mode selection ********/
16580  #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
16581                                                          ((INSTANCE) == TIM2) || \
16582                                                          ((INSTANCE) == TIM3) || \
16583                                                          ((INSTANCE) == TIM4) || \
16584                                                          ((INSTANCE) == TIM5) || \
16585                                                          ((INSTANCE) == TIM8))
16586  
16587  /****************** TIM Instances : supporting clock division *****************/
16588  #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
16589                                                    ((INSTANCE) == TIM2) || \
16590                                                    ((INSTANCE) == TIM3) || \
16591                                                    ((INSTANCE) == TIM4) || \
16592                                                    ((INSTANCE) == TIM5) || \
16593                                                    ((INSTANCE) == TIM8) || \
16594                                                    ((INSTANCE) == TIM9) || \
16595                                                    ((INSTANCE) == TIM10)|| \
16596                                                    ((INSTANCE) == TIM11)|| \
16597                                                    ((INSTANCE) == TIM12)|| \
16598                                                    ((INSTANCE) == TIM13)|| \
16599                                                    ((INSTANCE) == TIM14))
16600  
16601  /****************** TIM Instances : supporting commutation event generation ***/
16602  #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
16603                                                       ((INSTANCE) == TIM8))
16604  
16605  
16606  /****************** TIM Instances : supporting OCxREF clear *******************/
16607  #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
16608                                                         ((INSTANCE) == TIM2) || \
16609                                                         ((INSTANCE) == TIM3) || \
16610                                                         ((INSTANCE) == TIM4) || \
16611                                                         ((INSTANCE) == TIM5) || \
16612                                                         ((INSTANCE) == TIM8))
16613  
16614  /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
16615  #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16616                                                          ((INSTANCE) == TIM2) || \
16617                                                          ((INSTANCE) == TIM3) || \
16618                                                          ((INSTANCE) == TIM4) || \
16619                                                          ((INSTANCE) == TIM5) || \
16620                                                          ((INSTANCE) == TIM8) || \
16621                                                          ((INSTANCE) == TIM9) || \
16622                                                          ((INSTANCE) == TIM12))
16623  
16624  /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
16625  #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16626                                                          ((INSTANCE) == TIM2) || \
16627                                                          ((INSTANCE) == TIM3) || \
16628                                                          ((INSTANCE) == TIM4) || \
16629                                                          ((INSTANCE) == TIM5) || \
16630                                                          ((INSTANCE) == TIM8))
16631  
16632  /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
16633  #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
16634                                                          ((INSTANCE) == TIM2) || \
16635                                                          ((INSTANCE) == TIM3) || \
16636                                                          ((INSTANCE) == TIM4) || \
16637                                                          ((INSTANCE) == TIM5) || \
16638                                                          ((INSTANCE) == TIM8) || \
16639                                                          ((INSTANCE) == TIM9) || \
16640                                                          ((INSTANCE) == TIM12))
16641  
16642  /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
16643  #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
16644                                                          ((INSTANCE) == TIM2) || \
16645                                                          ((INSTANCE) == TIM3) || \
16646                                                          ((INSTANCE) == TIM4) || \
16647                                                          ((INSTANCE) == TIM5) || \
16648                                                          ((INSTANCE) == TIM8) || \
16649                                                          ((INSTANCE) == TIM9) || \
16650                                                          ((INSTANCE) == TIM12))
16651  
16652  /****************** TIM Instances : supporting repetition counter *************/
16653  #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
16654                                                         ((INSTANCE) == TIM8))
16655  
16656  /****************** TIM Instances : supporting encoder interface **************/
16657  #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
16658                                                        ((INSTANCE) == TIM2) || \
16659                                                        ((INSTANCE) == TIM3) || \
16660                                                        ((INSTANCE) == TIM4) || \
16661                                                        ((INSTANCE) == TIM5) || \
16662                                                        ((INSTANCE) == TIM8) || \
16663                                                        ((INSTANCE) == TIM9) || \
16664                                                        ((INSTANCE) == TIM12))
16665  /****************** TIM Instances : supporting Hall sensor interface **********/
16666  #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
16667                                                            ((INSTANCE) == TIM2) || \
16668                                                            ((INSTANCE) == TIM3) || \
16669                                                            ((INSTANCE) == TIM4) || \
16670                                                            ((INSTANCE) == TIM5) || \
16671                                                            ((INSTANCE) == TIM8))
16672  /****************** TIM Instances : supporting the break function *************/
16673  #define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
16674                                            ((INSTANCE) == TIM8))
16675  
16676  /******************** USART Instances : Synchronous mode **********************/
16677  #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16678                                       ((INSTANCE) == USART2) || \
16679                                       ((INSTANCE) == USART3) || \
16680                                       ((INSTANCE) == USART6))
16681  
16682  /******************** UART Instances : Half-Duplex mode **********************/
16683  #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16684                                                 ((INSTANCE) == USART2) || \
16685                                                 ((INSTANCE) == USART3) || \
16686                                                 ((INSTANCE) == UART4)  || \
16687                                                 ((INSTANCE) == UART5)  || \
16688                                                 ((INSTANCE) == USART6) || \
16689                                                 ((INSTANCE) == UART7)  || \
16690                                                 ((INSTANCE) == UART8))
16691  
16692  /* Legacy defines */
16693  #define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
16694  
16695  /****************** UART Instances : Hardware Flow control ********************/
16696  #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16697                                             ((INSTANCE) == USART2) || \
16698                                             ((INSTANCE) == USART3) || \
16699                                             ((INSTANCE) == USART6))
16700  /******************** UART Instances : LIN mode **********************/
16701  #define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
16702  
16703  /********************* UART Instances : Smart card mode ***********************/
16704  #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16705                                           ((INSTANCE) == USART2) || \
16706                                           ((INSTANCE) == USART3) || \
16707                                           ((INSTANCE) == USART6))
16708  
16709  /*********************** UART Instances : IRDA mode ***************************/
16710  #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16711                                      ((INSTANCE) == USART2) || \
16712                                      ((INSTANCE) == USART3) || \
16713                                      ((INSTANCE) == UART4)  || \
16714                                      ((INSTANCE) == UART5)  || \
16715                                      ((INSTANCE) == USART6) || \
16716                                      ((INSTANCE) == UART7)  || \
16717                                      ((INSTANCE) == UART8))
16718  
16719  /*********************** PCD Instances ****************************************/
16720  #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
16721                                         ((INSTANCE) == USB_OTG_HS))
16722  
16723  /*********************** HCD Instances ****************************************/
16724  #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
16725                                         ((INSTANCE) == USB_OTG_HS))
16726  
16727  /****************************** SDIO Instances ********************************/
16728  #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
16729  
16730  /****************************** IWDG Instances ********************************/
16731  #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
16732  
16733  /****************************** WWDG Instances ********************************/
16734  #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
16735  
16736  /****************************** USB Exported Constants ************************/
16737  #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
16738  #define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
16739  #define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
16740  #define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
16741  
16742  /*
16743   * @brief Specific devices reset values definitions
16744   */
16745  #define RCC_PLLCFGR_RST_VALUE              0x24003010U
16746  #define RCC_PLLI2SCFGR_RST_VALUE           0x24003000U
16747  #define RCC_PLLSAICFGR_RST_VALUE           0x24003000U
16748  
16749  #define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/
16750  #define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
16751  #define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
16752  #define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */
16753  #define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
16754  #define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
16755  #define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
16756  #define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
16757  
16758  #define RCC_PLLN_MIN_VALUE                 50U
16759  #define RCC_PLLN_MAX_VALUE                432U
16760  
16761  #define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
16762  #define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
16763  #define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
16764  #define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
16765  #define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
16766  
16767  #define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
16768  #define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
16769  #define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
16770  #define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
16771  #define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */
16772  
16773  #define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
16774  #define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
16775  #define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
16776  
16777  #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
16778  #define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
16779  #define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
16780  #define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
16781  /******************************************************************************/
16782  /*  For a painless codes migration between the STM32F4xx device product       */
16783  /*  lines, the aliases defined below are put in place to overcome the         */
16784  /*  differences in the interrupt handlers and IRQn definitions.               */
16785  /*  No need to update developed interrupt code when moving across             */
16786  /*  product lines within the same STM32F4 Family                              */
16787  /******************************************************************************/
16788  /* Aliases for __IRQn */
16789  #define FSMC_IRQn              FMC_IRQn
16790  
16791  /* Aliases for __IRQHandler */
16792  #define FSMC_IRQHandler        FMC_IRQHandler
16793  
16794  /**
16795    * @}
16796    */
16797  
16798  /**
16799    * @}
16800    */
16801  
16802  /**
16803    * @}
16804    */
16805  
16806  #ifdef __cplusplus
16807  }
16808  #endif /* __cplusplus */
16809  
16810  #endif /* __STM32F427xx_H */
16811  
16812  
16813  
16814  /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
16815