1 /* 2 * Copyright (c) 2017-2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_hcp_g11_X.h 24 //! \brief Defines functions for constructing Vdbox HCP commands on Gen11-based platforms 25 //! 26 27 #ifndef __MHW_VDBOX_HCP_G11_X_H__ 28 #define __MHW_VDBOX_HCP_G11_X_H__ 29 30 #include "mhw_vdbox_hcp_generic.h" 31 #include "mhw_vdbox_hcp_hwcmd_g11_X.h" 32 #include "mhw_vdbox_g11_X.h" 33 #include "mos_util_user_interface.h" 34 35 #define MHW_HCP_WORST_CASE_LCU_CU_TU_INFO (26 * MHW_CACHELINE_SIZE) // 18+4+4 36 #define MHW_HCP_WORST_CASE_LCU_CU_TU_INFO_REXT (35 * MHW_CACHELINE_SIZE) // 27+4+4 37 38 #define MHW_HCP_WORST_CASE_CU_TU_INFO (4 * MHW_CACHELINE_SIZE) // 2+1+1 39 #define MHW_HCP_WORST_CASE_CU_TU_INFO_REXT (6 * MHW_CACHELINE_SIZE) // 4+1+1 40 41 42 // ICL rowstore Cache values 43 #define MHW_VDBOX_PICWIDTH_1920 1920 44 #define MHW_VDBOX_PICWIDTH_3840 3840 45 #define VP9DATROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_1920 30 46 #define VP9DATROWSTORE_BASEADDRESS_PICWIDTH_BETWEEN_1920_AND_3840 60 47 #define VP9DFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_1920 30 48 #define HEVCDFROWSTORE_BASEADDRESS_NON444_PICWIDTH_LESS_THAN_OR_EQU_TO_1920 120 49 #define HEVCSAOROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_1920 360 50 #define HEVCSAOROWSTORE_BASEADDRESS_444_10BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_1920 120 51 52 // CU Record structure 53 struct EncodeHevcCuDataG11 54 { 55 //DWORD 0 56 union 57 { 58 struct 59 { 60 uint32_t DW0_L0_Mv0x : MOS_BITFIELD_RANGE(0, 15); 61 uint32_t DW0_L0_Mv0y : MOS_BITFIELD_RANGE(16, 31); 62 }; 63 struct 64 { 65 uint32_t DW0_LumaIntraModeSecondBest : MOS_BITFIELD_RANGE(0, 5); 66 uint32_t DW0_LumaIntraModeSecondBest4x4_1 : MOS_BITFIELD_RANGE(6, 11); 67 uint32_t DW0_LumaIntraModeSecondBest4x4_2 : MOS_BITFIELD_RANGE(12, 17); 68 uint32_t DW0_LumaIntraModeSecondBest4x4_3 : MOS_BITFIELD_RANGE(18, 23); 69 uint32_t DW0_ChromaIntraModeSecondBest_o3a_p : MOS_BITFIELD_RANGE(24, 26); 70 uint32_t DW0_Reserved0 : MOS_BITFIELD_RANGE(27, 31); 71 }; 72 }; 73 74 //DWORD 1 75 uint32_t DW1_L0_Mv1x : MOS_BITFIELD_RANGE(0, 15); 76 uint32_t DW1_L0_Mv1y : MOS_BITFIELD_RANGE(16, 31); 77 78 //DWORD 2 79 uint32_t DW2_L1_Mv0x : MOS_BITFIELD_RANGE(0, 15); 80 uint32_t DW2_L1_Mv0y : MOS_BITFIELD_RANGE(16, 31); 81 82 //DWORD 3 83 uint32_t DW3_L1_Mv1x : MOS_BITFIELD_RANGE(0, 15); 84 uint32_t DW3_L1_Mv1y : MOS_BITFIELD_RANGE(16, 31); 85 86 //DWORD 4 87 uint32_t DW4_L0Mv0RefIdx : MOS_BITFIELD_RANGE(0, 3); 88 uint32_t DW4_L0Mv1RefIdx_ChromaIntraMode : MOS_BITFIELD_RANGE(4, 7); 89 uint32_t DW4_L1Mv0RefIdx_ChromaIntraMode2 : MOS_BITFIELD_RANGE(8, 11); 90 uint32_t DW4_L1Mv1RefIdx_ChromaIntraMode1 : MOS_BITFIELD_RANGE(12, 15); 91 uint32_t DW4_Tu_Yuv_TransformSkip : MOS_BITFIELD_RANGE(16, 31); 92 93 //DWORD 5 94 uint32_t DW5_TuSize : MOS_BITFIELD_RANGE(0, 31); 95 96 //DWORD 6 97 uint32_t DW6_LumaIntraMode4x4_1 : MOS_BITFIELD_RANGE(0, 5); 98 uint32_t DW6_LumaIntraMode4x4_2 : MOS_BITFIELD_RANGE(6, 11); 99 uint32_t DW6_LumaIntraMode4x4_3 : MOS_BITFIELD_RANGE(12, 17); 100 uint32_t DW6_RoundingSelect : MOS_BITFIELD_RANGE(18, 21); 101 uint32_t DW6_Reserved0 : MOS_BITFIELD_RANGE(22, 23); 102 uint32_t DW6_TuCountMinus1 : MOS_BITFIELD_RANGE(24, 27); 103 uint32_t DW6_Reserved1 : MOS_BITFIELD_RANGE(28, 31); 104 105 //DWORD 7 106 uint32_t DW7_LumaIntraMode : MOS_BITFIELD_RANGE(0, 5); 107 uint32_t DW7_CuSize : MOS_BITFIELD_RANGE(6, 7); 108 uint32_t DW7_ChromaIntraMode : MOS_BITFIELD_RANGE(8, 10); 109 uint32_t DW7_CuTransquantBypassFlag : MOS_BITFIELD_BIT(11); 110 uint32_t DW7_CuPartMode : MOS_BITFIELD_RANGE(12, 14); 111 uint32_t DW7_CuPredMode : MOS_BITFIELD_BIT(15); 112 uint32_t DW7_InterPredIdcMv0 : MOS_BITFIELD_RANGE(16, 17); 113 uint32_t DW7_InterPredIdcMv1 : MOS_BITFIELD_RANGE(18, 19); 114 uint32_t DW7_ModifiedFlag : MOS_BITFIELD_BIT(20); 115 uint32_t DW7_ForceZeroCoeff : MOS_BITFIELD_BIT(21); 116 uint32_t DW7_Reserved0 : MOS_BITFIELD_RANGE(22, 23); 117 uint32_t DW7_CuQp : MOS_BITFIELD_RANGE(24, 30); 118 uint32_t DW7_CuQpSign : MOS_BITFIELD_BIT(31); 119 120 }; 121 122 struct MHW_VDBOX_HEVC_PIC_STATE_G11 : public MHW_VDBOX_HEVC_PIC_STATE 123 { 124 PCODEC_HEVC_EXT_PIC_PARAMS pHevcExtPicParams = nullptr; 125 }; 126 using PMHW_VDBOX_HEVC_PIC_STATE_G11 = MHW_VDBOX_HEVC_PIC_STATE_G11 *; 127 128 129 struct MHW_VDBOX_HEVC_SLICE_STATE_G11 : public MHW_VDBOX_HEVC_SLICE_STATE 130 { 131 // GEN11+ Tile coding params 132 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 pTileCodingParams = nullptr; 133 uint32_t dwTileID = 0; 134 uint32_t dwNumPipe = 0; 135 136 PCODEC_HEVC_EXT_SLICE_PARAMS pHevcExtSliceParams = nullptr; 137 PCODEC_HEVC_EXT_PIC_PARAMS pHevcExtPicParam = nullptr; 138 }; 139 using PMHW_VDBOX_HEVC_SLICE_STATE_G11 = MHW_VDBOX_HEVC_SLICE_STATE_G11 *; 140 141 struct MHW_VDBOX_PIPE_BUF_ADDR_PARAMS_G11 : public MHW_VDBOX_PIPE_BUF_ADDR_PARAMS 142 { 143 //Scalable 144 PMOS_RESOURCE presSliceStateStreamOutBuffer = nullptr; 145 PMOS_RESOURCE presMvUpRightColStoreBuffer = nullptr; 146 PMOS_RESOURCE presIntraPredUpRightColStoreBuffer = nullptr; 147 PMOS_RESOURCE presIntraPredLeftReconColStoreBuffer = nullptr; 148 PMOS_RESOURCE presCABACSyntaxStreamOutBuffer = nullptr; 149 PMOS_RESOURCE presCABACSyntaxStreamOutMaxAddr = nullptr; 150 }; 151 using PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS_G11 = MHW_VDBOX_PIPE_BUF_ADDR_PARAMS_G11 *; 152 153 // the tile size record is streamed out serving 2 purposes 154 // in vp9 for back annotation of tile size into the bitstream 155 struct HCPPakHWTileSizeRecord_G11 156 { 157 //DW0 158 uint32_t 159 Address_31_0; 160 161 //DW1 162 uint32_t 163 Address_63_32; 164 165 //DW2 166 uint32_t 167 Length; // Bitstream length per tile; includes header len in first tile, and tail len in last tile 168 169 //DW3 170 uint32_t 171 TileSize; // In Vp9, it is used for back annotation, In Hevc, it is the mmio register bytecountNoHeader 172 173 //DW4 174 uint32_t 175 AddressOffset; // Cacheline offset 176 177 //DW5 178 uint32_t 179 ByteOffset : 6, //[5:0] // Byte offset within cacheline 180 Res_95_70 : 26; //[31:6] 181 182 //DW6 183 uint32_t 184 Hcp_Bs_SE_Bitcount_Tile; // bitstream size for syntax element per tile 185 186 //DW7 187 uint32_t 188 Hcp_Cabac_BinCnt_Tile; // bitstream size for syntax element per tile 189 190 //DW8 191 uint32_t 192 Res_DW8_31_0; 193 194 //DW9 195 uint32_t 196 Hcp_Image_Status_Ctrl; // image status control per tile 197 198 //DW10 199 uint32_t 200 Hcp_Qp_Status_Count; // Qp status count per tile 201 202 //DW11 203 uint32_t 204 Hcp_Slice_Count_Tile; // number of slices per tile 205 206 //DW12-15 207 uint32_t 208 Res_DW12_DW15[4]; // reserved bits added so that QwordDisables are set correctly 209 }; 210 211 //! MHW Vdbox Hcp interface for Gen11 212 /*! 213 This class defines the Hcp command construction functions for Gen11 platform 214 */ 215 class MhwVdboxHcpInterfaceG11 : public MhwVdboxHcpInterfaceGeneric<mhw_vdbox_hcp_g11_X> 216 { 217 protected: 218 #define PATCH_LIST_COMMAND(x) (x##_NUMBER_OF_ADDRESSES) 219 220 enum CommandsNumberOfAddresses 221 { 222 MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 223 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 224 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 225 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 226 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 227 MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 4, // 4 DW for 2 address fields 228 MI_SEMAPHORE_WAIT_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address fields 229 MI_ATOMIC_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 230 231 MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 232 233 HCP_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 234 HCP_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 235 HCP_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 45, // 45 address fields 236 HCP_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 11, // 22 DW for 11 address field 237 HCP_QM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 238 HCP_FQM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 239 HCP_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 240 HCP_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 241 HCP_WEIGHTOFFSET_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 242 HCP_SLICE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 243 HCP_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 244 HCP_TILE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 245 HCP_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 246 HCP_VP9_SEGMENT_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 247 HCP_VP9_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 248 HCP_TILE_CODING_COMMAND_NUMBER_OF_ADDRESSES = 1, // 0 DW for address fields 249 250 VDENC_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 12, // 12 DW for 12 address fields 251 VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields 252 }; 253 254 bool m_hevcRDOQPerfDisabled = false; //!< Flag to indicate if HEVC RDOQ Perf is disabled 255 uint32_t m_watchDogTimerThreshold = 0; //!< For Watch Dog Timer threshold on Gen11+ 256 257 static const uint32_t m_hcpPakObjSize = (5 + 3); //!< hcp pak object size 258 259 static const uint32_t m_veboxRgbHistogramSizePerSlice = 256 * 4; 260 static const uint32_t m_veboxNumRgbChannel = 3; 261 static const uint32_t m_veboxAceHistogramSizePerFramePerSlice = 256 * 4; 262 static const uint32_t m_veboxNumFramePreviousCurrent = 2; 263 264 static const uint32_t m_veboxMaxSlices = 4; 265 static const uint32_t m_veboxRgbHistogramSize = m_veboxRgbHistogramSizePerSlice * m_veboxNumRgbChannel * m_veboxMaxSlices; 266 static const uint32_t m_veboxRgbAceHistogramSizeReserved = 3072 * 4; 267 static const uint32_t m_veboxLaceHistogram256BinPerBlock = 256 * 2; 268 static const uint32_t m_veboxStatisticsSize = 32 * 8; 269 270 public: 271 static const uint32_t m_watchDogEnableCounter = 0x0; 272 static const uint32_t m_watchDogDisableCounter = 0x00000001; 273 static const uint32_t m_watchDogTimeoutInMs = 120; // derived from WDT threshold in KMD 274 275 //! 276 //! \brief Constructor 277 //! MhwVdboxHcpInterfaceG11(PMOS_INTERFACE osInterface,MhwMiInterface * miInterface,MhwCpInterface * cpInterface,bool decodeInUse)278 MhwVdboxHcpInterfaceG11( 279 PMOS_INTERFACE osInterface, 280 MhwMiInterface *miInterface, 281 MhwCpInterface *cpInterface, 282 bool decodeInUse) 283 : MhwVdboxHcpInterfaceGeneric(osInterface, miInterface, cpInterface, decodeInUse) 284 { 285 MHW_FUNCTION_ENTER; 286 287 m_rhoDomainStatsEnabled = true; 288 289 // Debug hook for HEVC RDOQ issue on Gen11 290 MOS_USER_FEATURE_VALUE_DATA userFeatureData; 291 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); 292 #if (_DEBUG || _RELEASE_INTERNAL) 293 MOS_UserFeature_ReadValue_ID( 294 nullptr, 295 __MEDIA_USER_FEATURE_VALUE_HEVC_ENCODE_RDOQ_PERF_DISABLE_ID, 296 &userFeatureData, 297 this->m_osInterface->pOsContext); 298 #endif // _DEBUG || _RELEASE_INTERNAL 299 m_hevcRDOQPerfDisabled = userFeatureData.i32Data ? true : false; 300 301 m_watchDogTimerThreshold = m_watchDogTimeoutInMs; 302 #if (_DEBUG || _RELEASE_INTERNAL) 303 // User feature config of watchdog timer threshold 304 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); 305 MOS_UserFeature_ReadValue_ID( 306 nullptr, 307 __MEDIA_USER_FEATURE_VALUE_WATCHDOG_TIMER_THRESHOLD, 308 &userFeatureData, 309 this->m_osInterface->pOsContext); 310 if (userFeatureData.u32Data != 0) 311 { 312 m_watchDogTimerThreshold = userFeatureData.u32Data; 313 } 314 #endif 315 316 m_hevcEncCuRecordSize = sizeof(EncodeHevcCuDataG11); 317 m_pakHWTileSizeRecordSize = sizeof(HCPPakHWTileSizeRecord_G11); 318 319 InitRowstoreUserFeatureSettings(); 320 InitMmioRegisters(); 321 } 322 323 //! 324 //! \brief Destructor 325 //! ~MhwVdboxHcpInterfaceG11()326 virtual ~MhwVdboxHcpInterfaceG11() { MHW_FUNCTION_ENTER; } 327 GetHcpPakObjSize()328 uint32_t GetHcpPakObjSize() 329 { 330 return m_hcpPakObjSize; 331 } 332 GetHcpHevcVp9RdoqStateCommandSize()333 inline uint32_t GetHcpHevcVp9RdoqStateCommandSize() 334 { 335 return mhw_vdbox_hcp_g11_X::HEVC_VP9_RDOQ_STATE_CMD::byteSize; 336 } 337 GetHcpVp9PicStateCommandSize()338 inline uint32_t GetHcpVp9PicStateCommandSize() 339 { 340 return mhw_vdbox_hcp_g11_X::HCP_VP9_PIC_STATE_CMD::byteSize; 341 } 342 GetHcpVp9SegmentStateCommandSize()343 inline uint32_t GetHcpVp9SegmentStateCommandSize() 344 { 345 return mhw_vdbox_hcp_g11_X::HCP_VP9_SEGMENT_STATE_CMD::byteSize; 346 } 347 GetWatchDogTimerThrehold()348 inline uint32_t GetWatchDogTimerThrehold() 349 { 350 return m_watchDogTimerThreshold; 351 } 352 353 void InitMmioRegisters(); 354 355 void InitRowstoreUserFeatureSettings(); 356 357 MOS_STATUS GetHcpStateCommandSize( 358 uint32_t mode, 359 uint32_t *commandsSize, 360 uint32_t *patchListSize, 361 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params); 362 363 MOS_STATUS GetHcpPrimitiveCommandSize( 364 uint32_t mode, 365 uint32_t *commandsSize, 366 uint32_t *patchListSize, 367 bool modeSpecific); 368 369 MOS_STATUS GetRowstoreCachingAddrs( 370 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams); 371 372 MOS_STATUS GetHevcBufferSize( 373 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType, 374 PMHW_VDBOX_HCP_BUFFER_SIZE_PARAMS hcpBufSizeParam); 375 376 MOS_STATUS GetVp9BufferSize( 377 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType, 378 PMHW_VDBOX_HCP_BUFFER_SIZE_PARAMS hcpBufSizeParam); 379 380 MOS_STATUS IsHevcBufferReallocNeeded( 381 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType, 382 PMHW_VDBOX_HCP_BUFFER_REALLOC_PARAMS reallocParam); 383 384 MOS_STATUS IsVp9BufferReallocNeeded( 385 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType, 386 PMHW_VDBOX_HCP_BUFFER_REALLOC_PARAMS reallocParam); 387 388 MOS_STATUS AddHcpPipeModeSelectCmd( 389 PMOS_COMMAND_BUFFER cmdBuffer, 390 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS params); 391 392 MOS_STATUS AddHcpDecodeSurfaceStateCmd( 393 PMOS_COMMAND_BUFFER cmdBuffer, 394 PMHW_VDBOX_SURFACE_PARAMS params); 395 396 MOS_STATUS AddHcpEncodeSurfaceStateCmd( 397 PMOS_COMMAND_BUFFER cmdBuffer, 398 PMHW_VDBOX_SURFACE_PARAMS params); 399 400 MOS_STATUS AddHcpPipeBufAddrCmd( 401 PMOS_COMMAND_BUFFER cmdBuffer, 402 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS params); 403 404 MOS_STATUS AddHcpIndObjBaseAddrCmd( 405 PMOS_COMMAND_BUFFER cmdBuffer, 406 PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS params); 407 408 MOS_STATUS AddHcpDecodePicStateCmd( 409 PMOS_COMMAND_BUFFER cmdBuffer, 410 PMHW_VDBOX_HEVC_PIC_STATE params); 411 412 MOS_STATUS AddHcpEncodePicStateCmd( 413 PMOS_COMMAND_BUFFER cmdBuffer, 414 PMHW_VDBOX_HEVC_PIC_STATE params); 415 416 MOS_STATUS AddHcpTileStateCmd( 417 PMOS_COMMAND_BUFFER cmdBuffer, 418 PMHW_VDBOX_HEVC_TILE_STATE params); 419 420 MOS_STATUS AddHcpWeightOffsetStateCmd( 421 PMOS_COMMAND_BUFFER cmdBuffer, 422 PMHW_BATCH_BUFFER batchBuffer, 423 PMHW_VDBOX_HEVC_WEIGHTOFFSET_PARAMS params); 424 425 MOS_STATUS AddHcpFqmStateCmd( 426 PMOS_COMMAND_BUFFER cmdBuffer, 427 PMHW_VDBOX_QM_PARAMS params); 428 429 MOS_STATUS AddHcpDecodeSliceStateCmd( 430 PMOS_COMMAND_BUFFER cmdBuffer, 431 PMHW_VDBOX_HEVC_SLICE_STATE hevcSliceState); 432 433 MOS_STATUS AddHcpEncodeSliceStateCmd( 434 PMOS_COMMAND_BUFFER cmdBuffer, 435 PMHW_VDBOX_HEVC_SLICE_STATE hevcSliceState); 436 437 MOS_STATUS AddHcpPakInsertObject( 438 PMOS_COMMAND_BUFFER cmdBuffer, 439 PMHW_VDBOX_PAK_INSERT_PARAMS params); 440 441 MOS_STATUS AddHcpVp9PicStateCmd( 442 PMOS_COMMAND_BUFFER cmdBuffer, 443 PMHW_BATCH_BUFFER batchBuffer, 444 PMHW_VDBOX_VP9_PIC_STATE params); 445 446 MOS_STATUS AddHcpVp9PicStateEncCmd( 447 PMOS_COMMAND_BUFFER cmdBuffer, 448 PMHW_BATCH_BUFFER batchBuffer, 449 PMHW_VDBOX_VP9_ENCODE_PIC_STATE params); 450 451 MOS_STATUS AddHcpVp9SegmentStateCmd( 452 PMOS_COMMAND_BUFFER cmdBuffer, 453 PMHW_BATCH_BUFFER batchBuffer, 454 PMHW_VDBOX_VP9_SEGMENT_STATE params); 455 456 MOS_STATUS AddHcpHevcVp9RdoqStateCmd( 457 PMOS_COMMAND_BUFFER cmdBuffer, 458 PMHW_VDBOX_HEVC_PIC_STATE params); 459 460 //! 461 //! \brief Adds HCP tile coding command in command buffer for decoder 462 //! 463 //! \param [in] cmdBuffer 464 //! Command buffer to which HW command is added 465 //! \param [in] params 466 //! Params structure used to populate the HW command 467 //! 468 //! \return MOS_STATUS 469 //! MOS_STATUS_SUCCESS if success, else fail reason 470 //! 471 MOS_STATUS AddHcpDecodeTileCodingCmd( 472 PMOS_COMMAND_BUFFER cmdBuffer, 473 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 params); 474 475 //! 476 //! \brief Adds HCP tile coding command in command buffer for encoder 477 //! 478 //! \param [in] cmdBuffer 479 //! Command buffer to which HW command is added 480 //! \param [in] params 481 //! Params structure used to populate the HW command 482 //! 483 //! \return MOS_STATUS 484 //! MOS_STATUS_SUCCESS if success, else fail reason 485 //! 486 MOS_STATUS AddHcpEncodeTileCodingCmd( 487 PMOS_COMMAND_BUFFER cmdBuffer, 488 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 params); 489 490 MOS_STATUS AddHcpHevcPicBrcBuffer( 491 PMOS_RESOURCE hcpImgStates, 492 PMHW_VDBOX_HEVC_PIC_STATE hevcPicState); 493 494 MOS_STATUS GetOsResLaceOrAceOrRgbHistogramBufferSize( 495 uint32_t width, 496 uint32_t height, 497 uint32_t *size); 498 499 MOS_STATUS GetOsResStatisticsOutputBufferSize( 500 uint32_t width, 501 uint32_t height, 502 uint32_t *size); 503 504 //! 505 //! \brief Adds HCP tile coding command in command buffer 506 //! \details Client facing function to add HCP tile coding command in command buffer 507 //! 508 //! \param [in] cmdBuffer 509 //! Command buffer to which HW command is added 510 //! \param [in] params 511 //! Params structure used to populate the HW command 512 //! 513 //! \return MOS_STATUS 514 //! MOS_STATUS_SUCCESS if success, else fail reason 515 //! 516 MOS_STATUS AddHcpTileCodingCmd( 517 PMOS_COMMAND_BUFFER cmdBuffer, 518 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 params); 519 }; 520 521 #endif 522