1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 #if !defined (__GFX11_GB_REG_H__) 10 #define __GFX11_GB_REG_H__ 11 12 /* 13 * gfx11_gb_reg.h 14 * 15 * Register Spec Release: 1.0 16 * 17 */ 18 19 // 20 // Make sure the necessary endian defines are there. 21 // 22 #if defined(LITTLEENDIAN_CPU) 23 #elif defined(BIGENDIAN_CPU) 24 #else 25 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" 26 #endif 27 28 union GB_ADDR_CONFIG_GFX11 29 { 30 struct 31 { 32 #if defined(LITTLEENDIAN_CPU) 33 unsigned int NUM_PIPES : 3; 34 unsigned int PIPE_INTERLEAVE_SIZE : 3; 35 unsigned int MAX_COMPRESSED_FRAGS : 2; 36 unsigned int NUM_PKRS : 3; 37 unsigned int : 8; 38 unsigned int NUM_SHADER_ENGINES : 2; 39 unsigned int : 5; 40 unsigned int NUM_RB_PER_SE : 2; 41 unsigned int : 4; 42 #elif defined(BIGENDIAN_CPU) 43 unsigned int : 4; 44 unsigned int NUM_RB_PER_SE : 2; 45 unsigned int : 5; 46 unsigned int NUM_SHADER_ENGINES : 2; 47 unsigned int : 8; 48 unsigned int NUM_PKRS : 3; 49 unsigned int MAX_COMPRESSED_FRAGS : 2; 50 unsigned int PIPE_INTERLEAVE_SIZE : 3; 51 unsigned int NUM_PIPES : 3; 52 #endif 53 } bitfields, bits; 54 unsigned int u32All; 55 int i32All; 56 float f32All; 57 }; 58 59 #endif 60 61