1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 */
6
7 #ifndef __INPUT_SYSTEM_2401_PRIVATE_H_INCLUDED__
8 #define __INPUT_SYSTEM_2401_PRIVATE_H_INCLUDED__
9
10 #include "input_system_public.h"
11
12 #include "device_access.h" /* ia_css_device_load_uint32 */
13
14 #include "assert_support.h" /* assert */
15 #include "print_support.h" /* print */
16
17 /* Load the register value */
ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID,const hrt_address reg)18 static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID,
19 const hrt_address reg)
20 {
21 assert(ID < N_IBUF_CTRL_ID);
22 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
23 return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data));
24 }
25
26 /* Store a value to the register */
ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID,const hrt_address reg,const hrt_data value)27 static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID,
28 const hrt_address reg,
29 const hrt_data value)
30 {
31 assert(ID < N_IBUF_CTRL_ID);
32 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
33
34 ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
35 }
36
37 /* Get the state of the ibuf-controller process */
ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID,const u32 proc_id,ibuf_ctrl_proc_state_t * state)38 static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID,
39 const u32 proc_id,
40 ibuf_ctrl_proc_state_t *state)
41 {
42 hrt_address reg_bank_offset;
43
44 reg_bank_offset =
45 _IBUF_CNTRL_PROC_REG_ALIGN * (1 + proc_id);
46
47 state->num_items =
48 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE);
49
50 state->num_stores =
51 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_STORES_PER_FRAME);
52
53 state->dma_channel =
54 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CHANNEL);
55
56 state->dma_command =
57 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CMD);
58
59 state->ibuf_st_addr =
60 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_START_ADDRESS);
61
62 state->ibuf_stride =
63 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_STRIDE);
64
65 state->ibuf_end_addr =
66 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_END_ADDRESS);
67
68 state->dest_st_addr =
69 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_START_ADDRESS);
70
71 state->dest_stride =
72 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_STRIDE);
73
74 state->dest_end_addr =
75 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_END_ADDRESS);
76
77 state->sync_frame =
78 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SYNC_FRAME);
79
80 state->sync_command =
81 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_SYNC_CMD);
82
83 state->store_command =
84 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_STORE_CMD);
85
86 state->shift_returned_items =
87 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SHIFT_ITEMS);
88
89 state->elems_ibuf =
90 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_IBUF);
91
92 state->elems_dest =
93 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_DEST);
94
95 state->cur_stores =
96 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_STORES);
97
98 state->cur_acks =
99 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ACKS);
100
101 state->cur_s2m_ibuf_addr =
102 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_S2M_IBUF_ADDR);
103
104 state->cur_dma_ibuf_addr =
105 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_IBUF_ADDR);
106
107 state->cur_dma_dest_addr =
108 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_DEST_ADDR);
109
110 state->cur_isp_dest_addr =
111 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ISP_DEST_ADDR);
112
113 state->dma_cmds_send =
114 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND);
115
116 state->main_cntrl_state =
117 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_MAIN_CNTRL_STATE);
118
119 state->dma_sync_state =
120 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_SYNC_STATE);
121
122 state->isp_sync_state =
123 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE);
124 }
125
126 /* Get the ibuf-controller state. */
ibuf_ctrl_get_state(const ibuf_ctrl_ID_t ID,ibuf_ctrl_state_t * state)127 static inline void ibuf_ctrl_get_state(const ibuf_ctrl_ID_t ID,
128 ibuf_ctrl_state_t *state)
129 {
130 u32 i;
131
132 state->recalc_words =
133 ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS);
134 state->arbiters =
135 ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_ARBITERS_STATUS);
136
137 /*
138 * Get the values of the register-set per
139 * ibuf-controller process.
140 */
141 for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) {
142 ibuf_ctrl_get_proc_state(
143 ID,
144 i,
145 &state->proc_state[i]);
146 }
147 }
148
149 /* Dump the ibuf-controller state */
ibuf_ctrl_dump_state(const ibuf_ctrl_ID_t ID,ibuf_ctrl_state_t * state)150 static inline void ibuf_ctrl_dump_state(const ibuf_ctrl_ID_t ID,
151 ibuf_ctrl_state_t *state)
152 {
153 u32 i;
154
155 ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID,
156 state->recalc_words);
157 ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters);
158
159 /*
160 * Dump the values of the register-set per
161 * ibuf-controller process.
162 */
163 for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) {
164 ia_css_print("IBUF controller ID %d Process ID %d num_items 0x%x\n", ID, i,
165 state->proc_state[i].num_items);
166 ia_css_print("IBUF controller ID %d Process ID %d num_stores 0x%x\n", ID, i,
167 state->proc_state[i].num_stores);
168 ia_css_print("IBUF controller ID %d Process ID %d dma_channel 0x%x\n", ID, i,
169 state->proc_state[i].dma_channel);
170 ia_css_print("IBUF controller ID %d Process ID %d dma_command 0x%x\n", ID, i,
171 state->proc_state[i].dma_command);
172 ia_css_print("IBUF controller ID %d Process ID %d ibuf_st_addr 0x%x\n", ID, i,
173 state->proc_state[i].ibuf_st_addr);
174 ia_css_print("IBUF controller ID %d Process ID %d ibuf_stride 0x%x\n", ID, i,
175 state->proc_state[i].ibuf_stride);
176 ia_css_print("IBUF controller ID %d Process ID %d ibuf_end_addr 0x%x\n", ID, i,
177 state->proc_state[i].ibuf_end_addr);
178 ia_css_print("IBUF controller ID %d Process ID %d dest_st_addr 0x%x\n", ID, i,
179 state->proc_state[i].dest_st_addr);
180 ia_css_print("IBUF controller ID %d Process ID %d dest_stride 0x%x\n", ID, i,
181 state->proc_state[i].dest_stride);
182 ia_css_print("IBUF controller ID %d Process ID %d dest_end_addr 0x%x\n", ID, i,
183 state->proc_state[i].dest_end_addr);
184 ia_css_print("IBUF controller ID %d Process ID %d sync_frame 0x%x\n", ID, i,
185 state->proc_state[i].sync_frame);
186 ia_css_print("IBUF controller ID %d Process ID %d sync_command 0x%x\n", ID, i,
187 state->proc_state[i].sync_command);
188 ia_css_print("IBUF controller ID %d Process ID %d store_command 0x%x\n", ID, i,
189 state->proc_state[i].store_command);
190 ia_css_print("IBUF controller ID %d Process ID %d shift_returned_items 0x%x\n",
191 ID, i,
192 state->proc_state[i].shift_returned_items);
193 ia_css_print("IBUF controller ID %d Process ID %d elems_ibuf 0x%x\n", ID, i,
194 state->proc_state[i].elems_ibuf);
195 ia_css_print("IBUF controller ID %d Process ID %d elems_dest 0x%x\n", ID, i,
196 state->proc_state[i].elems_dest);
197 ia_css_print("IBUF controller ID %d Process ID %d cur_stores 0x%x\n", ID, i,
198 state->proc_state[i].cur_stores);
199 ia_css_print("IBUF controller ID %d Process ID %d cur_acks 0x%x\n", ID, i,
200 state->proc_state[i].cur_acks);
201 ia_css_print("IBUF controller ID %d Process ID %d cur_s2m_ibuf_addr 0x%x\n", ID,
202 i,
203 state->proc_state[i].cur_s2m_ibuf_addr);
204 ia_css_print("IBUF controller ID %d Process ID %d cur_dma_ibuf_addr 0x%x\n", ID,
205 i,
206 state->proc_state[i].cur_dma_ibuf_addr);
207 ia_css_print("IBUF controller ID %d Process ID %d cur_dma_dest_addr 0x%x\n", ID,
208 i,
209 state->proc_state[i].cur_dma_dest_addr);
210 ia_css_print("IBUF controller ID %d Process ID %d cur_isp_dest_addr 0x%x\n", ID,
211 i,
212 state->proc_state[i].cur_isp_dest_addr);
213 ia_css_print("IBUF controller ID %d Process ID %d dma_cmds_send 0x%x\n", ID, i,
214 state->proc_state[i].dma_cmds_send);
215 ia_css_print("IBUF controller ID %d Process ID %d main_cntrl_state 0x%x\n", ID,
216 i,
217 state->proc_state[i].main_cntrl_state);
218 ia_css_print("IBUF controller ID %d Process ID %d dma_sync_state 0x%x\n", ID, i,
219 state->proc_state[i].dma_sync_state);
220 ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i,
221 state->proc_state[i].isp_sync_state);
222 }
223 }
224
225 #endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */
226