1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
4  *
5  * Copyright 2020 NXP
6  *
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/kernel.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <linux/stmmac.h>
22 
23 #include "stmmac_platform.h"
24 
25 #define GPR_ENET_QOS_INTF_MODE_MASK	GENMASK(21, 16)
26 #define GPR_ENET_QOS_INTF_SEL_MII	(0x0 << 16)
27 #define GPR_ENET_QOS_INTF_SEL_RMII	(0x4 << 16)
28 #define GPR_ENET_QOS_INTF_SEL_RGMII	(0x1 << 16)
29 #define GPR_ENET_QOS_CLK_GEN_EN		(0x1 << 19)
30 #define GPR_ENET_QOS_CLK_TX_CLK_SEL	(0x1 << 20)
31 #define GPR_ENET_QOS_RGMII_EN		(0x1 << 21)
32 
33 #define MX93_GPR_ENET_QOS_INTF_MODE_MASK	GENMASK(3, 0)
34 #define MX93_GPR_ENET_QOS_INTF_MASK		GENMASK(3, 1)
35 #define MX93_GPR_ENET_QOS_INTF_SEL_MII		(0x0 << 1)
36 #define MX93_GPR_ENET_QOS_INTF_SEL_RMII		(0x4 << 1)
37 #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII	(0x1 << 1)
38 #define MX93_GPR_ENET_QOS_CLK_GEN_EN		(0x1 << 0)
39 #define MX93_GPR_ENET_QOS_CLK_SEL_MASK		BIT_MASK(0)
40 #define MX93_GPR_CLK_SEL_OFFSET			(4)
41 
42 #define DMA_BUS_MODE			0x00001000
43 #define DMA_BUS_MODE_SFT_RESET		(0x1 << 0)
44 #define RMII_RESET_SPEED		(0x3 << 14)
45 #define CTRL_SPEED_MASK			GENMASK(15, 14)
46 
47 struct imx_dwmac_ops {
48 	u32 addr_width;
49 	u32 flags;
50 	bool mac_rgmii_txclk_auto_adj;
51 
52 	int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
53 	int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat);
54 	void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode);
55 };
56 
57 struct imx_priv_data {
58 	struct device *dev;
59 	struct clk *clk_tx;
60 	struct clk *clk_mem;
61 	struct regmap *intf_regmap;
62 	u32 intf_reg_off;
63 	bool rmii_refclk_ext;
64 	void __iomem *base_addr;
65 
66 	const struct imx_dwmac_ops *ops;
67 	struct plat_stmmacenet_data *plat_dat;
68 };
69 
imx8mp_set_intf_mode(struct plat_stmmacenet_data * plat_dat)70 static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
71 {
72 	struct imx_priv_data *dwmac = plat_dat->bsp_priv;
73 	int val;
74 
75 	switch (plat_dat->mac_interface) {
76 	case PHY_INTERFACE_MODE_MII:
77 		val = GPR_ENET_QOS_INTF_SEL_MII;
78 		break;
79 	case PHY_INTERFACE_MODE_RMII:
80 		val = GPR_ENET_QOS_INTF_SEL_RMII;
81 		val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL);
82 		break;
83 	case PHY_INTERFACE_MODE_RGMII:
84 	case PHY_INTERFACE_MODE_RGMII_ID:
85 	case PHY_INTERFACE_MODE_RGMII_RXID:
86 	case PHY_INTERFACE_MODE_RGMII_TXID:
87 		val = GPR_ENET_QOS_INTF_SEL_RGMII |
88 		      GPR_ENET_QOS_RGMII_EN;
89 		break;
90 	default:
91 		pr_debug("imx dwmac doesn't support %d interface\n",
92 			 plat_dat->mac_interface);
93 		return -EINVAL;
94 	}
95 
96 	val |= GPR_ENET_QOS_CLK_GEN_EN;
97 	return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
98 				  GPR_ENET_QOS_INTF_MODE_MASK, val);
99 };
100 
101 static int
imx8dxl_set_intf_mode(struct plat_stmmacenet_data * plat_dat)102 imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
103 {
104 	int ret = 0;
105 
106 	/* TBD: depends on imx8dxl scu interfaces to be upstreamed */
107 	return ret;
108 }
109 
imx93_set_intf_mode(struct plat_stmmacenet_data * plat_dat)110 static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
111 {
112 	struct imx_priv_data *dwmac = plat_dat->bsp_priv;
113 	int val, ret;
114 
115 	switch (plat_dat->mac_interface) {
116 	case PHY_INTERFACE_MODE_MII:
117 		val = MX93_GPR_ENET_QOS_INTF_SEL_MII;
118 		break;
119 	case PHY_INTERFACE_MODE_RMII:
120 		if (dwmac->rmii_refclk_ext) {
121 			ret = regmap_clear_bits(dwmac->intf_regmap,
122 						dwmac->intf_reg_off +
123 						MX93_GPR_CLK_SEL_OFFSET,
124 						MX93_GPR_ENET_QOS_CLK_SEL_MASK);
125 			if (ret)
126 				return ret;
127 		}
128 		val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
129 		break;
130 	case PHY_INTERFACE_MODE_RGMII:
131 	case PHY_INTERFACE_MODE_RGMII_ID:
132 	case PHY_INTERFACE_MODE_RGMII_RXID:
133 	case PHY_INTERFACE_MODE_RGMII_TXID:
134 		val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII;
135 		break;
136 	default:
137 		dev_dbg(dwmac->dev, "imx dwmac doesn't support %d interface\n",
138 			 plat_dat->mac_interface);
139 		return -EINVAL;
140 	}
141 
142 	val |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
143 	return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
144 				  MX93_GPR_ENET_QOS_INTF_MODE_MASK, val);
145 };
146 
imx_dwmac_clks_config(void * priv,bool enabled)147 static int imx_dwmac_clks_config(void *priv, bool enabled)
148 {
149 	struct imx_priv_data *dwmac = priv;
150 	int ret = 0;
151 
152 	if (enabled) {
153 		ret = clk_prepare_enable(dwmac->clk_mem);
154 		if (ret) {
155 			dev_err(dwmac->dev, "mem clock enable failed\n");
156 			return ret;
157 		}
158 
159 		ret = clk_prepare_enable(dwmac->clk_tx);
160 		if (ret) {
161 			dev_err(dwmac->dev, "tx clock enable failed\n");
162 			clk_disable_unprepare(dwmac->clk_mem);
163 			return ret;
164 		}
165 	} else {
166 		clk_disable_unprepare(dwmac->clk_tx);
167 		clk_disable_unprepare(dwmac->clk_mem);
168 	}
169 
170 	return ret;
171 }
172 
imx_dwmac_init(struct platform_device * pdev,void * priv)173 static int imx_dwmac_init(struct platform_device *pdev, void *priv)
174 {
175 	struct plat_stmmacenet_data *plat_dat;
176 	struct imx_priv_data *dwmac = priv;
177 	int ret;
178 
179 	plat_dat = dwmac->plat_dat;
180 
181 	if (dwmac->ops->set_intf_mode) {
182 		ret = dwmac->ops->set_intf_mode(plat_dat);
183 		if (ret)
184 			return ret;
185 	}
186 
187 	return 0;
188 }
189 
imx_dwmac_exit(struct platform_device * pdev,void * priv)190 static void imx_dwmac_exit(struct platform_device *pdev, void *priv)
191 {
192 	/* nothing to do now */
193 }
194 
imx_dwmac_fix_speed(void * priv,unsigned int speed,unsigned int mode)195 static void imx_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode)
196 {
197 	struct plat_stmmacenet_data *plat_dat;
198 	struct imx_priv_data *dwmac = priv;
199 	long rate;
200 	int err;
201 
202 	plat_dat = dwmac->plat_dat;
203 
204 	if (dwmac->ops->mac_rgmii_txclk_auto_adj ||
205 	    (plat_dat->mac_interface == PHY_INTERFACE_MODE_RMII) ||
206 	    (plat_dat->mac_interface == PHY_INTERFACE_MODE_MII))
207 		return;
208 
209 	rate = rgmii_clock(speed);
210 	if (rate < 0) {
211 		dev_err(dwmac->dev, "invalid speed %u\n", speed);
212 		return;
213 	}
214 
215 	err = clk_set_rate(dwmac->clk_tx, rate);
216 	if (err < 0)
217 		dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
218 }
219 
imx93_dwmac_fix_speed(void * priv,unsigned int speed,unsigned int mode)220 static void imx93_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode)
221 {
222 	struct imx_priv_data *dwmac = priv;
223 	unsigned int iface;
224 	int ctrl, old_ctrl;
225 
226 	imx_dwmac_fix_speed(priv, speed, mode);
227 
228 	if (!dwmac || mode != MLO_AN_FIXED)
229 		return;
230 
231 	if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
232 		return;
233 
234 	iface &= MX93_GPR_ENET_QOS_INTF_MASK;
235 	if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
236 		return;
237 
238 	old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
239 	ctrl = old_ctrl & ~CTRL_SPEED_MASK;
240 	regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
241 			   MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
242 	writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
243 
244 	 /* Ensure the settings for CTRL are applied. */
245 	readl(dwmac->base_addr + MAC_CTRL_REG);
246 
247 	usleep_range(10, 20);
248 	iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
249 	regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
250 			   MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
251 
252 	writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG);
253 }
254 
imx_dwmac_mx93_reset(void * priv,void __iomem * ioaddr)255 static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
256 {
257 	struct plat_stmmacenet_data *plat_dat = priv;
258 	u32 value = readl(ioaddr + DMA_BUS_MODE);
259 
260 	/* DMA SW reset */
261 	value |= DMA_BUS_MODE_SFT_RESET;
262 	writel(value, ioaddr + DMA_BUS_MODE);
263 
264 	if (plat_dat->mac_interface == PHY_INTERFACE_MODE_RMII) {
265 		usleep_range(100, 200);
266 		writel(RMII_RESET_SPEED, ioaddr + MAC_CTRL_REG);
267 	}
268 
269 	return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
270 				 !(value & DMA_BUS_MODE_SFT_RESET),
271 				 10000, 1000000);
272 }
273 
274 static int
imx_dwmac_parse_dt(struct imx_priv_data * dwmac,struct device * dev)275 imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
276 {
277 	struct device_node *np = dev->of_node;
278 	int err = 0;
279 
280 	dwmac->rmii_refclk_ext = of_property_read_bool(np, "snps,rmii_refclk_ext");
281 
282 	dwmac->clk_tx = devm_clk_get(dev, "tx");
283 	if (IS_ERR(dwmac->clk_tx)) {
284 		dev_err(dev, "failed to get tx clock\n");
285 		return PTR_ERR(dwmac->clk_tx);
286 	}
287 
288 	dwmac->clk_mem = NULL;
289 
290 	if (of_machine_is_compatible("fsl,imx8dxl") ||
291 	    of_machine_is_compatible("fsl,imx93")) {
292 		dwmac->clk_mem = devm_clk_get(dev, "mem");
293 		if (IS_ERR(dwmac->clk_mem)) {
294 			dev_err(dev, "failed to get mem clock\n");
295 			return PTR_ERR(dwmac->clk_mem);
296 		}
297 	}
298 
299 	if (of_machine_is_compatible("fsl,imx8mp") ||
300 	    of_machine_is_compatible("fsl,imx93")) {
301 		/* Binding doc describes the propety:
302 		 * is required by i.MX8MP, i.MX93.
303 		 * is optinoal for i.MX8DXL.
304 		 */
305 		dwmac->intf_regmap =
306 			syscon_regmap_lookup_by_phandle_args(np, "intf_mode", 1,
307 							     &dwmac->intf_reg_off);
308 		if (IS_ERR(dwmac->intf_regmap))
309 			return PTR_ERR(dwmac->intf_regmap);
310 	}
311 
312 	return err;
313 }
314 
imx_dwmac_probe(struct platform_device * pdev)315 static int imx_dwmac_probe(struct platform_device *pdev)
316 {
317 	struct plat_stmmacenet_data *plat_dat;
318 	struct stmmac_resources stmmac_res;
319 	struct imx_priv_data *dwmac;
320 	const struct imx_dwmac_ops *data;
321 	int ret;
322 
323 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
324 	if (ret)
325 		return ret;
326 
327 	dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
328 	if (!dwmac)
329 		return -ENOMEM;
330 
331 	plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
332 	if (IS_ERR(plat_dat))
333 		return PTR_ERR(plat_dat);
334 
335 	data = of_device_get_match_data(&pdev->dev);
336 	if (!data) {
337 		dev_err(&pdev->dev, "failed to get match data\n");
338 		return -EINVAL;
339 	}
340 
341 	dwmac->ops = data;
342 	dwmac->dev = &pdev->dev;
343 
344 	ret = imx_dwmac_parse_dt(dwmac, &pdev->dev);
345 	if (ret) {
346 		dev_err(&pdev->dev, "failed to parse OF data\n");
347 		return ret;
348 	}
349 
350 	if (data->flags & STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY)
351 		plat_dat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY;
352 
353 	/* Default TX Q0 to use TSO and rest TXQ for TBS */
354 	for (int i = 1; i < plat_dat->tx_queues_to_use; i++)
355 		plat_dat->tx_queues_cfg[i].tbs_en = 1;
356 
357 	plat_dat->host_dma_width = dwmac->ops->addr_width;
358 	plat_dat->init = imx_dwmac_init;
359 	plat_dat->exit = imx_dwmac_exit;
360 	plat_dat->clks_config = imx_dwmac_clks_config;
361 	plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
362 	plat_dat->bsp_priv = dwmac;
363 	dwmac->plat_dat = plat_dat;
364 	dwmac->base_addr = stmmac_res.addr;
365 
366 	ret = imx_dwmac_clks_config(dwmac, true);
367 	if (ret)
368 		return ret;
369 
370 	ret = imx_dwmac_init(pdev, dwmac);
371 	if (ret)
372 		goto err_dwmac_init;
373 
374 	if (dwmac->ops->fix_mac_speed)
375 		plat_dat->fix_mac_speed = dwmac->ops->fix_mac_speed;
376 	dwmac->plat_dat->fix_soc_reset = dwmac->ops->fix_soc_reset;
377 
378 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
379 	if (ret)
380 		goto err_drv_probe;
381 
382 	return 0;
383 
384 err_drv_probe:
385 	imx_dwmac_exit(pdev, plat_dat->bsp_priv);
386 err_dwmac_init:
387 	imx_dwmac_clks_config(dwmac, false);
388 	return ret;
389 }
390 
391 static struct imx_dwmac_ops imx8mp_dwmac_data = {
392 	.addr_width = 34,
393 	.mac_rgmii_txclk_auto_adj = false,
394 	.set_intf_mode = imx8mp_set_intf_mode,
395 	.flags = STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY,
396 };
397 
398 static struct imx_dwmac_ops imx8dxl_dwmac_data = {
399 	.addr_width = 32,
400 	.mac_rgmii_txclk_auto_adj = true,
401 	.set_intf_mode = imx8dxl_set_intf_mode,
402 };
403 
404 static struct imx_dwmac_ops imx93_dwmac_data = {
405 	.addr_width = 32,
406 	.mac_rgmii_txclk_auto_adj = true,
407 	.set_intf_mode = imx93_set_intf_mode,
408 	.fix_soc_reset = imx_dwmac_mx93_reset,
409 	.fix_mac_speed = imx93_dwmac_fix_speed,
410 };
411 
412 static const struct of_device_id imx_dwmac_match[] = {
413 	{ .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },
414 	{ .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },
415 	{ .compatible = "nxp,imx93-dwmac-eqos", .data = &imx93_dwmac_data },
416 	{ }
417 };
418 MODULE_DEVICE_TABLE(of, imx_dwmac_match);
419 
420 static struct platform_driver imx_dwmac_driver = {
421 	.probe  = imx_dwmac_probe,
422 	.remove = stmmac_pltfr_remove,
423 	.driver = {
424 		.name           = "imx-dwmac",
425 		.pm		= &stmmac_pltfr_pm_ops,
426 		.of_match_table = imx_dwmac_match,
427 	},
428 };
429 module_platform_driver(imx_dwmac_driver);
430 
431 MODULE_AUTHOR("NXP");
432 MODULE_DESCRIPTION("NXP imx8 DWMAC Specific Glue layer");
433 MODULE_LICENSE("GPL v2");
434