1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_fs.h"
25 #include "brw_fs_live_variables.h"
26 #include "brw_cfg.h"
27
28 /** @file
29 *
30 * Dataflow-aware dead code elimination.
31 *
32 * Walks the instruction list from the bottom, removing instructions that
33 * have results that both aren't used in later blocks and haven't been read
34 * yet in the tail end of this block.
35 */
36
37 using namespace brw;
38
39 /**
40 * Is it safe to eliminate the instruction?
41 */
42 static bool
can_eliminate(const intel_device_info * devinfo,const fs_inst * inst,BITSET_WORD * flag_live)43 can_eliminate(const intel_device_info *devinfo, const fs_inst *inst,
44 BITSET_WORD *flag_live)
45 {
46 return !inst->is_control_flow() &&
47 !inst->has_side_effects() &&
48 !(flag_live[0] & inst->flags_written(devinfo)) &&
49 !inst->writes_accumulator;
50 }
51
52 /**
53 * Is it safe to omit the write, making the destination ARF null?
54 */
55 static bool
can_omit_write(const fs_inst * inst)56 can_omit_write(const fs_inst *inst)
57 {
58 switch (inst->opcode) {
59 case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL:
60 return true;
61 default:
62 /* We can eliminate the destination write for ordinary instructions,
63 * but not most SENDs.
64 */
65 if (inst->opcode < NUM_BRW_OPCODES && inst->mlen == 0)
66 return true;
67
68 /* It might not be safe for other virtual opcodes. */
69 return false;
70 }
71 }
72
73 static bool
can_eliminate_conditional_mod(const intel_device_info * devinfo,const fs_inst * inst,BITSET_WORD * flag_live)74 can_eliminate_conditional_mod(const intel_device_info *devinfo,
75 const fs_inst *inst, BITSET_WORD *flag_live)
76 {
77 /* CMP, CMPN, and CSEL must have a conditional modifier because the
78 * modifier determines what the instruction does. SEL with a conditional
79 * modifier has a special meaning (i.e., makes the instruction behave as
80 * MIN or MAX), so those cannot be eliminated either.
81 */
82 if (inst->conditional_mod == BRW_CONDITIONAL_NONE ||
83 inst->opcode == BRW_OPCODE_CMP ||
84 inst->opcode == BRW_OPCODE_CMPN ||
85 inst->opcode == BRW_OPCODE_SEL ||
86 inst->opcode == BRW_OPCODE_CSEL) {
87 return false;
88 }
89
90 /* The conditional modifier can be eliminated if none of the flags written
91 * are read.
92 */
93 const BITSET_WORD flags_written = inst->flags_written(devinfo);
94
95 assert(flags_written != 0);
96 return (flag_live[0] & flags_written) == 0;
97 }
98
99 bool
brw_fs_opt_dead_code_eliminate(fs_visitor & s)100 brw_fs_opt_dead_code_eliminate(fs_visitor &s)
101 {
102 const intel_device_info *devinfo = s.devinfo;
103
104 bool progress = false;
105
106 const fs_live_variables &live_vars = s.live_analysis.require();
107 int num_vars = live_vars.num_vars;
108 BITSET_WORD *live = rzalloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));
109 BITSET_WORD *flag_live = rzalloc_array(NULL, BITSET_WORD, 1);
110
111 foreach_block_reverse_safe(block, s.cfg) {
112 memcpy(live, live_vars.block_data[block->num].liveout,
113 sizeof(BITSET_WORD) * BITSET_WORDS(num_vars));
114 memcpy(flag_live, live_vars.block_data[block->num].flag_liveout,
115 sizeof(BITSET_WORD));
116
117 foreach_inst_in_block_reverse_safe(fs_inst, inst, block) {
118 if (inst->dst.file == VGRF) {
119 const unsigned var = live_vars.var_from_reg(inst->dst);
120 bool result_live = false;
121
122 for (unsigned i = 0; i < regs_written(inst); i++)
123 result_live |= BITSET_TEST(live, var + i);
124
125 if (!result_live &&
126 (can_omit_write(inst) || can_eliminate(devinfo, inst, flag_live))) {
127 inst->dst = brw_reg(spread(retype(brw_null_reg(), inst->dst.type),
128 inst->dst.stride));
129 progress = true;
130 }
131 }
132
133 if (can_eliminate_conditional_mod(devinfo, inst, flag_live))
134 inst->conditional_mod = BRW_CONDITIONAL_NONE;
135
136 if (inst->dst.is_null() && can_eliminate(devinfo, inst, flag_live) &&
137 !(inst->opcode == BRW_OPCODE_NOP &&
138 exec_list_is_singular(&block->instructions))) {
139 inst->opcode = BRW_OPCODE_NOP;
140 progress = true;
141 }
142
143 if (inst->dst.file == VGRF) {
144 if (!inst->is_partial_write()) {
145 const unsigned var = live_vars.var_from_reg(inst->dst);
146 for (unsigned i = 0; i < regs_written(inst); i++) {
147 BITSET_CLEAR(live, var + i);
148 }
149 }
150 }
151
152 if (!inst->predicate && inst->exec_size >= 8)
153 flag_live[0] &= ~inst->flags_written(devinfo);
154
155 if (inst->opcode == BRW_OPCODE_NOP) {
156 inst->remove(block, true);
157 continue;
158 }
159
160 for (int i = 0; i < inst->sources; i++) {
161 if (inst->src[i].file == VGRF) {
162 int var = live_vars.var_from_reg(inst->src[i]);
163
164 for (unsigned j = 0; j < regs_read(inst, i); j++) {
165 BITSET_SET(live, var + j);
166 }
167 }
168 }
169
170 flag_live[0] |= inst->flags_read(devinfo);
171 }
172 }
173
174 s.cfg->adjust_block_ips();
175
176 ralloc_free(live);
177 ralloc_free(flag_live);
178
179 if (progress)
180 s.invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
181
182 return progress;
183 }
184