"59239bc96a73f430bbcce1d2e7f46fb72ed68048" (history) in projects: XiangShan

Searched hist:"59239 bc96a73f430bbcce1d2e7f46fb72ed68048" (Results 1 – 4 of 4) sorted by relevance

/XiangShan/src/main/scala/system/
H A D	SoC.scala	`diff 59239bc96a73f430bbcce1d2e7f46fb72ed68048 Wed Dec 01 13:44:10 CET 2021 Jiawei Lin <[email protected]> Change L2 to 4 banks (#1256) * misc: soc timing optimize * XSTile: insert buffer between L1Dcache and L2 * Bump huancun * Change L2 to 4 banks * Adjust buffers * Add more buffers for peripheral port * Fix submodule version`
/XiangShan/src/main/scala/top/
H A D	Top.scala	`diff 59239bc96a73f430bbcce1d2e7f46fb72ed68048 Wed Dec 01 13:44:10 CET 2021 Jiawei Lin <[email protected]> Change L2 to 4 banks (#1256) * misc: soc timing optimize * XSTile: insert buffer between L1Dcache and L2 * Bump huancun * Change L2 to 4 banks * Adjust buffers * Add more buffers for peripheral port * Fix submodule version`
H A D	Configs.scala	`diff 59239bc96a73f430bbcce1d2e7f46fb72ed68048 Wed Dec 01 13:44:10 CET 2021 Jiawei Lin <[email protected]> Change L2 to 4 banks (#1256) * misc: soc timing optimize * XSTile: insert buffer between L1Dcache and L2 * Bump huancun * Change L2 to 4 banks * Adjust buffers * Add more buffers for peripheral port * Fix submodule version`
/XiangShan/src/main/scala/xiangshan/
H A D	XSTile.scala	`diff 59239bc96a73f430bbcce1d2e7f46fb72ed68048 Wed Dec 01 13:44:10 CET 2021 Jiawei Lin <[email protected]> Change L2 to 4 banks (#1256) * misc: soc timing optimize * XSTile: insert buffer between L1Dcache and L2 * Bump huancun * Change L2 to 4 banks * Adjust buffers * Add more buffers for peripheral port * Fix submodule version`