Home
last modified time | relevance | path

Searched hist:"2993 c5ecece73b73073301e23435ca1b763d0b5f" (Results 1 – 4 of 4) sorted by relevance

/XiangShan/src/main/scala/utils/
H A DVerilogAXI4Record.scala2993c5ecece73b73073301e23435ca1b763d0b5f Thu Jun 27 15:27:49 CEST 2024 Haojin Tang <[email protected]> Top: use VerilogAXI4Record instead of `sed` to handle amba signal names

/XiangShan/src/test/scala/top/
H A DSimTop.scaladiff 2993c5ecece73b73073301e23435ca1b763d0b5f Thu Jun 27 15:27:49 CEST 2024 Haojin Tang <[email protected]> Top: use VerilogAXI4Record instead of `sed` to handle amba signal names

/XiangShan/src/main/scala/top/
H A DTop.scaladiff 2993c5ecece73b73073301e23435ca1b763d0b5f Thu Jun 27 15:27:49 CEST 2024 Haojin Tang <[email protected]> Top: use VerilogAXI4Record instead of `sed` to handle amba signal names

/XiangShan/
H A DMakefilediff 2993c5ecece73b73073301e23435ca1b763d0b5f Thu Jun 27 15:27:49 CEST 2024 Haojin Tang <[email protected]> Top: use VerilogAXI4Record instead of `sed` to handle amba signal names