Searched hist:"1 eae6a3f990c4840bbce3f033cc38efd032a7af6" (Results 1 – 2 of 2) sorted by relevance
| /XiangShan/src/main/scala/xiangshan/ |
| H A D | package.scala | diff 1eae6a3f990c4840bbce3f033cc38efd032a7af6 Thu Oct 03 09:25:33 CEST 2024 happy-lx <[email protected]> fix(cmo): support DiffTest with cbo.inval instruction (#3662)
When the DUT executes a cbo.inval, a set in Difftest is used to record
its cacheline address.
Later, if there is a data mismatch between DUT and GoldenMem in the
address space operated by the cbo.inval instruction, the Pmem of REF and
GoldenMem will be directly updated using the data of DUT.
|
| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | StoreQueue.scala | diff 1eae6a3f990c4840bbce3f033cc38efd032a7af6 Thu Oct 03 09:25:33 CEST 2024 happy-lx <[email protected]> fix(cmo): support DiffTest with cbo.inval instruction (#3662)
When the DUT executes a cbo.inval, a set in Difftest is used to record
its cacheline address.
Later, if there is a data mismatch between DUT and GoldenMem in the
address space operated by the cbo.inval instruction, the Pmem of REF and
GoldenMem will be directly updated using the data of DUT.
|